Luis Silvio Cordova Rivadeneira / Mbed 2 deprecated mpu9250

Ejemplo de uso del MPU9250 por puerto I2C

Dependencies:   mbed

mpu9250Define.h@0:cecf4940adf1, 2015-10-25 (annotated)

Committer:
a0074639
Date:
Sun Oct 25 15:28:55 2015 +0000
Revision:
0:cecf4940adf1
comfirmed it works well

Who changed what in which revision?

UserRevisionLine numberNew contents of line
a0074639 0:cecf4940adf1 1 #ifndef MPU9250DEFINE_H
a0074639 0:cecf4940adf1 2 #define MPU9250DEFINE_H
a0074639 0:cecf4940adf1 3
a0074639 0:cecf4940adf1 4 /*-bit-*/
a0074639 0:cecf4940adf1 5 #define BIT_1 (1)
a0074639 0:cecf4940adf1 6 #define BIT_2 (2)
a0074639 0:cecf4940adf1 7 #define BIT_3 (3)
a0074639 0:cecf4940adf1 8 #define BIT_4 (4)
a0074639 0:cecf4940adf1 9 #define BIT_5 (5)
a0074639 0:cecf4940adf1 10 #define BIT_6 (6)
a0074639 0:cecf4940adf1 11
a0074639 0:cecf4940adf1 12 /*-send command-*/
a0074639 0:cecf4940adf1 13 #define CLEAR_COMMAND (0x00)
a0074639 0:cecf4940adf1 14
a0074639 0:cecf4940adf1 15 #define X_AXIS (1)
a0074639 0:cecf4940adf1 16 #define Y_AXIS (2)
a0074639 0:cecf4940adf1 17 #define Z_AXIS (5)
a0074639 0:cecf4940adf1 18 #define ALL_AXIS (X_AXIS+Y_AXIS+Z_AXIS)
a0074639 0:cecf4940adf1 19
a0074639 0:cecf4940adf1 20 /*-MPU-9150 address-*/
a0074639 0:cecf4940adf1 21 #define MPU9250_ADDRESS (0x68<<1) // 0b1101000 AD0=L
a0074639 0:cecf4940adf1 22
a0074639 0:cecf4940adf1 23 /*-MPU-9150 register-*/ //| Bit7 | Bit6 | Bit5 | Bit4 | Bit3 | Bit2 | Bit1 | Bit0 |
a0074639 0:cecf4940adf1 24 #define SELF_TEST_X_GYRO (0x00)
a0074639 0:cecf4940adf1 25 #define SELF_TEST_Y_GYRO (0x01)
a0074639 0:cecf4940adf1 26 #define SELF_TEST_Z_GYRO (0x02)
a0074639 0:cecf4940adf1 27 #define SELF_TEST_X_ACCEL (0x0D) // R/W //| XA_TEST[4-2] | XG_TEST[4-0] |
a0074639 0:cecf4940adf1 28 #define SELF_TEST_Y_ACCEL (0x0E) // R/W //| YA_TEST[4-2] | YG_TEST[4-0] |
a0074639 0:cecf4940adf1 29 #define SELE_TEST_Z_ACCEL (0x0F) // R/W //| ZA_TEST[4-2] | ZA_TEST[4-0] |
a0074639 0:cecf4940adf1 30
a0074639 0:cecf4940adf1 31 #define SELF_TEST_A (0x10) // R/W //| RESERVED | XA_TEST[1-0]| YA_TEST[1-0]| ZA_TEST[1-0]|
a0074639 0:cecf4940adf1 32 #define XG_OFFSET_H (0x13) // User-defined trim values for gyroscope
a0074639 0:cecf4940adf1 33 #define XG_OFFSET_L (0x14)
a0074639 0:cecf4940adf1 34 #define YG_OFFSET_H (0x15)
a0074639 0:cecf4940adf1 35 #define YG_OFFSET_L (0x16)
a0074639 0:cecf4940adf1 36 #define ZG_OFFSET_H (0x17)
a0074639 0:cecf4940adf1 37 #define ZG_OFFSET_L (0x18)
a0074639 0:cecf4940adf1 38 #define SMPLRT_DIV (0x19) // R/W //| SMPLRT_DIV[7:0] |
a0074639 0:cecf4940adf1 39 #define CONFIG (0x1A) // R/W //| - | - | EXT_SYNC_SET[2:0] | DLPE_CFG[2:0] |
a0074639 0:cecf4940adf1 40 #define GYRO_CONFIG (0x1B) // R/W //| XG_ST| YG_ST| ZG_ST| FS_SEL[1:0] | - | - | - |
a0074639 0:cecf4940adf1 41 #define ACCEL_CONFIG (0x1C) // R/W //| XA_ST| YA_ST| ZA_ST| AFS_SEL[1:0]| - |
a0074639 0:cecf4940adf1 42 #define ACCEL_CONFIG2 (0x1D)
a0074639 0:cecf4940adf1 43 #define LP_ACCEL_ODR (0x1E)
a0074639 0:cecf4940adf1 44 #define WOM_THR (0x1F)
a0074639 0:cecf4940adf1 45
a0074639 0:cecf4940adf1 46 #define MOT_DUR (0x20) // Duration counter threshold for motion interrupt generation, 1 kHz rate, LSB = 1 ms
a0074639 0:cecf4940adf1 47 #define ZMOT_THR (0x21) // Zero-motion detection threshold bits [7:0]
a0074639 0:cecf4940adf1 48 #define ZRMOT_DUR (0x22) // Duration counter threshold for zero motion interrupt generation, 16 Hz rate, LSB = 64 ms
a0074639 0:cecf4940adf1 49
a0074639 0:cecf4940adf1 50 #define FIFO_EN (0x23) // R/W //| TEMP_FIFO_EN | XG_FIFO_EN | YG_FIFO_EN | ZG_FIFO_EN | ACCEL_FIFO_EN | SLV2_FIFO_EN | SLV1_FIFO_EN | SLV0_FIFO_EN |
a0074639 0:cecf4940adf1 51 #define I2C_MST_CTRL (0x24) // R/W //| MULT_MST_EN | WAIT_FOR_ES | SLV_3_FIFO_EN | I2C_MST_P_NSR | I2C_MST_CLK[3:0] |
a0074639 0:cecf4940adf1 52 #define I2C_SLV0_ADDR (0x25) // R/W //| I2C_SLV0_RW | I2C_SLV0_ADDR[6:0] |
a0074639 0:cecf4940adf1 53 #define I2C_SLV0_REG (0x26) // R/W //| I2C_SLV0_REG[7:0] |
a0074639 0:cecf4940adf1 54 #define I2C_SLV0_CTRL (0x27) // R/W //| I2C_SLV0_EN | I2C_SLV0_BYTE_SW | I2C_SLV0_REG_DIS | I2C_SLV0_GRP | I2C_SLV0_LEN[3:0] |
a0074639 0:cecf4940adf1 55 #define I2C_SLV1_ADDR (0x28) // R/W
a0074639 0:cecf4940adf1 56 #define I2C_SLV1_REG (0x29) // R/W
a0074639 0:cecf4940adf1 57 #define I2C_SLV1_CTRL (0x2A) // R/W
a0074639 0:cecf4940adf1 58 #define I2C_SLV2_ADDR (0x2B) // R/W
a0074639 0:cecf4940adf1 59 #define I2C_SLV2_REG (0x2C) // R/W
a0074639 0:cecf4940adf1 60 #define I2C_SLV2_CTRL (0x2D) // R/W
a0074639 0:cecf4940adf1 61 #define I2C_SLV3_ADDR (0x2E) // R/W
a0074639 0:cecf4940adf1 62 #define I2C_SLV3_REG (0x2F) // R/W
a0074639 0:cecf4940adf1 63 #define I2C_SLV3_CTRL (0x30) // R/W
a0074639 0:cecf4940adf1 64 #define I2C_SLV4_ADDR (0x31) // R/W
a0074639 0:cecf4940adf1 65 #define I2C_SLV4_REG (0x32) // R/W
a0074639 0:cecf4940adf1 66 #define I2C_SLV4_DO (0x33) // R/W
a0074639 0:cecf4940adf1 67 #define I2C_SLV4_CTRL (0x34) // R/W
a0074639 0:cecf4940adf1 68 #define I2C_SLV4_DI (0x35) // R
a0074639 0:cecf4940adf1 69
a0074639 0:cecf4940adf1 70 #define I2C_MST_STATUS (0x36) // R
a0074639 0:cecf4940adf1 71 #define INT_PIN_CFG (0x37) // R/W // This register configures the behavior of the interrupt signals at the INT pins.
a0074639 0:cecf4940adf1 72 #define INT_ENBLE (0x38) // R/W
a0074639 0:cecf4940adf1 73 #define DMP_INT_STATUS (0x39) // Check DMP interrupt
a0074639 0:cecf4940adf1 74 #define INT_STATUS (0x3A) // R
a0074639 0:cecf4940adf1 75
a0074639 0:cecf4940adf1 76 #define ACCEL_XOUT_H (0x3B) // R //ACCEL_XOUT[15:8]
a0074639 0:cecf4940adf1 77 #define ACCEL_XOUT_L (0x3C) // R //ACCEL_XOUT[7:0]
a0074639 0:cecf4940adf1 78 #define ACCEL_YOUT_H (0x3D) // R //ACCEL_YOUT[15:8]
a0074639 0:cecf4940adf1 79 #define ACCEL_YOUT_L (0x3E) // R //ACCEL_YOUT[7:0]
a0074639 0:cecf4940adf1 80 #define ACCEL_ZOUT_H (0x3F) // R //ACCEL_ZOUT[15:8]
a0074639 0:cecf4940adf1 81 #define ACCEL_ZOUT_L (0x40) // R //ACCEL_ZOUT[7:0]
a0074639 0:cecf4940adf1 82
a0074639 0:cecf4940adf1 83 #define TEMP_OUT_H (0x41) // R
a0074639 0:cecf4940adf1 84 #define TEMP_OUT_L (0x42) // R
a0074639 0:cecf4940adf1 85
a0074639 0:cecf4940adf1 86 #define GYRO_XOUT_H (0x43) // R //GYRO_XOUT[15:8]
a0074639 0:cecf4940adf1 87 #define GYRO_XOUT_L (0x44) // R //GYRO_XOUT[7:0]
a0074639 0:cecf4940adf1 88 #define GYRO_YOUT_H (0x45) // R //GYRO_YOUT[15:8]
a0074639 0:cecf4940adf1 89 #define GYRO_YOUT_L (0x46) // R //GYRO_YOUT[7:0]
a0074639 0:cecf4940adf1 90 #define GYRO_ZOUT_H (0x47) // R //GYRO_ZOUT[15:8]
a0074639 0:cecf4940adf1 91 #define GYRO_ZOUT_L (0x48) // R //GYRO_ZOUT[7:0]
a0074639 0:cecf4940adf1 92
a0074639 0:cecf4940adf1 93 #define EXT_SENS_DATA_00 (0x49) // R
a0074639 0:cecf4940adf1 94 #define EXT_SENS_DATA_01 (0x4A) // R
a0074639 0:cecf4940adf1 95 #define EXT_SENS_DATA_02 (0x4B) // R
a0074639 0:cecf4940adf1 96 #define EXT_SENS_DATA_03 (0x4C) // R
a0074639 0:cecf4940adf1 97 #define EXT_SENS_DATA_04 (0x4D) // R
a0074639 0:cecf4940adf1 98 #define EXT_SENS_DATA_05 (0x4E) // R
a0074639 0:cecf4940adf1 99 #define EXT_SENS_DATA_06 (0x4F) // R
a0074639 0:cecf4940adf1 100 #define EXT_SENS_DATA_07 (0x50) // R
a0074639 0:cecf4940adf1 101 #define EXT_SENS_DATA_08 (0x51) // R
a0074639 0:cecf4940adf1 102 #define EXT_SENS_DATA_09 (0x52) // R
a0074639 0:cecf4940adf1 103 #define EXT_SENS_DATA_10 (0x53) // R
a0074639 0:cecf4940adf1 104 #define EXT_SENS_DATA_11 (0x54) // R
a0074639 0:cecf4940adf1 105 #define EXT_SENS_DATA_12 (0x55) // R
a0074639 0:cecf4940adf1 106 #define EXT_SENS_DATA_13 (0x56) // R
a0074639 0:cecf4940adf1 107 #define EXT_SENS_DATA_14 (0x57) // R
a0074639 0:cecf4940adf1 108 #define EXT_SENS_DATA_15 (0x58) // R
a0074639 0:cecf4940adf1 109 #define EXT_SENS_DATA_16 (0x59) // R
a0074639 0:cecf4940adf1 110 #define EXT_SENS_DATA_17 (0x5A) // R
a0074639 0:cecf4940adf1 111 #define EXT_SENS_DATA_18 (0x5B) // R
a0074639 0:cecf4940adf1 112 #define EXT_SENS_DATA_19 (0x5C) // R
a0074639 0:cecf4940adf1 113 #define EXT_SENS_DATA_20 (0x5D) // R
a0074639 0:cecf4940adf1 114 #define EXT_SENS_DATA_21 (0x5E) // R
a0074639 0:cecf4940adf1 115 #define EXT_SENS_DATA_22 (0x5F) // R
a0074639 0:cecf4940adf1 116 #define EXT_SENS_DATA_23 (0x60) // R
a0074639 0:cecf4940adf1 117
a0074639 0:cecf4940adf1 118 #define I2C_SLV0_DO (0x63) // R/W
a0074639 0:cecf4940adf1 119 #define I2C_SLV1_DO (0x64) // R/W
a0074639 0:cecf4940adf1 120 #define I2C_SLV2_DO (0x65) // R/W
a0074639 0:cecf4940adf1 121 #define I2C_SLV3_DO (0x66) // R/W
a0074639 0:cecf4940adf1 122 #define I2C_MST_DELAY_CTRL (0x67) // R/W
a0074639 0:cecf4940adf1 123 #define SIGNAL_PATH_RESET (0x68) // R/W
a0074639 0:cecf4940adf1 124 #define USER_CTRL (0x6A) // R/W
a0074639 0:cecf4940adf1 125 #define PWR_MGMT_1 (0x6B) // R/W
a0074639 0:cecf4940adf1 126 #define PER_MGMT_2 (0x6C) // R/W
a0074639 0:cecf4940adf1 127
a0074639 0:cecf4940adf1 128 #define FIFO_COUNTH (0x72) // R/W
a0074639 0:cecf4940adf1 129 #define FIFO_COUNTL (0x73) // R/W
a0074639 0:cecf4940adf1 130 #define FIFO_R_W (0x74) // R/W
a0074639 0:cecf4940adf1 131 #define WHO_AM_I (0x75) // R
a0074639 0:cecf4940adf1 132
a0074639 0:cecf4940adf1 133 #define XA_OFFSET_H (0x77)
a0074639 0:cecf4940adf1 134 #define XA_OFFSET_L (0x78)
a0074639 0:cecf4940adf1 135 #define YA_OFFSET_H (0x7A)
a0074639 0:cecf4940adf1 136 #define YA_OFFSET_L (0x7B)
a0074639 0:cecf4940adf1 137 #define ZA_OFFSET_H (0x7D)
a0074639 0:cecf4940adf1 138 #define ZA_OFFSET_L (0x7E)
a0074639 0:cecf4940adf1 139
a0074639 0:cecf4940adf1 140 /*-MPU-9150 setting command-*/
a0074639 0:cecf4940adf1 141 #define ACCEL_CONFIG_AFS_SEL_2 (0x00 << 3) //16384 LSB/mg
a0074639 0:cecf4940adf1 142 #define ACCEL_CONFIG_AFS_SEL_4 (0x01 << 3) //8192 LSB/mg
a0074639 0:cecf4940adf1 143 #define ACCEL_CONFIG_AFS_SEL_8 (0x02 << 3) //4096 LSB/mg
a0074639 0:cecf4940adf1 144 #define ACCEL_CONFIG_AFS_SEL_16 (0x03 << 3) //2048 LSB/mg
a0074639 0:cecf4940adf1 145
a0074639 0:cecf4940adf1 146 #define GYRO_CONFIG_FS_SEL_250 (0x00 << 3) //131 LSB/deg/sce
a0074639 0:cecf4940adf1 147 #define GYRO_CONFIG_FS_SEL_500 (0x01 << 3) //65.5 LSB/deg/sec
a0074639 0:cecf4940adf1 148 #define GYRO_CONFIG_FS_SEL_1000 (0x02 << 3) //32.8 LSB/deg/sec
a0074639 0:cecf4940adf1 149 #define GYRO_CONFIG_FS_SEL_2000 (0x03 << 3) //16.4 LSB/deg/sec
a0074639 0:cecf4940adf1 150
a0074639 0:cecf4940adf1 151 /*-MPU-9150 clock source-*/
a0074639 0:cecf4940adf1 152 #define PWR_MGMT_1_CLKSEL_0 (0x00) //Internal 8MHz oscillator
a0074639 0:cecf4940adf1 153 #define PWR_MGMT_1_CLKSEL_1 (0x01) //PLL with X axis gyroscope reference
a0074639 0:cecf4940adf1 154 #define PWR_MGMT_1_CLKSEL_2 (0x02) //PLL with Y axis gyroscope reference
a0074639 0:cecf4940adf1 155 #define PWR_MGMT_1_CLKSEL_3 (0x03) //PLL with Z axis gyroscope reference
a0074639 0:cecf4940adf1 156 #define PWR_MGMT_1_CLKSEL_4 (0x04) //PLL with external 32.768kHz reference
a0074639 0:cecf4940adf1 157 #define PWR_MGMT_1_CLKSEL_5 (0x05) //PLL with external 19.2MHz reference
a0074639 0:cecf4940adf1 158 #define PWR_MGMT_1_CLKSEL_6 (0x06) //Reserved
a0074639 0:cecf4940adf1 159 #define PWR_MGMT_1_CLKSEL_7 (0x07) //Stops the clock and keeps the timing generator in reset
a0074639 0:cecf4940adf1 160
a0074639 0:cecf4940adf1 161 #define INT_PIN_DFG_I2C_BYPASS_EN (0x02)
a0074639 0:cecf4940adf1 162
a0074639 0:cecf4940adf1 163 enum AccelSensitivity {
a0074639 0:cecf4940adf1 164 AFS_SEL_2=0,
a0074639 0:cecf4940adf1 165 AFS_SEL_4,
a0074639 0:cecf4940adf1 166 AFS_SEL_8,
a0074639 0:cecf4940adf1 167 AFS_SEL_16,
a0074639 0:cecf4940adf1 168 };
a0074639 0:cecf4940adf1 169
a0074639 0:cecf4940adf1 170 char getAccelSensitivity(AccelSensitivity mode)
a0074639 0:cecf4940adf1 171 {
a0074639 0:cecf4940adf1 172 switch(mode) {
a0074639 0:cecf4940adf1 173 case AFS_SEL_2:
a0074639 0:cecf4940adf1 174 return ACCEL_CONFIG_AFS_SEL_2;
a0074639 0:cecf4940adf1 175 case AFS_SEL_4:
a0074639 0:cecf4940adf1 176 return ACCEL_CONFIG_AFS_SEL_4;
a0074639 0:cecf4940adf1 177 case AFS_SEL_8:
a0074639 0:cecf4940adf1 178 return ACCEL_CONFIG_AFS_SEL_8;
a0074639 0:cecf4940adf1 179 case AFS_SEL_16:
a0074639 0:cecf4940adf1 180 return ACCEL_CONFIG_AFS_SEL_16;
a0074639 0:cecf4940adf1 181 default:
a0074639 0:cecf4940adf1 182 return ACCEL_CONFIG_AFS_SEL_2;
a0074639 0:cecf4940adf1 183 }
a0074639 0:cecf4940adf1 184 };
a0074639 0:cecf4940adf1 185
a0074639 0:cecf4940adf1 186 double getAccelLSB2MG(AccelSensitivity mode)
a0074639 0:cecf4940adf1 187 {
a0074639 0:cecf4940adf1 188 switch(mode) {
a0074639 0:cecf4940adf1 189 case AFS_SEL_2:
a0074639 0:cecf4940adf1 190 return (2.0/32768.0);
a0074639 0:cecf4940adf1 191 case AFS_SEL_4:
a0074639 0:cecf4940adf1 192 return (4.0/32768.0);
a0074639 0:cecf4940adf1 193 case AFS_SEL_8:
a0074639 0:cecf4940adf1 194 return (8.0/32768.0);
a0074639 0:cecf4940adf1 195 case AFS_SEL_16:
a0074639 0:cecf4940adf1 196 return (16.0/32768.0);
a0074639 0:cecf4940adf1 197 default:
a0074639 0:cecf4940adf1 198 return (2.0/32768.0);
a0074639 0:cecf4940adf1 199 }
a0074639 0:cecf4940adf1 200 };
a0074639 0:cecf4940adf1 201
a0074639 0:cecf4940adf1 202 enum GyroSensitivity {
a0074639 0:cecf4940adf1 203 FS_SEL_250=0,
a0074639 0:cecf4940adf1 204 FS_SEL_500,
a0074639 0:cecf4940adf1 205 FS_SEL_1000,
a0074639 0:cecf4940adf1 206 FS_SEL_2000,
a0074639 0:cecf4940adf1 207 };
a0074639 0:cecf4940adf1 208
a0074639 0:cecf4940adf1 209 char getGyroSensitivity(GyroSensitivity mode)
a0074639 0:cecf4940adf1 210 {
a0074639 0:cecf4940adf1 211 switch(mode) {
a0074639 0:cecf4940adf1 212 case FS_SEL_250:
a0074639 0:cecf4940adf1 213 return GYRO_CONFIG_FS_SEL_250;
a0074639 0:cecf4940adf1 214 case FS_SEL_500:
a0074639 0:cecf4940adf1 215 return GYRO_CONFIG_FS_SEL_500;
a0074639 0:cecf4940adf1 216 case FS_SEL_1000:
a0074639 0:cecf4940adf1 217 return GYRO_CONFIG_FS_SEL_1000;
a0074639 0:cecf4940adf1 218 case FS_SEL_2000:
a0074639 0:cecf4940adf1 219 return GYRO_CONFIG_FS_SEL_2000;
a0074639 0:cecf4940adf1 220 default:
a0074639 0:cecf4940adf1 221 return GYRO_CONFIG_FS_SEL_250;
a0074639 0:cecf4940adf1 222 }
a0074639 0:cecf4940adf1 223 };
a0074639 0:cecf4940adf1 224
a0074639 0:cecf4940adf1 225 double getGyroLSB2DegPerSec(GyroSensitivity mode)
a0074639 0:cecf4940adf1 226 {
a0074639 0:cecf4940adf1 227 switch(mode) {
a0074639 0:cecf4940adf1 228 case FS_SEL_250:
a0074639 0:cecf4940adf1 229 return (250.0/32768.0);
a0074639 0:cecf4940adf1 230 case FS_SEL_500:
a0074639 0:cecf4940adf1 231 return (500.0/32768.0);
a0074639 0:cecf4940adf1 232 case FS_SEL_1000:
a0074639 0:cecf4940adf1 233 return (1000.0/32768.0);
a0074639 0:cecf4940adf1 234 case FS_SEL_2000:
a0074639 0:cecf4940adf1 235 return (2000.0/32768.0);
a0074639 0:cecf4940adf1 236 default:
a0074639 0:cecf4940adf1 237 return (250.0/32768.0);
a0074639 0:cecf4940adf1 238 }
a0074639 0:cecf4940adf1 239 };
a0074639 0:cecf4940adf1 240
a0074639 0:cecf4940adf1 241 #endif /* MPU9250DEFINE_H */