Luth Haroon / SD_modified

SD card interface

mbed-export/LPC11U24/GCC_CS/LPC11Uxx.h@0:22612ae617a0, 2012-10-08 (annotated)

Committer:
lharoon
Date:
Mon Oct 08 11:14:07 2012 +0000
Revision:
0:22612ae617a0
1st edition

Who changed what in which revision?

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lharoon 0:22612ae617a0 1
lharoon 0:22612ae617a0 2 /****************************************************************************************************//**
lharoon 0:22612ae617a0 3 * @file LPC11Uxx.h
lharoon 0:22612ae617a0 4 *
lharoon 0:22612ae617a0 5 *
lharoon 0:22612ae617a0 6 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
lharoon 0:22612ae617a0 7 * default LPC11Uxx Device Series
lharoon 0:22612ae617a0 8 *
lharoon 0:22612ae617a0 9 * @version V0.1
lharoon 0:22612ae617a0 10 * @date 21. March 2011
lharoon 0:22612ae617a0 11 *
lharoon 0:22612ae617a0 12 * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
lharoon 0:22612ae617a0 13 *
lharoon 0:22612ae617a0 14 * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
lharoon 0:22612ae617a0 15 * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
lharoon 0:22612ae617a0 16 *
lharoon 0:22612ae617a0 17 *******************************************************************************************************/
lharoon 0:22612ae617a0 18
lharoon 0:22612ae617a0 19 // ################################################################################
lharoon 0:22612ae617a0 20 // Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
lharoon 0:22612ae617a0 21 // ################################################################################
lharoon 0:22612ae617a0 22
lharoon 0:22612ae617a0 23 /** @addtogroup NXP
lharoon 0:22612ae617a0 24 * @{
lharoon 0:22612ae617a0 25 */
lharoon 0:22612ae617a0 26
lharoon 0:22612ae617a0 27 /** @addtogroup LPC11Uxx
lharoon 0:22612ae617a0 28 * @{
lharoon 0:22612ae617a0 29 */
lharoon 0:22612ae617a0 30
lharoon 0:22612ae617a0 31 #ifndef __LPC11UXX_H__
lharoon 0:22612ae617a0 32 #define __LPC11UXX_H__
lharoon 0:22612ae617a0 33
lharoon 0:22612ae617a0 34 #ifdef __cplusplus
lharoon 0:22612ae617a0 35 extern "C" {
lharoon 0:22612ae617a0 36 #endif
lharoon 0:22612ae617a0 37
lharoon 0:22612ae617a0 38
lharoon 0:22612ae617a0 39 #if defined ( __CC_ARM )
lharoon 0:22612ae617a0 40 #pragma anon_unions
lharoon 0:22612ae617a0 41 #endif
lharoon 0:22612ae617a0 42
lharoon 0:22612ae617a0 43 /* Interrupt Number Definition */
lharoon 0:22612ae617a0 44
lharoon 0:22612ae617a0 45 typedef enum {
lharoon 0:22612ae617a0 46 // ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
lharoon 0:22612ae617a0 47 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
lharoon 0:22612ae617a0 48 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
lharoon 0:22612ae617a0 49 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
lharoon 0:22612ae617a0 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
lharoon 0:22612ae617a0 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
lharoon 0:22612ae617a0 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
lharoon 0:22612ae617a0 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
lharoon 0:22612ae617a0 54 // --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
lharoon 0:22612ae617a0 55 FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
lharoon 0:22612ae617a0 56 FLEX_INT1_IRQn = 1,
lharoon 0:22612ae617a0 57 FLEX_INT2_IRQn = 2,
lharoon 0:22612ae617a0 58 FLEX_INT3_IRQn = 3,
lharoon 0:22612ae617a0 59 FLEX_INT4_IRQn = 4,
lharoon 0:22612ae617a0 60 FLEX_INT5_IRQn = 5,
lharoon 0:22612ae617a0 61 FLEX_INT6_IRQn = 6,
lharoon 0:22612ae617a0 62 FLEX_INT7_IRQn = 7,
lharoon 0:22612ae617a0 63 GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
lharoon 0:22612ae617a0 64 GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
lharoon 0:22612ae617a0 65 Reserved0_IRQn = 10, /*!< Reserved Interrupt */
lharoon 0:22612ae617a0 66 Reserved1_IRQn = 11,
lharoon 0:22612ae617a0 67 Reserved2_IRQn = 12,
lharoon 0:22612ae617a0 68 Reserved3_IRQn = 13,
lharoon 0:22612ae617a0 69 SSP1_IRQn = 14, /*!< SSP1 Interrupt */
lharoon 0:22612ae617a0 70 I2C_IRQn = 15, /*!< I2C Interrupt */
lharoon 0:22612ae617a0 71 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
lharoon 0:22612ae617a0 72 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
lharoon 0:22612ae617a0 73 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
lharoon 0:22612ae617a0 74 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
lharoon 0:22612ae617a0 75 SSP0_IRQn = 20, /*!< SSP0 Interrupt */
lharoon 0:22612ae617a0 76 UART_IRQn = 21, /*!< UART Interrupt */
lharoon 0:22612ae617a0 77 USB_IRQn = 22, /*!< USB IRQ Interrupt */
lharoon 0:22612ae617a0 78 USB_FIQn = 23, /*!< USB FIQ Interrupt */
lharoon 0:22612ae617a0 79 ADC_IRQn = 24, /*!< A/D Converter Interrupt */
lharoon 0:22612ae617a0 80 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
lharoon 0:22612ae617a0 81 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
lharoon 0:22612ae617a0 82 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
lharoon 0:22612ae617a0 83 Reserved4_IRQn = 28, /*!< Reserved Interrupt */
lharoon 0:22612ae617a0 84 Reserved5_IRQn = 29, /*!< Reserved Interrupt */
lharoon 0:22612ae617a0 85 USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
lharoon 0:22612ae617a0 86 Reserved6_IRQn = 31, /*!< Reserved Interrupt */
lharoon 0:22612ae617a0 87 } IRQn_Type;
lharoon 0:22612ae617a0 88
lharoon 0:22612ae617a0 89
lharoon 0:22612ae617a0 90 /** @addtogroup Configuration_of_CMSIS
lharoon 0:22612ae617a0 91 * @{
lharoon 0:22612ae617a0 92 */
lharoon 0:22612ae617a0 93
lharoon 0:22612ae617a0 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
lharoon 0:22612ae617a0 95
lharoon 0:22612ae617a0 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
lharoon 0:22612ae617a0 97 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
lharoon 0:22612ae617a0 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
lharoon 0:22612ae617a0 99 /** @} */ /* End of group Configuration_of_CMSIS */
lharoon 0:22612ae617a0 100
lharoon 0:22612ae617a0 101 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
lharoon 0:22612ae617a0 102 #include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
lharoon 0:22612ae617a0 103
lharoon 0:22612ae617a0 104 /** @addtogroup Device_Peripheral_Registers
lharoon 0:22612ae617a0 105 * @{
lharoon 0:22612ae617a0 106 */
lharoon 0:22612ae617a0 107
lharoon 0:22612ae617a0 108
lharoon 0:22612ae617a0 109 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 110 // ----- I2C -----
lharoon 0:22612ae617a0 111 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 112
lharoon 0:22612ae617a0 113
lharoon 0:22612ae617a0 114 /**
lharoon 0:22612ae617a0 115 * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
lharoon 0:22612ae617a0 116 */
lharoon 0:22612ae617a0 117
lharoon 0:22612ae617a0 118 typedef struct { /*!< (@ 0x40000000) I2C Structure */
lharoon 0:22612ae617a0 119 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
lharoon 0:22612ae617a0 120 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
lharoon 0:22612ae617a0 121 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
lharoon 0:22612ae617a0 122 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
lharoon 0:22612ae617a0 123 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
lharoon 0:22612ae617a0 124 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
lharoon 0:22612ae617a0 125 __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
lharoon 0:22612ae617a0 126 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
lharoon 0:22612ae617a0 127 __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
lharoon 0:22612ae617a0 128 __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
lharoon 0:22612ae617a0 129 __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
lharoon 0:22612ae617a0 130 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
lharoon 0:22612ae617a0 131 union{
lharoon 0:22612ae617a0 132 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
lharoon 0:22612ae617a0 133 struct{
lharoon 0:22612ae617a0 134 __IO uint32_t MASK0;
lharoon 0:22612ae617a0 135 __IO uint32_t MASK1;
lharoon 0:22612ae617a0 136 __IO uint32_t MASK2;
lharoon 0:22612ae617a0 137 __IO uint32_t MASK3;
lharoon 0:22612ae617a0 138 };
lharoon 0:22612ae617a0 139 };
lharoon 0:22612ae617a0 140 } LPC_I2C_Type;
lharoon 0:22612ae617a0 141
lharoon 0:22612ae617a0 142
lharoon 0:22612ae617a0 143 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 144 // ----- WWDT -----
lharoon 0:22612ae617a0 145 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 146
lharoon 0:22612ae617a0 147
lharoon 0:22612ae617a0 148 /**
lharoon 0:22612ae617a0 149 * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
lharoon 0:22612ae617a0 150 */
lharoon 0:22612ae617a0 151
lharoon 0:22612ae617a0 152 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
lharoon 0:22612ae617a0 153 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
lharoon 0:22612ae617a0 154 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
lharoon 0:22612ae617a0 155 __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
lharoon 0:22612ae617a0 156 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
lharoon 0:22612ae617a0 157 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
lharoon 0:22612ae617a0 158 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
lharoon 0:22612ae617a0 159 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
lharoon 0:22612ae617a0 160 } LPC_WWDT_Type;
lharoon 0:22612ae617a0 161
lharoon 0:22612ae617a0 162
lharoon 0:22612ae617a0 163 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 164 // ----- USART -----
lharoon 0:22612ae617a0 165 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 166
lharoon 0:22612ae617a0 167
lharoon 0:22612ae617a0 168 /**
lharoon 0:22612ae617a0 169 * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
lharoon 0:22612ae617a0 170 */
lharoon 0:22612ae617a0 171
lharoon 0:22612ae617a0 172 typedef struct { /*!< (@ 0x40008000) USART Structure */
lharoon 0:22612ae617a0 173
lharoon 0:22612ae617a0 174 union {
lharoon 0:22612ae617a0 175 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
lharoon 0:22612ae617a0 176 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
lharoon 0:22612ae617a0 177 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
lharoon 0:22612ae617a0 178 };
lharoon 0:22612ae617a0 179
lharoon 0:22612ae617a0 180 union {
lharoon 0:22612ae617a0 181 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
lharoon 0:22612ae617a0 182 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
lharoon 0:22612ae617a0 183 };
lharoon 0:22612ae617a0 184
lharoon 0:22612ae617a0 185 union {
lharoon 0:22612ae617a0 186 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
lharoon 0:22612ae617a0 187 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
lharoon 0:22612ae617a0 188 };
lharoon 0:22612ae617a0 189 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
lharoon 0:22612ae617a0 190 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
lharoon 0:22612ae617a0 191 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
lharoon 0:22612ae617a0 192 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
lharoon 0:22612ae617a0 193 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
lharoon 0:22612ae617a0 194 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
lharoon 0:22612ae617a0 195 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
lharoon 0:22612ae617a0 196 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
lharoon 0:22612ae617a0 197 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
lharoon 0:22612ae617a0 198 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
lharoon 0:22612ae617a0 199 __I uint32_t RESERVED0[3];
lharoon 0:22612ae617a0 200 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
lharoon 0:22612ae617a0 201 __I uint32_t RESERVED1;
lharoon 0:22612ae617a0 202 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
lharoon 0:22612ae617a0 203 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
lharoon 0:22612ae617a0 204 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
lharoon 0:22612ae617a0 205 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
lharoon 0:22612ae617a0 206 __IO uint32_t SYNCCTRL;
lharoon 0:22612ae617a0 207 } LPC_USART_Type;
lharoon 0:22612ae617a0 208
lharoon 0:22612ae617a0 209
lharoon 0:22612ae617a0 210 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 211 // ----- Timer -----
lharoon 0:22612ae617a0 212 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 213
lharoon 0:22612ae617a0 214
lharoon 0:22612ae617a0 215 /**
lharoon 0:22612ae617a0 216 * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
lharoon 0:22612ae617a0 217 */
lharoon 0:22612ae617a0 218
lharoon 0:22612ae617a0 219 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
lharoon 0:22612ae617a0 220 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
lharoon 0:22612ae617a0 221 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
lharoon 0:22612ae617a0 222 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
lharoon 0:22612ae617a0 223 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
lharoon 0:22612ae617a0 224 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
lharoon 0:22612ae617a0 225 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
lharoon 0:22612ae617a0 226 union {
lharoon 0:22612ae617a0 227 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
lharoon 0:22612ae617a0 228 struct{
lharoon 0:22612ae617a0 229 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
lharoon 0:22612ae617a0 230 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
lharoon 0:22612ae617a0 231 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
lharoon 0:22612ae617a0 232 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
lharoon 0:22612ae617a0 233 };
lharoon 0:22612ae617a0 234 };
lharoon 0:22612ae617a0 235 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
lharoon 0:22612ae617a0 236 union{
lharoon 0:22612ae617a0 237 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
lharoon 0:22612ae617a0 238 struct{
lharoon 0:22612ae617a0 239 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
lharoon 0:22612ae617a0 240 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
lharoon 0:22612ae617a0 241 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
lharoon 0:22612ae617a0 242 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
lharoon 0:22612ae617a0 243 };
lharoon 0:22612ae617a0 244 };
lharoon 0:22612ae617a0 245 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
lharoon 0:22612ae617a0 246 __I uint32_t RESERVED0[12];
lharoon 0:22612ae617a0 247 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
lharoon 0:22612ae617a0 248 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
lharoon 0:22612ae617a0 249 } LPC_CTxxBx_Type;
lharoon 0:22612ae617a0 250
lharoon 0:22612ae617a0 251
lharoon 0:22612ae617a0 252
lharoon 0:22612ae617a0 253 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 254 // ----- ADC -----
lharoon 0:22612ae617a0 255 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 256
lharoon 0:22612ae617a0 257
lharoon 0:22612ae617a0 258 /**
lharoon 0:22612ae617a0 259 * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
lharoon 0:22612ae617a0 260 */
lharoon 0:22612ae617a0 261
lharoon 0:22612ae617a0 262 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
lharoon 0:22612ae617a0 263 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
lharoon 0:22612ae617a0 264 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
lharoon 0:22612ae617a0 265 __I uint32_t RESERVED0[1];
lharoon 0:22612ae617a0 266 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
lharoon 0:22612ae617a0 267 union{
lharoon 0:22612ae617a0 268 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
lharoon 0:22612ae617a0 269 struct{
lharoon 0:22612ae617a0 270 __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
lharoon 0:22612ae617a0 271 __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
lharoon 0:22612ae617a0 272 __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
lharoon 0:22612ae617a0 273 __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
lharoon 0:22612ae617a0 274 __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
lharoon 0:22612ae617a0 275 __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
lharoon 0:22612ae617a0 276 __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
lharoon 0:22612ae617a0 277 __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
lharoon 0:22612ae617a0 278 };
lharoon 0:22612ae617a0 279 };
lharoon 0:22612ae617a0 280 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
lharoon 0:22612ae617a0 281 } LPC_ADC_Type;
lharoon 0:22612ae617a0 282
lharoon 0:22612ae617a0 283
lharoon 0:22612ae617a0 284 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 285 // ----- PMU -----
lharoon 0:22612ae617a0 286 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 287
lharoon 0:22612ae617a0 288
lharoon 0:22612ae617a0 289 /**
lharoon 0:22612ae617a0 290 * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
lharoon 0:22612ae617a0 291 */
lharoon 0:22612ae617a0 292
lharoon 0:22612ae617a0 293 typedef struct { /*!< (@ 0x40038000) PMU Structure */
lharoon 0:22612ae617a0 294 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
lharoon 0:22612ae617a0 295 union{
lharoon 0:22612ae617a0 296 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
lharoon 0:22612ae617a0 297 struct{
lharoon 0:22612ae617a0 298 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
lharoon 0:22612ae617a0 299 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
lharoon 0:22612ae617a0 300 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
lharoon 0:22612ae617a0 301 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
lharoon 0:22612ae617a0 302 };
lharoon 0:22612ae617a0 303 };
lharoon 0:22612ae617a0 304 } LPC_PMU_Type;
lharoon 0:22612ae617a0 305
lharoon 0:22612ae617a0 306
lharoon 0:22612ae617a0 307 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 308 // ----- FLASHCTRL -----
lharoon 0:22612ae617a0 309 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 310
lharoon 0:22612ae617a0 311
lharoon 0:22612ae617a0 312 /**
lharoon 0:22612ae617a0 313 * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
lharoon 0:22612ae617a0 314 */
lharoon 0:22612ae617a0 315
lharoon 0:22612ae617a0 316 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
lharoon 0:22612ae617a0 317 __I uint32_t RESERVED0[4];
lharoon 0:22612ae617a0 318 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
lharoon 0:22612ae617a0 319 __I uint32_t RESERVED1[3];
lharoon 0:22612ae617a0 320 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
lharoon 0:22612ae617a0 321 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
lharoon 0:22612ae617a0 322 __I uint32_t RESERVED2[1];
lharoon 0:22612ae617a0 323 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
lharoon 0:22612ae617a0 324 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
lharoon 0:22612ae617a0 325 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
lharoon 0:22612ae617a0 326 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
lharoon 0:22612ae617a0 327 __I uint32_t RESERVED3[1001];
lharoon 0:22612ae617a0 328 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
lharoon 0:22612ae617a0 329 __I uint32_t RESERVED4[1];
lharoon 0:22612ae617a0 330 __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
lharoon 0:22612ae617a0 331 } LPC_FLASHCTRL_Type;
lharoon 0:22612ae617a0 332
lharoon 0:22612ae617a0 333
lharoon 0:22612ae617a0 334 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 335 // ----- SSP0/1 -----
lharoon 0:22612ae617a0 336 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 337
lharoon 0:22612ae617a0 338
lharoon 0:22612ae617a0 339 /**
lharoon 0:22612ae617a0 340 * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
lharoon 0:22612ae617a0 341 */
lharoon 0:22612ae617a0 342
lharoon 0:22612ae617a0 343 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
lharoon 0:22612ae617a0 344 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
lharoon 0:22612ae617a0 345 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
lharoon 0:22612ae617a0 346 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
lharoon 0:22612ae617a0 347 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
lharoon 0:22612ae617a0 348 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
lharoon 0:22612ae617a0 349 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
lharoon 0:22612ae617a0 350 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
lharoon 0:22612ae617a0 351 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
lharoon 0:22612ae617a0 352 __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
lharoon 0:22612ae617a0 353 } LPC_SSPx_Type;
lharoon 0:22612ae617a0 354
lharoon 0:22612ae617a0 355
lharoon 0:22612ae617a0 356
lharoon 0:22612ae617a0 357 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 358 // ----- IOCONFIG -----
lharoon 0:22612ae617a0 359 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 360
lharoon 0:22612ae617a0 361
lharoon 0:22612ae617a0 362 /**
lharoon 0:22612ae617a0 363 * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
lharoon 0:22612ae617a0 364 */
lharoon 0:22612ae617a0 365
lharoon 0:22612ae617a0 366 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
lharoon 0:22612ae617a0 367 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
lharoon 0:22612ae617a0 368 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
lharoon 0:22612ae617a0 369 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
lharoon 0:22612ae617a0 370 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
lharoon 0:22612ae617a0 371 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
lharoon 0:22612ae617a0 372 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
lharoon 0:22612ae617a0 373 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
lharoon 0:22612ae617a0 374 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
lharoon 0:22612ae617a0 375 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
lharoon 0:22612ae617a0 376 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
lharoon 0:22612ae617a0 377 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
lharoon 0:22612ae617a0 378 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
lharoon 0:22612ae617a0 379 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
lharoon 0:22612ae617a0 380 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
lharoon 0:22612ae617a0 381 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
lharoon 0:22612ae617a0 382 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
lharoon 0:22612ae617a0 383 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
lharoon 0:22612ae617a0 384 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
lharoon 0:22612ae617a0 385 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
lharoon 0:22612ae617a0 386 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
lharoon 0:22612ae617a0 387 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
lharoon 0:22612ae617a0 388 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
lharoon 0:22612ae617a0 389 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
lharoon 0:22612ae617a0 390 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
lharoon 0:22612ae617a0 391 __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
lharoon 0:22612ae617a0 392 __IO uint32_t PIO1_1;
lharoon 0:22612ae617a0 393 __IO uint32_t PIO1_2;
lharoon 0:22612ae617a0 394 __IO uint32_t PIO1_3;
lharoon 0:22612ae617a0 395 __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
lharoon 0:22612ae617a0 396 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
lharoon 0:22612ae617a0 397 __IO uint32_t PIO1_6;
lharoon 0:22612ae617a0 398 __IO uint32_t PIO1_7;
lharoon 0:22612ae617a0 399 __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
lharoon 0:22612ae617a0 400 __IO uint32_t PIO1_9;
lharoon 0:22612ae617a0 401 __IO uint32_t PIO1_10;
lharoon 0:22612ae617a0 402 __IO uint32_t PIO1_11;
lharoon 0:22612ae617a0 403 __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
lharoon 0:22612ae617a0 404 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
lharoon 0:22612ae617a0 405 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
lharoon 0:22612ae617a0 406 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
lharoon 0:22612ae617a0 407 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
lharoon 0:22612ae617a0 408 __IO uint32_t PIO1_17;
lharoon 0:22612ae617a0 409 __IO uint32_t PIO1_18;
lharoon 0:22612ae617a0 410 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
lharoon 0:22612ae617a0 411 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
lharoon 0:22612ae617a0 412 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
lharoon 0:22612ae617a0 413 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
lharoon 0:22612ae617a0 414 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
lharoon 0:22612ae617a0 415 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
lharoon 0:22612ae617a0 416 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
lharoon 0:22612ae617a0 417 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
lharoon 0:22612ae617a0 418 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
lharoon 0:22612ae617a0 419 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
lharoon 0:22612ae617a0 420 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
lharoon 0:22612ae617a0 421 __IO uint32_t PIO1_30;
lharoon 0:22612ae617a0 422 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
lharoon 0:22612ae617a0 423 } LPC_IOCON_Type;
lharoon 0:22612ae617a0 424
lharoon 0:22612ae617a0 425
lharoon 0:22612ae617a0 426 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 427 // ----- SYSCON -----
lharoon 0:22612ae617a0 428 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 429
lharoon 0:22612ae617a0 430
lharoon 0:22612ae617a0 431 /**
lharoon 0:22612ae617a0 432 * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
lharoon 0:22612ae617a0 433 */
lharoon 0:22612ae617a0 434
lharoon 0:22612ae617a0 435 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
lharoon 0:22612ae617a0 436 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
lharoon 0:22612ae617a0 437 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
lharoon 0:22612ae617a0 438 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
lharoon 0:22612ae617a0 439 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
lharoon 0:22612ae617a0 440 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
lharoon 0:22612ae617a0 441 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
lharoon 0:22612ae617a0 442 __I uint32_t RESERVED0[2];
lharoon 0:22612ae617a0 443 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
lharoon 0:22612ae617a0 444 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
lharoon 0:22612ae617a0 445 __I uint32_t RESERVED1[2];
lharoon 0:22612ae617a0 446 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
lharoon 0:22612ae617a0 447 __I uint32_t RESERVED2[3];
lharoon 0:22612ae617a0 448 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
lharoon 0:22612ae617a0 449 __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
lharoon 0:22612ae617a0 450 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
lharoon 0:22612ae617a0 451 __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
lharoon 0:22612ae617a0 452 __I uint32_t RESERVED3[8];
lharoon 0:22612ae617a0 453 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
lharoon 0:22612ae617a0 454 __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
lharoon 0:22612ae617a0 455 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
lharoon 0:22612ae617a0 456 __I uint32_t RESERVED4[1];
lharoon 0:22612ae617a0 457 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
lharoon 0:22612ae617a0 458 __I uint32_t RESERVED5[4];
lharoon 0:22612ae617a0 459 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
lharoon 0:22612ae617a0 460 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
lharoon 0:22612ae617a0 461 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
lharoon 0:22612ae617a0 462 __I uint32_t RESERVED6[8];
lharoon 0:22612ae617a0 463 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
lharoon 0:22612ae617a0 464 __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
lharoon 0:22612ae617a0 465 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
lharoon 0:22612ae617a0 466 __I uint32_t RESERVED7[5];
lharoon 0:22612ae617a0 467 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
lharoon 0:22612ae617a0 468 __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
lharoon 0:22612ae617a0 469 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
lharoon 0:22612ae617a0 470 __I uint32_t RESERVED8[5];
lharoon 0:22612ae617a0 471 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
lharoon 0:22612ae617a0 472 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
lharoon 0:22612ae617a0 473 __I uint32_t RESERVED9[18];
lharoon 0:22612ae617a0 474 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
lharoon 0:22612ae617a0 475 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
lharoon 0:22612ae617a0 476 __I uint32_t RESERVED10[6];
lharoon 0:22612ae617a0 477 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
lharoon 0:22612ae617a0 478 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
lharoon 0:22612ae617a0 479 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
lharoon 0:22612ae617a0 480 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
lharoon 0:22612ae617a0 481 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
lharoon 0:22612ae617a0 482 __I uint32_t RESERVED11[25];
lharoon 0:22612ae617a0 483 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
lharoon 0:22612ae617a0 484 __I uint32_t RESERVED12[3];
lharoon 0:22612ae617a0 485 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
lharoon 0:22612ae617a0 486 __I uint32_t RESERVED13[6];
lharoon 0:22612ae617a0 487 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
lharoon 0:22612ae617a0 488 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
lharoon 0:22612ae617a0 489 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
lharoon 0:22612ae617a0 490 __I uint32_t RESERVED14[110];
lharoon 0:22612ae617a0 491 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
lharoon 0:22612ae617a0 492 } LPC_SYSCON_Type;
lharoon 0:22612ae617a0 493
lharoon 0:22612ae617a0 494
lharoon 0:22612ae617a0 495 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 496 // ----- GPIO_PIN_INT -----
lharoon 0:22612ae617a0 497 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 498
lharoon 0:22612ae617a0 499
lharoon 0:22612ae617a0 500 /**
lharoon 0:22612ae617a0 501 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
lharoon 0:22612ae617a0 502 */
lharoon 0:22612ae617a0 503
lharoon 0:22612ae617a0 504 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
lharoon 0:22612ae617a0 505 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
lharoon 0:22612ae617a0 506 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
lharoon 0:22612ae617a0 507 __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
lharoon 0:22612ae617a0 508 __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
lharoon 0:22612ae617a0 509 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
lharoon 0:22612ae617a0 510 __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
lharoon 0:22612ae617a0 511 __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
lharoon 0:22612ae617a0 512 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
lharoon 0:22612ae617a0 513 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
lharoon 0:22612ae617a0 514 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
lharoon 0:22612ae617a0 515 } LPC_GPIO_PIN_INT_Type;
lharoon 0:22612ae617a0 516
lharoon 0:22612ae617a0 517
lharoon 0:22612ae617a0 518 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 519 // ----- GPIO_GROUP_INT0/1 -----
lharoon 0:22612ae617a0 520 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 521
lharoon 0:22612ae617a0 522
lharoon 0:22612ae617a0 523 /**
lharoon 0:22612ae617a0 524 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
lharoon 0:22612ae617a0 525 */
lharoon 0:22612ae617a0 526
lharoon 0:22612ae617a0 527 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
lharoon 0:22612ae617a0 528 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
lharoon 0:22612ae617a0 529 __I uint32_t RESERVED0[7];
lharoon 0:22612ae617a0 530 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
lharoon 0:22612ae617a0 531 __I uint32_t RESERVED1[6];
lharoon 0:22612ae617a0 532 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
lharoon 0:22612ae617a0 533 } LPC_GPIO_GROUP_INTx_Type;
lharoon 0:22612ae617a0 534
lharoon 0:22612ae617a0 535
lharoon 0:22612ae617a0 536
lharoon 0:22612ae617a0 537 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 538 // ----- USB -----
lharoon 0:22612ae617a0 539 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 540
lharoon 0:22612ae617a0 541
lharoon 0:22612ae617a0 542 /**
lharoon 0:22612ae617a0 543 * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
lharoon 0:22612ae617a0 544 */
lharoon 0:22612ae617a0 545
lharoon 0:22612ae617a0 546 typedef struct { /*!< (@ 0x40080000) USB Structure */
lharoon 0:22612ae617a0 547 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
lharoon 0:22612ae617a0 548 __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
lharoon 0:22612ae617a0 549 __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
lharoon 0:22612ae617a0 550 __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
lharoon 0:22612ae617a0 551 __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
lharoon 0:22612ae617a0 552 __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
lharoon 0:22612ae617a0 553 __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
lharoon 0:22612ae617a0 554 __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
lharoon 0:22612ae617a0 555 __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
lharoon 0:22612ae617a0 556 __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
lharoon 0:22612ae617a0 557 __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
lharoon 0:22612ae617a0 558 __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
lharoon 0:22612ae617a0 559 __I uint32_t RESERVED0[1];
lharoon 0:22612ae617a0 560 __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
lharoon 0:22612ae617a0 561 } LPC_USB_Type;
lharoon 0:22612ae617a0 562
lharoon 0:22612ae617a0 563
lharoon 0:22612ae617a0 564 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 565 // ----- GPIO_PORT -----
lharoon 0:22612ae617a0 566 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 567
lharoon 0:22612ae617a0 568
lharoon 0:22612ae617a0 569 /**
lharoon 0:22612ae617a0 570 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
lharoon 0:22612ae617a0 571 */
lharoon 0:22612ae617a0 572
lharoon 0:22612ae617a0 573 typedef struct {
lharoon 0:22612ae617a0 574 union {
lharoon 0:22612ae617a0 575 struct {
lharoon 0:22612ae617a0 576 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
lharoon 0:22612ae617a0 577 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
lharoon 0:22612ae617a0 578 };
lharoon 0:22612ae617a0 579 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
lharoon 0:22612ae617a0 580 };
lharoon 0:22612ae617a0 581 __I uint32_t RESERVED0[1008];
lharoon 0:22612ae617a0 582 union {
lharoon 0:22612ae617a0 583 struct {
lharoon 0:22612ae617a0 584 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
lharoon 0:22612ae617a0 585 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
lharoon 0:22612ae617a0 586 };
lharoon 0:22612ae617a0 587 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
lharoon 0:22612ae617a0 588 };
lharoon 0:22612ae617a0 589 uint32_t RESERVED1[960];
lharoon 0:22612ae617a0 590 __IO uint32_t DIR[2]; /* 0x2000 */
lharoon 0:22612ae617a0 591 uint32_t RESERVED2[30];
lharoon 0:22612ae617a0 592 __IO uint32_t MASK[2]; /* 0x2080 */
lharoon 0:22612ae617a0 593 uint32_t RESERVED3[30];
lharoon 0:22612ae617a0 594 __IO uint32_t PIN[2]; /* 0x2100 */
lharoon 0:22612ae617a0 595 uint32_t RESERVED4[30];
lharoon 0:22612ae617a0 596 __IO uint32_t MPIN[2]; /* 0x2180 */
lharoon 0:22612ae617a0 597 uint32_t RESERVED5[30];
lharoon 0:22612ae617a0 598 __IO uint32_t SET[2]; /* 0x2200 */
lharoon 0:22612ae617a0 599 uint32_t RESERVED6[30];
lharoon 0:22612ae617a0 600 __O uint32_t CLR[2]; /* 0x2280 */
lharoon 0:22612ae617a0 601 uint32_t RESERVED7[30];
lharoon 0:22612ae617a0 602 __O uint32_t NOT[2]; /* 0x2300 */
lharoon 0:22612ae617a0 603 } LPC_GPIO_Type;
lharoon 0:22612ae617a0 604
lharoon 0:22612ae617a0 605
lharoon 0:22612ae617a0 606 #if defined ( __CC_ARM )
lharoon 0:22612ae617a0 607 #pragma no_anon_unions
lharoon 0:22612ae617a0 608 #endif
lharoon 0:22612ae617a0 609
lharoon 0:22612ae617a0 610
lharoon 0:22612ae617a0 611 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 612 // ----- Peripheral memory map -----
lharoon 0:22612ae617a0 613 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 614
lharoon 0:22612ae617a0 615 #define LPC_I2C_BASE (0x40000000)
lharoon 0:22612ae617a0 616 #define LPC_WWDT_BASE (0x40004000)
lharoon 0:22612ae617a0 617 #define LPC_USART_BASE (0x40008000)
lharoon 0:22612ae617a0 618 #define LPC_CT16B0_BASE (0x4000C000)
lharoon 0:22612ae617a0 619 #define LPC_CT16B1_BASE (0x40010000)
lharoon 0:22612ae617a0 620 #define LPC_CT32B0_BASE (0x40014000)
lharoon 0:22612ae617a0 621 #define LPC_CT32B1_BASE (0x40018000)
lharoon 0:22612ae617a0 622 #define LPC_ADC_BASE (0x4001C000)
lharoon 0:22612ae617a0 623 #define LPC_PMU_BASE (0x40038000)
lharoon 0:22612ae617a0 624 #define LPC_FLASHCTRL_BASE (0x4003C000)
lharoon 0:22612ae617a0 625 #define LPC_SSP0_BASE (0x40040000)
lharoon 0:22612ae617a0 626 #define LPC_SSP1_BASE (0x40058000)
lharoon 0:22612ae617a0 627 #define LPC_IOCON_BASE (0x40044000)
lharoon 0:22612ae617a0 628 #define LPC_SYSCON_BASE (0x40048000)
lharoon 0:22612ae617a0 629 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
lharoon 0:22612ae617a0 630 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
lharoon 0:22612ae617a0 631 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
lharoon 0:22612ae617a0 632 #define LPC_USB_BASE (0x40080000)
lharoon 0:22612ae617a0 633 #define LPC_GPIO_BASE (0x50000000)
lharoon 0:22612ae617a0 634
lharoon 0:22612ae617a0 635
lharoon 0:22612ae617a0 636 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 637 // ----- Peripheral declaration -----
lharoon 0:22612ae617a0 638 // ------------------------------------------------------------------------------------------------
lharoon 0:22612ae617a0 639
lharoon 0:22612ae617a0 640 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
lharoon 0:22612ae617a0 641 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
lharoon 0:22612ae617a0 642 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
lharoon 0:22612ae617a0 643 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
lharoon 0:22612ae617a0 644 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
lharoon 0:22612ae617a0 645 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
lharoon 0:22612ae617a0 646 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
lharoon 0:22612ae617a0 647 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
lharoon 0:22612ae617a0 648 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
lharoon 0:22612ae617a0 649 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
lharoon 0:22612ae617a0 650 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
lharoon 0:22612ae617a0 651 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
lharoon 0:22612ae617a0 652 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
lharoon 0:22612ae617a0 653 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
lharoon 0:22612ae617a0 654 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
lharoon 0:22612ae617a0 655 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
lharoon 0:22612ae617a0 656 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
lharoon 0:22612ae617a0 657 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
lharoon 0:22612ae617a0 658 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
lharoon 0:22612ae617a0 659
lharoon 0:22612ae617a0 660
lharoon 0:22612ae617a0 661 /** @} */ /* End of group Device_Peripheral_Registers */
lharoon 0:22612ae617a0 662 /** @} */ /* End of group (null) */
lharoon 0:22612ae617a0 663 /** @} */ /* End of group LPC11Uxx */
lharoon 0:22612ae617a0 664
lharoon 0:22612ae617a0 665 #ifdef __cplusplus
lharoon 0:22612ae617a0 666 }
lharoon 0:22612ae617a0 667 #endif
lharoon 0:22612ae617a0 668
lharoon 0:22612ae617a0 669
lharoon 0:22612ae617a0 670 #endif // __LPC11UXX_H__