Luth Haroon / SD_modified

SD card interface

mbed-export/LPC2368/GCC_ARM/LPC23xx.h@0:22612ae617a0, 2012-10-08 (annotated)

Committer:
lharoon
Date:
Mon Oct 08 11:14:07 2012 +0000
Revision:
0:22612ae617a0
1st edition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lharoon 0:22612ae617a0 1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
lharoon 0:22612ae617a0 2 * Copyright (C) 2009 ARM Limited. All rights reserved.
lharoon 0:22612ae617a0 3 *
lharoon 0:22612ae617a0 4 * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
lharoon 0:22612ae617a0 5 */
lharoon 0:22612ae617a0 6
lharoon 0:22612ae617a0 7 #ifndef __LPC23xx_H
lharoon 0:22612ae617a0 8 #define __LPC23xx_H
lharoon 0:22612ae617a0 9
lharoon 0:22612ae617a0 10 #ifdef __cplusplus
lharoon 0:22612ae617a0 11 extern "C" {
lharoon 0:22612ae617a0 12 #endif
lharoon 0:22612ae617a0 13
lharoon 0:22612ae617a0 14 /*
lharoon 0:22612ae617a0 15 * ==========================================================================
lharoon 0:22612ae617a0 16 * ---------- Interrupt Number Definition -----------------------------------
lharoon 0:22612ae617a0 17 * ==========================================================================
lharoon 0:22612ae617a0 18 */
lharoon 0:22612ae617a0 19
lharoon 0:22612ae617a0 20 typedef enum IRQn
lharoon 0:22612ae617a0 21 {
lharoon 0:22612ae617a0 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
lharoon 0:22612ae617a0 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
lharoon 0:22612ae617a0 24
lharoon 0:22612ae617a0 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
lharoon 0:22612ae617a0 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
lharoon 0:22612ae617a0 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
lharoon 0:22612ae617a0 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
lharoon 0:22612ae617a0 29 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
lharoon 0:22612ae617a0 30 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
lharoon 0:22612ae617a0 31 SPI_IRQn = 10, /*!< SPI Interrupt */
lharoon 0:22612ae617a0 32 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
lharoon 0:22612ae617a0 33 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
lharoon 0:22612ae617a0 34 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
lharoon 0:22612ae617a0 35 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
lharoon 0:22612ae617a0 36 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
lharoon 0:22612ae617a0 37 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
lharoon 0:22612ae617a0 38 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
lharoon 0:22612ae617a0 39 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
lharoon 0:22612ae617a0 40 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
lharoon 0:22612ae617a0 41 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
lharoon 0:22612ae617a0 42 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
lharoon 0:22612ae617a0 43 ENET_IRQn = 21, /*!< Ethernet Interrupt */
lharoon 0:22612ae617a0 44 USB_IRQn = 22, /*!< USB Interrupt */
lharoon 0:22612ae617a0 45 CAN_IRQn = 23, /*!< CAN Interrupt */
lharoon 0:22612ae617a0 46 MIC_IRQn = 24, /*!< Multimedia Interface Controler */
lharoon 0:22612ae617a0 47 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
lharoon 0:22612ae617a0 48 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
lharoon 0:22612ae617a0 49 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
lharoon 0:22612ae617a0 50 UART2_IRQn = 28, /*!< UART2 Interrupt */
lharoon 0:22612ae617a0 51 UART3_IRQn = 29, /*!< UART3 Interrupt */
lharoon 0:22612ae617a0 52 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
lharoon 0:22612ae617a0 53 I2S_IRQn = 31, /*!< I2S Interrupt */
lharoon 0:22612ae617a0 54 } IRQn_Type;
lharoon 0:22612ae617a0 55
lharoon 0:22612ae617a0 56 /*
lharoon 0:22612ae617a0 57 * ==========================================================================
lharoon 0:22612ae617a0 58 * ----------- Processor and Core Peripheral Section ------------------------
lharoon 0:22612ae617a0 59 * ==========================================================================
lharoon 0:22612ae617a0 60 */
lharoon 0:22612ae617a0 61
lharoon 0:22612ae617a0 62 /* Configuration of the ARM7 Processor and Core Peripherals */
lharoon 0:22612ae617a0 63 #define __MPU_PRESENT 0 /*!< MPU present or not */
lharoon 0:22612ae617a0 64 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
lharoon 0:22612ae617a0 65 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
lharoon 0:22612ae617a0 66
lharoon 0:22612ae617a0 67
lharoon 0:22612ae617a0 68 #include <core_arm7.h>
lharoon 0:22612ae617a0 69 #include "system_LPC23xx.h" /* System Header */
lharoon 0:22612ae617a0 70
lharoon 0:22612ae617a0 71
lharoon 0:22612ae617a0 72 /******************************************************************************/
lharoon 0:22612ae617a0 73 /* Device Specific Peripheral registers structures */
lharoon 0:22612ae617a0 74 /******************************************************************************/
lharoon 0:22612ae617a0 75 #if defined ( __CC_ARM )
lharoon 0:22612ae617a0 76 #pragma anon_unions
lharoon 0:22612ae617a0 77 #endif
lharoon 0:22612ae617a0 78
lharoon 0:22612ae617a0 79 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
lharoon 0:22612ae617a0 80 typedef struct
lharoon 0:22612ae617a0 81 {
lharoon 0:22612ae617a0 82 __I uint32_t IRQStatus;
lharoon 0:22612ae617a0 83 __I uint32_t FIQStatus;
lharoon 0:22612ae617a0 84 __I uint32_t RawIntr;
lharoon 0:22612ae617a0 85 __IO uint32_t IntSelect;
lharoon 0:22612ae617a0 86 __IO uint32_t IntEnable;
lharoon 0:22612ae617a0 87 __O uint32_t IntEnClr;
lharoon 0:22612ae617a0 88 __IO uint32_t SoftInt;
lharoon 0:22612ae617a0 89 __O uint32_t SoftIntClr;
lharoon 0:22612ae617a0 90 __IO uint32_t Protection;
lharoon 0:22612ae617a0 91 __IO uint32_t SWPriorityMask;
lharoon 0:22612ae617a0 92 __IO uint32_t RESERVED0[54];
lharoon 0:22612ae617a0 93 __IO uint32_t VectAddr[32];
lharoon 0:22612ae617a0 94 __IO uint32_t RESERVED1[32];
lharoon 0:22612ae617a0 95 __IO uint32_t VectPriority[32];
lharoon 0:22612ae617a0 96 __IO uint32_t RESERVED2[800];
lharoon 0:22612ae617a0 97 __IO uint32_t Address;
lharoon 0:22612ae617a0 98 } LPC_VIC_TypeDef;
lharoon 0:22612ae617a0 99
lharoon 0:22612ae617a0 100 /*------------- System Control (SC) ------------------------------------------*/
lharoon 0:22612ae617a0 101 typedef struct
lharoon 0:22612ae617a0 102 {
lharoon 0:22612ae617a0 103 __IO uint32_t MAMCR;
lharoon 0:22612ae617a0 104 __IO uint32_t MAMTIM;
lharoon 0:22612ae617a0 105 uint32_t RESERVED0[14];
lharoon 0:22612ae617a0 106 __IO uint32_t MEMMAP;
lharoon 0:22612ae617a0 107 uint32_t RESERVED1[15];
lharoon 0:22612ae617a0 108 __IO uint32_t PLL0CON; /* Clocking and Power Control */
lharoon 0:22612ae617a0 109 __IO uint32_t PLL0CFG;
lharoon 0:22612ae617a0 110 __I uint32_t PLL0STAT;
lharoon 0:22612ae617a0 111 __O uint32_t PLL0FEED;
lharoon 0:22612ae617a0 112 uint32_t RESERVED2[12];
lharoon 0:22612ae617a0 113 __IO uint32_t PCON;
lharoon 0:22612ae617a0 114 __IO uint32_t PCONP;
lharoon 0:22612ae617a0 115 uint32_t RESERVED3[15];
lharoon 0:22612ae617a0 116 __IO uint32_t CCLKCFG;
lharoon 0:22612ae617a0 117 __IO uint32_t USBCLKCFG;
lharoon 0:22612ae617a0 118 __IO uint32_t CLKSRCSEL;
lharoon 0:22612ae617a0 119 uint32_t RESERVED4[12];
lharoon 0:22612ae617a0 120 __IO uint32_t EXTINT; /* External Interrupts */
lharoon 0:22612ae617a0 121 __IO uint32_t INTWAKE;
lharoon 0:22612ae617a0 122 __IO uint32_t EXTMODE;
lharoon 0:22612ae617a0 123 __IO uint32_t EXTPOLAR;
lharoon 0:22612ae617a0 124 uint32_t RESERVED6[12];
lharoon 0:22612ae617a0 125 __IO uint32_t RSID; /* Reset */
lharoon 0:22612ae617a0 126 __IO uint32_t CSPR;
lharoon 0:22612ae617a0 127 __IO uint32_t AHBCFG1;
lharoon 0:22612ae617a0 128 __IO uint32_t AHBCFG2;
lharoon 0:22612ae617a0 129 uint32_t RESERVED7[4];
lharoon 0:22612ae617a0 130 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
lharoon 0:22612ae617a0 131 __IO uint32_t IRCTRIM; /* Clock Dividers */
lharoon 0:22612ae617a0 132 __IO uint32_t PCLKSEL0;
lharoon 0:22612ae617a0 133 __IO uint32_t PCLKSEL1;
lharoon 0:22612ae617a0 134 uint32_t RESERVED8[4];
lharoon 0:22612ae617a0 135 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
lharoon 0:22612ae617a0 136 uint32_t RESERVED9;
lharoon 0:22612ae617a0 137 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
lharoon 0:22612ae617a0 138 } LPC_SC_TypeDef;
lharoon 0:22612ae617a0 139
lharoon 0:22612ae617a0 140 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
lharoon 0:22612ae617a0 141 typedef struct
lharoon 0:22612ae617a0 142 {
lharoon 0:22612ae617a0 143 __IO uint32_t PINSEL0;
lharoon 0:22612ae617a0 144 __IO uint32_t PINSEL1;
lharoon 0:22612ae617a0 145 __IO uint32_t PINSEL2;
lharoon 0:22612ae617a0 146 __IO uint32_t PINSEL3;
lharoon 0:22612ae617a0 147 __IO uint32_t PINSEL4;
lharoon 0:22612ae617a0 148 __IO uint32_t PINSEL5;
lharoon 0:22612ae617a0 149 __IO uint32_t PINSEL6;
lharoon 0:22612ae617a0 150 __IO uint32_t PINSEL7;
lharoon 0:22612ae617a0 151 __IO uint32_t PINSEL8;
lharoon 0:22612ae617a0 152 __IO uint32_t PINSEL9;
lharoon 0:22612ae617a0 153 __IO uint32_t PINSEL10;
lharoon 0:22612ae617a0 154 uint32_t RESERVED0[5];
lharoon 0:22612ae617a0 155 __IO uint32_t PINMODE0;
lharoon 0:22612ae617a0 156 __IO uint32_t PINMODE1;
lharoon 0:22612ae617a0 157 __IO uint32_t PINMODE2;
lharoon 0:22612ae617a0 158 __IO uint32_t PINMODE3;
lharoon 0:22612ae617a0 159 __IO uint32_t PINMODE4;
lharoon 0:22612ae617a0 160 __IO uint32_t PINMODE5;
lharoon 0:22612ae617a0 161 __IO uint32_t PINMODE6;
lharoon 0:22612ae617a0 162 __IO uint32_t PINMODE7;
lharoon 0:22612ae617a0 163 __IO uint32_t PINMODE8;
lharoon 0:22612ae617a0 164 __IO uint32_t PINMODE9;
lharoon 0:22612ae617a0 165 __IO uint32_t PINMODE_OD0;
lharoon 0:22612ae617a0 166 __IO uint32_t PINMODE_OD1;
lharoon 0:22612ae617a0 167 __IO uint32_t PINMODE_OD2;
lharoon 0:22612ae617a0 168 __IO uint32_t PINMODE_OD3;
lharoon 0:22612ae617a0 169 __IO uint32_t PINMODE_OD4;
lharoon 0:22612ae617a0 170 } LPC_PINCON_TypeDef;
lharoon 0:22612ae617a0 171
lharoon 0:22612ae617a0 172 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
lharoon 0:22612ae617a0 173 typedef struct
lharoon 0:22612ae617a0 174 {
lharoon 0:22612ae617a0 175 __IO uint32_t FIODIR;
lharoon 0:22612ae617a0 176 uint32_t RESERVED0[3];
lharoon 0:22612ae617a0 177 __IO uint32_t FIOMASK;
lharoon 0:22612ae617a0 178 __IO uint32_t FIOPIN;
lharoon 0:22612ae617a0 179 __IO uint32_t FIOSET;
lharoon 0:22612ae617a0 180 __O uint32_t FIOCLR;
lharoon 0:22612ae617a0 181 } LPC_GPIO_TypeDef;
lharoon 0:22612ae617a0 182
lharoon 0:22612ae617a0 183 typedef struct
lharoon 0:22612ae617a0 184 {
lharoon 0:22612ae617a0 185 __I uint32_t IntStatus;
lharoon 0:22612ae617a0 186 __I uint32_t IO0IntStatR;
lharoon 0:22612ae617a0 187 __I uint32_t IO0IntStatF;
lharoon 0:22612ae617a0 188 __O uint32_t IO0IntClr;
lharoon 0:22612ae617a0 189 __IO uint32_t IO0IntEnR;
lharoon 0:22612ae617a0 190 __IO uint32_t IO0IntEnF;
lharoon 0:22612ae617a0 191 uint32_t RESERVED0[3];
lharoon 0:22612ae617a0 192 __I uint32_t IO2IntStatR;
lharoon 0:22612ae617a0 193 __I uint32_t IO2IntStatF;
lharoon 0:22612ae617a0 194 __O uint32_t IO2IntClr;
lharoon 0:22612ae617a0 195 __IO uint32_t IO2IntEnR;
lharoon 0:22612ae617a0 196 __IO uint32_t IO2IntEnF;
lharoon 0:22612ae617a0 197 } LPC_GPIOINT_TypeDef;
lharoon 0:22612ae617a0 198
lharoon 0:22612ae617a0 199 /*------------- Timer (TIM) --------------------------------------------------*/
lharoon 0:22612ae617a0 200 typedef struct
lharoon 0:22612ae617a0 201 {
lharoon 0:22612ae617a0 202 __IO uint32_t IR;
lharoon 0:22612ae617a0 203 __IO uint32_t TCR;
lharoon 0:22612ae617a0 204 __IO uint32_t TC;
lharoon 0:22612ae617a0 205 __IO uint32_t PR;
lharoon 0:22612ae617a0 206 __IO uint32_t PC;
lharoon 0:22612ae617a0 207 __IO uint32_t MCR;
lharoon 0:22612ae617a0 208 __IO uint32_t MR0;
lharoon 0:22612ae617a0 209 __IO uint32_t MR1;
lharoon 0:22612ae617a0 210 __IO uint32_t MR2;
lharoon 0:22612ae617a0 211 __IO uint32_t MR3;
lharoon 0:22612ae617a0 212 __IO uint32_t CCR;
lharoon 0:22612ae617a0 213 __I uint32_t CR0;
lharoon 0:22612ae617a0 214 __I uint32_t CR1;
lharoon 0:22612ae617a0 215 uint32_t RESERVED0[2];
lharoon 0:22612ae617a0 216 __IO uint32_t EMR;
lharoon 0:22612ae617a0 217 uint32_t RESERVED1[12];
lharoon 0:22612ae617a0 218 __IO uint32_t CTCR;
lharoon 0:22612ae617a0 219 } LPC_TIM_TypeDef;
lharoon 0:22612ae617a0 220
lharoon 0:22612ae617a0 221 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
lharoon 0:22612ae617a0 222 typedef struct
lharoon 0:22612ae617a0 223 {
lharoon 0:22612ae617a0 224 __IO uint32_t IR;
lharoon 0:22612ae617a0 225 __IO uint32_t TCR;
lharoon 0:22612ae617a0 226 __IO uint32_t TC;
lharoon 0:22612ae617a0 227 __IO uint32_t PR;
lharoon 0:22612ae617a0 228 __IO uint32_t PC;
lharoon 0:22612ae617a0 229 __IO uint32_t MCR;
lharoon 0:22612ae617a0 230 __IO uint32_t MR0;
lharoon 0:22612ae617a0 231 __IO uint32_t MR1;
lharoon 0:22612ae617a0 232 __IO uint32_t MR2;
lharoon 0:22612ae617a0 233 __IO uint32_t MR3;
lharoon 0:22612ae617a0 234 __IO uint32_t CCR;
lharoon 0:22612ae617a0 235 __I uint32_t CR0;
lharoon 0:22612ae617a0 236 __I uint32_t CR1;
lharoon 0:22612ae617a0 237 __I uint32_t CR2;
lharoon 0:22612ae617a0 238 __I uint32_t CR3;
lharoon 0:22612ae617a0 239 uint32_t RESERVED0;
lharoon 0:22612ae617a0 240 __IO uint32_t MR4;
lharoon 0:22612ae617a0 241 __IO uint32_t MR5;
lharoon 0:22612ae617a0 242 __IO uint32_t MR6;
lharoon 0:22612ae617a0 243 __IO uint32_t PCR;
lharoon 0:22612ae617a0 244 __IO uint32_t LER;
lharoon 0:22612ae617a0 245 uint32_t RESERVED1[7];
lharoon 0:22612ae617a0 246 __IO uint32_t CTCR;
lharoon 0:22612ae617a0 247 } LPC_PWM_TypeDef;
lharoon 0:22612ae617a0 248
lharoon 0:22612ae617a0 249 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
lharoon 0:22612ae617a0 250 typedef struct
lharoon 0:22612ae617a0 251 {
lharoon 0:22612ae617a0 252 union {
lharoon 0:22612ae617a0 253 __I uint8_t RBR;
lharoon 0:22612ae617a0 254 __O uint8_t THR;
lharoon 0:22612ae617a0 255 __IO uint8_t DLL;
lharoon 0:22612ae617a0 256 uint32_t RESERVED0;
lharoon 0:22612ae617a0 257 };
lharoon 0:22612ae617a0 258 union {
lharoon 0:22612ae617a0 259 __IO uint8_t DLM;
lharoon 0:22612ae617a0 260 __IO uint32_t IER;
lharoon 0:22612ae617a0 261 };
lharoon 0:22612ae617a0 262 union {
lharoon 0:22612ae617a0 263 __I uint32_t IIR;
lharoon 0:22612ae617a0 264 __O uint8_t FCR;
lharoon 0:22612ae617a0 265 };
lharoon 0:22612ae617a0 266 __IO uint8_t LCR;
lharoon 0:22612ae617a0 267 uint8_t RESERVED1[7];
lharoon 0:22612ae617a0 268 __IO uint8_t LSR;
lharoon 0:22612ae617a0 269 uint8_t RESERVED2[7];
lharoon 0:22612ae617a0 270 __IO uint8_t SCR;
lharoon 0:22612ae617a0 271 uint8_t RESERVED3[3];
lharoon 0:22612ae617a0 272 __IO uint32_t ACR;
lharoon 0:22612ae617a0 273 __IO uint8_t ICR;
lharoon 0:22612ae617a0 274 uint8_t RESERVED4[3];
lharoon 0:22612ae617a0 275 __IO uint8_t FDR;
lharoon 0:22612ae617a0 276 uint8_t RESERVED5[7];
lharoon 0:22612ae617a0 277 __IO uint8_t TER;
lharoon 0:22612ae617a0 278 uint8_t RESERVED6[27];
lharoon 0:22612ae617a0 279 __IO uint8_t RS485CTRL;
lharoon 0:22612ae617a0 280 uint8_t RESERVED7[3];
lharoon 0:22612ae617a0 281 __IO uint8_t ADRMATCH;
lharoon 0:22612ae617a0 282 } LPC_UART_TypeDef;
lharoon 0:22612ae617a0 283
lharoon 0:22612ae617a0 284 typedef struct
lharoon 0:22612ae617a0 285 {
lharoon 0:22612ae617a0 286 union {
lharoon 0:22612ae617a0 287 __I uint8_t RBR;
lharoon 0:22612ae617a0 288 __O uint8_t THR;
lharoon 0:22612ae617a0 289 __IO uint8_t DLL;
lharoon 0:22612ae617a0 290 uint32_t RESERVED0;
lharoon 0:22612ae617a0 291 };
lharoon 0:22612ae617a0 292 union {
lharoon 0:22612ae617a0 293 __IO uint8_t DLM;
lharoon 0:22612ae617a0 294 __IO uint32_t IER;
lharoon 0:22612ae617a0 295 };
lharoon 0:22612ae617a0 296 union {
lharoon 0:22612ae617a0 297 __I uint32_t IIR;
lharoon 0:22612ae617a0 298 __O uint8_t FCR;
lharoon 0:22612ae617a0 299 };
lharoon 0:22612ae617a0 300 __IO uint8_t LCR;
lharoon 0:22612ae617a0 301 uint8_t RESERVED1[3];
lharoon 0:22612ae617a0 302 __IO uint8_t MCR;
lharoon 0:22612ae617a0 303 uint8_t RESERVED2[3];
lharoon 0:22612ae617a0 304 __IO uint8_t LSR;
lharoon 0:22612ae617a0 305 uint8_t RESERVED3[3];
lharoon 0:22612ae617a0 306 __IO uint8_t MSR;
lharoon 0:22612ae617a0 307 uint8_t RESERVED4[3];
lharoon 0:22612ae617a0 308 __IO uint8_t SCR;
lharoon 0:22612ae617a0 309 uint8_t RESERVED5[3];
lharoon 0:22612ae617a0 310 __IO uint32_t ACR;
lharoon 0:22612ae617a0 311 uint32_t RESERVED6;
lharoon 0:22612ae617a0 312 __IO uint32_t FDR;
lharoon 0:22612ae617a0 313 uint32_t RESERVED7;
lharoon 0:22612ae617a0 314 __IO uint8_t TER;
lharoon 0:22612ae617a0 315 uint8_t RESERVED8[27];
lharoon 0:22612ae617a0 316 __IO uint8_t RS485CTRL;
lharoon 0:22612ae617a0 317 uint8_t RESERVED9[3];
lharoon 0:22612ae617a0 318 __IO uint8_t ADRMATCH;
lharoon 0:22612ae617a0 319 uint8_t RESERVED10[3];
lharoon 0:22612ae617a0 320 __IO uint8_t RS485DLY;
lharoon 0:22612ae617a0 321 } LPC_UART1_TypeDef;
lharoon 0:22612ae617a0 322
lharoon 0:22612ae617a0 323 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
lharoon 0:22612ae617a0 324 typedef struct
lharoon 0:22612ae617a0 325 {
lharoon 0:22612ae617a0 326 __IO uint32_t SPCR;
lharoon 0:22612ae617a0 327 __I uint32_t SPSR;
lharoon 0:22612ae617a0 328 __IO uint32_t SPDR;
lharoon 0:22612ae617a0 329 __IO uint32_t SPCCR;
lharoon 0:22612ae617a0 330 uint32_t RESERVED0[3];
lharoon 0:22612ae617a0 331 __IO uint32_t SPINT;
lharoon 0:22612ae617a0 332 } LPC_SPI_TypeDef;
lharoon 0:22612ae617a0 333
lharoon 0:22612ae617a0 334 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
lharoon 0:22612ae617a0 335 typedef struct
lharoon 0:22612ae617a0 336 {
lharoon 0:22612ae617a0 337 __IO uint32_t CR0;
lharoon 0:22612ae617a0 338 __IO uint32_t CR1;
lharoon 0:22612ae617a0 339 __IO uint32_t DR;
lharoon 0:22612ae617a0 340 __I uint32_t SR;
lharoon 0:22612ae617a0 341 __IO uint32_t CPSR;
lharoon 0:22612ae617a0 342 __IO uint32_t IMSC;
lharoon 0:22612ae617a0 343 __IO uint32_t RIS;
lharoon 0:22612ae617a0 344 __IO uint32_t MIS;
lharoon 0:22612ae617a0 345 __IO uint32_t ICR;
lharoon 0:22612ae617a0 346 __IO uint32_t DMACR;
lharoon 0:22612ae617a0 347 } LPC_SSP_TypeDef;
lharoon 0:22612ae617a0 348
lharoon 0:22612ae617a0 349 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
lharoon 0:22612ae617a0 350 typedef struct
lharoon 0:22612ae617a0 351 {
lharoon 0:22612ae617a0 352 __IO uint32_t I2CONSET;
lharoon 0:22612ae617a0 353 __I uint32_t I2STAT;
lharoon 0:22612ae617a0 354 __IO uint32_t I2DAT;
lharoon 0:22612ae617a0 355 __IO uint32_t I2ADR0;
lharoon 0:22612ae617a0 356 __IO uint32_t I2SCLH;
lharoon 0:22612ae617a0 357 __IO uint32_t I2SCLL;
lharoon 0:22612ae617a0 358 __O uint32_t I2CONCLR;
lharoon 0:22612ae617a0 359 __IO uint32_t MMCTRL;
lharoon 0:22612ae617a0 360 __IO uint32_t I2ADR1;
lharoon 0:22612ae617a0 361 __IO uint32_t I2ADR2;
lharoon 0:22612ae617a0 362 __IO uint32_t I2ADR3;
lharoon 0:22612ae617a0 363 __I uint32_t I2DATA_BUFFER;
lharoon 0:22612ae617a0 364 __IO uint32_t I2MASK0;
lharoon 0:22612ae617a0 365 __IO uint32_t I2MASK1;
lharoon 0:22612ae617a0 366 __IO uint32_t I2MASK2;
lharoon 0:22612ae617a0 367 __IO uint32_t I2MASK3;
lharoon 0:22612ae617a0 368 } LPC_I2C_TypeDef;
lharoon 0:22612ae617a0 369
lharoon 0:22612ae617a0 370 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
lharoon 0:22612ae617a0 371 typedef struct
lharoon 0:22612ae617a0 372 {
lharoon 0:22612ae617a0 373 __IO uint32_t I2SDAO;
lharoon 0:22612ae617a0 374 __I uint32_t I2SDAI;
lharoon 0:22612ae617a0 375 __O uint32_t I2STXFIFO;
lharoon 0:22612ae617a0 376 __I uint32_t I2SRXFIFO;
lharoon 0:22612ae617a0 377 __I uint32_t I2SSTATE;
lharoon 0:22612ae617a0 378 __IO uint32_t I2SDMA1;
lharoon 0:22612ae617a0 379 __IO uint32_t I2SDMA2;
lharoon 0:22612ae617a0 380 __IO uint32_t I2SIRQ;
lharoon 0:22612ae617a0 381 __IO uint32_t I2STXRATE;
lharoon 0:22612ae617a0 382 __IO uint32_t I2SRXRATE;
lharoon 0:22612ae617a0 383 __IO uint32_t I2STXBITRATE;
lharoon 0:22612ae617a0 384 __IO uint32_t I2SRXBITRATE;
lharoon 0:22612ae617a0 385 __IO uint32_t I2STXMODE;
lharoon 0:22612ae617a0 386 __IO uint32_t I2SRXMODE;
lharoon 0:22612ae617a0 387 } LPC_I2S_TypeDef;
lharoon 0:22612ae617a0 388
lharoon 0:22612ae617a0 389 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
lharoon 0:22612ae617a0 390 typedef struct
lharoon 0:22612ae617a0 391 {
lharoon 0:22612ae617a0 392 __IO uint8_t ILR;
lharoon 0:22612ae617a0 393 uint8_t RESERVED0[3];
lharoon 0:22612ae617a0 394 __IO uint8_t CTC;
lharoon 0:22612ae617a0 395 uint8_t RESERVED1[3];
lharoon 0:22612ae617a0 396 __IO uint8_t CCR;
lharoon 0:22612ae617a0 397 uint8_t RESERVED2[3];
lharoon 0:22612ae617a0 398 __IO uint8_t CIIR;
lharoon 0:22612ae617a0 399 uint8_t RESERVED3[3];
lharoon 0:22612ae617a0 400 __IO uint8_t AMR;
lharoon 0:22612ae617a0 401 uint8_t RESERVED4[3];
lharoon 0:22612ae617a0 402 __I uint32_t CTIME0;
lharoon 0:22612ae617a0 403 __I uint32_t CTIME1;
lharoon 0:22612ae617a0 404 __I uint32_t CTIME2;
lharoon 0:22612ae617a0 405 __IO uint8_t SEC;
lharoon 0:22612ae617a0 406 uint8_t RESERVED5[3];
lharoon 0:22612ae617a0 407 __IO uint8_t MIN;
lharoon 0:22612ae617a0 408 uint8_t RESERVED6[3];
lharoon 0:22612ae617a0 409 __IO uint8_t HOUR;
lharoon 0:22612ae617a0 410 uint8_t RESERVED7[3];
lharoon 0:22612ae617a0 411 __IO uint8_t DOM;
lharoon 0:22612ae617a0 412 uint8_t RESERVED8[3];
lharoon 0:22612ae617a0 413 __IO uint8_t DOW;
lharoon 0:22612ae617a0 414 uint8_t RESERVED9[3];
lharoon 0:22612ae617a0 415 __IO uint16_t DOY;
lharoon 0:22612ae617a0 416 uint16_t RESERVED10;
lharoon 0:22612ae617a0 417 __IO uint8_t MONTH;
lharoon 0:22612ae617a0 418 uint8_t RESERVED11[3];
lharoon 0:22612ae617a0 419 __IO uint16_t YEAR;
lharoon 0:22612ae617a0 420 uint16_t RESERVED12;
lharoon 0:22612ae617a0 421 __IO uint32_t CALIBRATION;
lharoon 0:22612ae617a0 422 __IO uint32_t GPREG0;
lharoon 0:22612ae617a0 423 __IO uint32_t GPREG1;
lharoon 0:22612ae617a0 424 __IO uint32_t GPREG2;
lharoon 0:22612ae617a0 425 __IO uint32_t GPREG3;
lharoon 0:22612ae617a0 426 __IO uint32_t GPREG4;
lharoon 0:22612ae617a0 427 __IO uint8_t WAKEUPDIS;
lharoon 0:22612ae617a0 428 uint8_t RESERVED13[3];
lharoon 0:22612ae617a0 429 __IO uint8_t PWRCTRL;
lharoon 0:22612ae617a0 430 uint8_t RESERVED14[3];
lharoon 0:22612ae617a0 431 __IO uint8_t ALSEC;
lharoon 0:22612ae617a0 432 uint8_t RESERVED15[3];
lharoon 0:22612ae617a0 433 __IO uint8_t ALMIN;
lharoon 0:22612ae617a0 434 uint8_t RESERVED16[3];
lharoon 0:22612ae617a0 435 __IO uint8_t ALHOUR;
lharoon 0:22612ae617a0 436 uint8_t RESERVED17[3];
lharoon 0:22612ae617a0 437 __IO uint8_t ALDOM;
lharoon 0:22612ae617a0 438 uint8_t RESERVED18[3];
lharoon 0:22612ae617a0 439 __IO uint8_t ALDOW;
lharoon 0:22612ae617a0 440 uint8_t RESERVED19[3];
lharoon 0:22612ae617a0 441 __IO uint16_t ALDOY;
lharoon 0:22612ae617a0 442 uint16_t RESERVED20;
lharoon 0:22612ae617a0 443 __IO uint8_t ALMON;
lharoon 0:22612ae617a0 444 uint8_t RESERVED21[3];
lharoon 0:22612ae617a0 445 __IO uint16_t ALYEAR;
lharoon 0:22612ae617a0 446 uint16_t RESERVED22;
lharoon 0:22612ae617a0 447 } LPC_RTC_TypeDef;
lharoon 0:22612ae617a0 448
lharoon 0:22612ae617a0 449 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
lharoon 0:22612ae617a0 450 typedef struct
lharoon 0:22612ae617a0 451 {
lharoon 0:22612ae617a0 452 __IO uint8_t WDMOD;
lharoon 0:22612ae617a0 453 uint8_t RESERVED0[3];
lharoon 0:22612ae617a0 454 __IO uint32_t WDTC;
lharoon 0:22612ae617a0 455 __O uint8_t WDFEED;
lharoon 0:22612ae617a0 456 uint8_t RESERVED1[3];
lharoon 0:22612ae617a0 457 __I uint32_t WDTV;
lharoon 0:22612ae617a0 458 __IO uint32_t WDCLKSEL;
lharoon 0:22612ae617a0 459 } LPC_WDT_TypeDef;
lharoon 0:22612ae617a0 460
lharoon 0:22612ae617a0 461 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
lharoon 0:22612ae617a0 462 typedef struct
lharoon 0:22612ae617a0 463 {
lharoon 0:22612ae617a0 464 __IO uint32_t ADCR;
lharoon 0:22612ae617a0 465 __IO uint32_t ADGDR;
lharoon 0:22612ae617a0 466 uint32_t RESERVED0;
lharoon 0:22612ae617a0 467 __IO uint32_t ADINTEN;
lharoon 0:22612ae617a0 468 __I uint32_t ADDR0;
lharoon 0:22612ae617a0 469 __I uint32_t ADDR1;
lharoon 0:22612ae617a0 470 __I uint32_t ADDR2;
lharoon 0:22612ae617a0 471 __I uint32_t ADDR3;
lharoon 0:22612ae617a0 472 __I uint32_t ADDR4;
lharoon 0:22612ae617a0 473 __I uint32_t ADDR5;
lharoon 0:22612ae617a0 474 __I uint32_t ADDR6;
lharoon 0:22612ae617a0 475 __I uint32_t ADDR7;
lharoon 0:22612ae617a0 476 __I uint32_t ADSTAT;
lharoon 0:22612ae617a0 477 __IO uint32_t ADTRM;
lharoon 0:22612ae617a0 478 } LPC_ADC_TypeDef;
lharoon 0:22612ae617a0 479
lharoon 0:22612ae617a0 480 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
lharoon 0:22612ae617a0 481 typedef struct
lharoon 0:22612ae617a0 482 {
lharoon 0:22612ae617a0 483 __IO uint32_t DACR;
lharoon 0:22612ae617a0 484 __IO uint32_t DACCTRL;
lharoon 0:22612ae617a0 485 __IO uint16_t DACCNTVAL;
lharoon 0:22612ae617a0 486 } LPC_DAC_TypeDef;
lharoon 0:22612ae617a0 487
lharoon 0:22612ae617a0 488 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
lharoon 0:22612ae617a0 489 typedef struct
lharoon 0:22612ae617a0 490 {
lharoon 0:22612ae617a0 491 __IO uint32_t MCIPower; /* Power control */
lharoon 0:22612ae617a0 492 __IO uint32_t MCIClock; /* Clock control */
lharoon 0:22612ae617a0 493 __IO uint32_t MCIArgument;
lharoon 0:22612ae617a0 494 __IO uint32_t MMCCommand;
lharoon 0:22612ae617a0 495 __I uint32_t MCIRespCmd;
lharoon 0:22612ae617a0 496 __I uint32_t MCIResponse0;
lharoon 0:22612ae617a0 497 __I uint32_t MCIResponse1;
lharoon 0:22612ae617a0 498 __I uint32_t MCIResponse2;
lharoon 0:22612ae617a0 499 __I uint32_t MCIResponse3;
lharoon 0:22612ae617a0 500 __IO uint32_t MCIDataTimer;
lharoon 0:22612ae617a0 501 __IO uint32_t MCIDataLength;
lharoon 0:22612ae617a0 502 __IO uint32_t MCIDataCtrl;
lharoon 0:22612ae617a0 503 __I uint32_t MCIDataCnt;
lharoon 0:22612ae617a0 504 } LPC_MCI_TypeDef;
lharoon 0:22612ae617a0 505
lharoon 0:22612ae617a0 506 /*------------- Controller Area Network (CAN) --------------------------------*/
lharoon 0:22612ae617a0 507 typedef struct
lharoon 0:22612ae617a0 508 {
lharoon 0:22612ae617a0 509 __IO uint32_t mask[512]; /* ID Masks */
lharoon 0:22612ae617a0 510 } LPC_CANAF_RAM_TypeDef;
lharoon 0:22612ae617a0 511
lharoon 0:22612ae617a0 512 typedef struct /* Acceptance Filter Registers */
lharoon 0:22612ae617a0 513 {
lharoon 0:22612ae617a0 514 __IO uint32_t AFMR;
lharoon 0:22612ae617a0 515 __IO uint32_t SFF_sa;
lharoon 0:22612ae617a0 516 __IO uint32_t SFF_GRP_sa;
lharoon 0:22612ae617a0 517 __IO uint32_t EFF_sa;
lharoon 0:22612ae617a0 518 __IO uint32_t EFF_GRP_sa;
lharoon 0:22612ae617a0 519 __IO uint32_t ENDofTable;
lharoon 0:22612ae617a0 520 __I uint32_t LUTerrAd;
lharoon 0:22612ae617a0 521 __I uint32_t LUTerr;
lharoon 0:22612ae617a0 522 } LPC_CANAF_TypeDef;
lharoon 0:22612ae617a0 523
lharoon 0:22612ae617a0 524 typedef struct /* Central Registers */
lharoon 0:22612ae617a0 525 {
lharoon 0:22612ae617a0 526 __I uint32_t CANTxSR;
lharoon 0:22612ae617a0 527 __I uint32_t CANRxSR;
lharoon 0:22612ae617a0 528 __I uint32_t CANMSR;
lharoon 0:22612ae617a0 529 } LPC_CANCR_TypeDef;
lharoon 0:22612ae617a0 530
lharoon 0:22612ae617a0 531 typedef struct /* Controller Registers */
lharoon 0:22612ae617a0 532 {
lharoon 0:22612ae617a0 533 __IO uint32_t MOD;
lharoon 0:22612ae617a0 534 __O uint32_t CMR;
lharoon 0:22612ae617a0 535 __IO uint32_t GSR;
lharoon 0:22612ae617a0 536 __I uint32_t ICR;
lharoon 0:22612ae617a0 537 __IO uint32_t IER;
lharoon 0:22612ae617a0 538 __IO uint32_t BTR;
lharoon 0:22612ae617a0 539 __IO uint32_t EWL;
lharoon 0:22612ae617a0 540 __I uint32_t SR;
lharoon 0:22612ae617a0 541 __IO uint32_t RFS;
lharoon 0:22612ae617a0 542 __IO uint32_t RID;
lharoon 0:22612ae617a0 543 __IO uint32_t RDA;
lharoon 0:22612ae617a0 544 __IO uint32_t RDB;
lharoon 0:22612ae617a0 545 __IO uint32_t TFI1;
lharoon 0:22612ae617a0 546 __IO uint32_t TID1;
lharoon 0:22612ae617a0 547 __IO uint32_t TDA1;
lharoon 0:22612ae617a0 548 __IO uint32_t TDB1;
lharoon 0:22612ae617a0 549 __IO uint32_t TFI2;
lharoon 0:22612ae617a0 550 __IO uint32_t TID2;
lharoon 0:22612ae617a0 551 __IO uint32_t TDA2;
lharoon 0:22612ae617a0 552 __IO uint32_t TDB2;
lharoon 0:22612ae617a0 553 __IO uint32_t TFI3;
lharoon 0:22612ae617a0 554 __IO uint32_t TID3;
lharoon 0:22612ae617a0 555 __IO uint32_t TDA3;
lharoon 0:22612ae617a0 556 __IO uint32_t TDB3;
lharoon 0:22612ae617a0 557 } LPC_CAN_TypeDef;
lharoon 0:22612ae617a0 558
lharoon 0:22612ae617a0 559 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
lharoon 0:22612ae617a0 560 typedef struct /* Common Registers */
lharoon 0:22612ae617a0 561 {
lharoon 0:22612ae617a0 562 __I uint32_t DMACIntStat;
lharoon 0:22612ae617a0 563 __I uint32_t DMACIntTCStat;
lharoon 0:22612ae617a0 564 __O uint32_t DMACIntTCClear;
lharoon 0:22612ae617a0 565 __I uint32_t DMACIntErrStat;
lharoon 0:22612ae617a0 566 __O uint32_t DMACIntErrClr;
lharoon 0:22612ae617a0 567 __I uint32_t DMACRawIntTCStat;
lharoon 0:22612ae617a0 568 __I uint32_t DMACRawIntErrStat;
lharoon 0:22612ae617a0 569 __I uint32_t DMACEnbldChns;
lharoon 0:22612ae617a0 570 __IO uint32_t DMACSoftBReq;
lharoon 0:22612ae617a0 571 __IO uint32_t DMACSoftSReq;
lharoon 0:22612ae617a0 572 __IO uint32_t DMACSoftLBReq;
lharoon 0:22612ae617a0 573 __IO uint32_t DMACSoftLSReq;
lharoon 0:22612ae617a0 574 __IO uint32_t DMACConfig;
lharoon 0:22612ae617a0 575 __IO uint32_t DMACSync;
lharoon 0:22612ae617a0 576 } LPC_GPDMA_TypeDef;
lharoon 0:22612ae617a0 577
lharoon 0:22612ae617a0 578 typedef struct /* Channel Registers */
lharoon 0:22612ae617a0 579 {
lharoon 0:22612ae617a0 580 __IO uint32_t DMACCSrcAddr;
lharoon 0:22612ae617a0 581 __IO uint32_t DMACCDestAddr;
lharoon 0:22612ae617a0 582 __IO uint32_t DMACCLLI;
lharoon 0:22612ae617a0 583 __IO uint32_t DMACCControl;
lharoon 0:22612ae617a0 584 __IO uint32_t DMACCConfig;
lharoon 0:22612ae617a0 585 } LPC_GPDMACH_TypeDef;
lharoon 0:22612ae617a0 586
lharoon 0:22612ae617a0 587 /*------------- Universal Serial Bus (USB) -----------------------------------*/
lharoon 0:22612ae617a0 588 typedef struct
lharoon 0:22612ae617a0 589 {
lharoon 0:22612ae617a0 590 __I uint32_t HcRevision; /* USB Host Registers */
lharoon 0:22612ae617a0 591 __IO uint32_t HcControl;
lharoon 0:22612ae617a0 592 __IO uint32_t HcCommandStatus;
lharoon 0:22612ae617a0 593 __IO uint32_t HcInterruptStatus;
lharoon 0:22612ae617a0 594 __IO uint32_t HcInterruptEnable;
lharoon 0:22612ae617a0 595 __IO uint32_t HcInterruptDisable;
lharoon 0:22612ae617a0 596 __IO uint32_t HcHCCA;
lharoon 0:22612ae617a0 597 __I uint32_t HcPeriodCurrentED;
lharoon 0:22612ae617a0 598 __IO uint32_t HcControlHeadED;
lharoon 0:22612ae617a0 599 __IO uint32_t HcControlCurrentED;
lharoon 0:22612ae617a0 600 __IO uint32_t HcBulkHeadED;
lharoon 0:22612ae617a0 601 __IO uint32_t HcBulkCurrentED;
lharoon 0:22612ae617a0 602 __I uint32_t HcDoneHead;
lharoon 0:22612ae617a0 603 __IO uint32_t HcFmInterval;
lharoon 0:22612ae617a0 604 __I uint32_t HcFmRemaining;
lharoon 0:22612ae617a0 605 __I uint32_t HcFmNumber;
lharoon 0:22612ae617a0 606 __IO uint32_t HcPeriodicStart;
lharoon 0:22612ae617a0 607 __IO uint32_t HcLSTreshold;
lharoon 0:22612ae617a0 608 __IO uint32_t HcRhDescriptorA;
lharoon 0:22612ae617a0 609 __IO uint32_t HcRhDescriptorB;
lharoon 0:22612ae617a0 610 __IO uint32_t HcRhStatus;
lharoon 0:22612ae617a0 611 __IO uint32_t HcRhPortStatus1;
lharoon 0:22612ae617a0 612 __IO uint32_t HcRhPortStatus2;
lharoon 0:22612ae617a0 613 uint32_t RESERVED0[40];
lharoon 0:22612ae617a0 614 __I uint32_t Module_ID;
lharoon 0:22612ae617a0 615
lharoon 0:22612ae617a0 616 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
lharoon 0:22612ae617a0 617 __IO uint32_t OTGIntEn;
lharoon 0:22612ae617a0 618 __O uint32_t OTGIntSet;
lharoon 0:22612ae617a0 619 __O uint32_t OTGIntClr;
lharoon 0:22612ae617a0 620 __IO uint32_t OTGStCtrl;
lharoon 0:22612ae617a0 621 __IO uint32_t OTGTmr;
lharoon 0:22612ae617a0 622 uint32_t RESERVED1[58];
lharoon 0:22612ae617a0 623
lharoon 0:22612ae617a0 624 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
lharoon 0:22612ae617a0 625 __IO uint32_t USBDevIntEn;
lharoon 0:22612ae617a0 626 __O uint32_t USBDevIntClr;
lharoon 0:22612ae617a0 627 __O uint32_t USBDevIntSet;
lharoon 0:22612ae617a0 628
lharoon 0:22612ae617a0 629 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
lharoon 0:22612ae617a0 630 __I uint32_t USBCmdData;
lharoon 0:22612ae617a0 631
lharoon 0:22612ae617a0 632 __I uint32_t USBRxData; /* USB Device Transfer Registers */
lharoon 0:22612ae617a0 633 __O uint32_t USBTxData;
lharoon 0:22612ae617a0 634 __I uint32_t USBRxPLen;
lharoon 0:22612ae617a0 635 __O uint32_t USBTxPLen;
lharoon 0:22612ae617a0 636 __IO uint32_t USBCtrl;
lharoon 0:22612ae617a0 637 __O uint32_t USBDevIntPri;
lharoon 0:22612ae617a0 638
lharoon 0:22612ae617a0 639 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
lharoon 0:22612ae617a0 640 __IO uint32_t USBEpIntEn;
lharoon 0:22612ae617a0 641 __O uint32_t USBEpIntClr;
lharoon 0:22612ae617a0 642 __O uint32_t USBEpIntSet;
lharoon 0:22612ae617a0 643 __O uint32_t USBEpIntPri;
lharoon 0:22612ae617a0 644
lharoon 0:22612ae617a0 645 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
lharoon 0:22612ae617a0 646 __O uint32_t USBEpInd;
lharoon 0:22612ae617a0 647 __IO uint32_t USBMaxPSize;
lharoon 0:22612ae617a0 648
lharoon 0:22612ae617a0 649 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
lharoon 0:22612ae617a0 650 __O uint32_t USBDMARClr;
lharoon 0:22612ae617a0 651 __O uint32_t USBDMARSet;
lharoon 0:22612ae617a0 652 uint32_t RESERVED2[9];
lharoon 0:22612ae617a0 653 __IO uint32_t USBUDCAH;
lharoon 0:22612ae617a0 654 __I uint32_t USBEpDMASt;
lharoon 0:22612ae617a0 655 __O uint32_t USBEpDMAEn;
lharoon 0:22612ae617a0 656 __O uint32_t USBEpDMADis;
lharoon 0:22612ae617a0 657 __I uint32_t USBDMAIntSt;
lharoon 0:22612ae617a0 658 __IO uint32_t USBDMAIntEn;
lharoon 0:22612ae617a0 659 uint32_t RESERVED3[2];
lharoon 0:22612ae617a0 660 __I uint32_t USBEoTIntSt;
lharoon 0:22612ae617a0 661 __O uint32_t USBEoTIntClr;
lharoon 0:22612ae617a0 662 __O uint32_t USBEoTIntSet;
lharoon 0:22612ae617a0 663 __I uint32_t USBNDDRIntSt;
lharoon 0:22612ae617a0 664 __O uint32_t USBNDDRIntClr;
lharoon 0:22612ae617a0 665 __O uint32_t USBNDDRIntSet;
lharoon 0:22612ae617a0 666 __I uint32_t USBSysErrIntSt;
lharoon 0:22612ae617a0 667 __O uint32_t USBSysErrIntClr;
lharoon 0:22612ae617a0 668 __O uint32_t USBSysErrIntSet;
lharoon 0:22612ae617a0 669 uint32_t RESERVED4[15];
lharoon 0:22612ae617a0 670
lharoon 0:22612ae617a0 671 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
lharoon 0:22612ae617a0 672 __O uint32_t I2C_WO;
lharoon 0:22612ae617a0 673 __I uint32_t I2C_STS;
lharoon 0:22612ae617a0 674 __IO uint32_t I2C_CTL;
lharoon 0:22612ae617a0 675 __IO uint32_t I2C_CLKHI;
lharoon 0:22612ae617a0 676 __O uint32_t I2C_CLKLO;
lharoon 0:22612ae617a0 677 uint32_t RESERVED5[823];
lharoon 0:22612ae617a0 678
lharoon 0:22612ae617a0 679 union {
lharoon 0:22612ae617a0 680 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
lharoon 0:22612ae617a0 681 __IO uint32_t OTGClkCtrl;
lharoon 0:22612ae617a0 682 };
lharoon 0:22612ae617a0 683 union {
lharoon 0:22612ae617a0 684 __I uint32_t USBClkSt;
lharoon 0:22612ae617a0 685 __I uint32_t OTGClkSt;
lharoon 0:22612ae617a0 686 };
lharoon 0:22612ae617a0 687 } LPC_USB_TypeDef;
lharoon 0:22612ae617a0 688
lharoon 0:22612ae617a0 689 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
lharoon 0:22612ae617a0 690 typedef struct
lharoon 0:22612ae617a0 691 {
lharoon 0:22612ae617a0 692 __IO uint32_t MAC1; /* MAC Registers */
lharoon 0:22612ae617a0 693 __IO uint32_t MAC2;
lharoon 0:22612ae617a0 694 __IO uint32_t IPGT;
lharoon 0:22612ae617a0 695 __IO uint32_t IPGR;
lharoon 0:22612ae617a0 696 __IO uint32_t CLRT;
lharoon 0:22612ae617a0 697 __IO uint32_t MAXF;
lharoon 0:22612ae617a0 698 __IO uint32_t SUPP;
lharoon 0:22612ae617a0 699 __IO uint32_t TEST;
lharoon 0:22612ae617a0 700 __IO uint32_t MCFG;
lharoon 0:22612ae617a0 701 __IO uint32_t MCMD;
lharoon 0:22612ae617a0 702 __IO uint32_t MADR;
lharoon 0:22612ae617a0 703 __O uint32_t MWTD;
lharoon 0:22612ae617a0 704 __I uint32_t MRDD;
lharoon 0:22612ae617a0 705 __I uint32_t MIND;
lharoon 0:22612ae617a0 706 uint32_t RESERVED0[2];
lharoon 0:22612ae617a0 707 __IO uint32_t SA0;
lharoon 0:22612ae617a0 708 __IO uint32_t SA1;
lharoon 0:22612ae617a0 709 __IO uint32_t SA2;
lharoon 0:22612ae617a0 710 uint32_t RESERVED1[45];
lharoon 0:22612ae617a0 711 __IO uint32_t Command; /* Control Registers */
lharoon 0:22612ae617a0 712 __I uint32_t Status;
lharoon 0:22612ae617a0 713 __IO uint32_t RxDescriptor;
lharoon 0:22612ae617a0 714 __IO uint32_t RxStatus;
lharoon 0:22612ae617a0 715 __IO uint32_t RxDescriptorNumber;
lharoon 0:22612ae617a0 716 __I uint32_t RxProduceIndex;
lharoon 0:22612ae617a0 717 __IO uint32_t RxConsumeIndex;
lharoon 0:22612ae617a0 718 __IO uint32_t TxDescriptor;
lharoon 0:22612ae617a0 719 __IO uint32_t TxStatus;
lharoon 0:22612ae617a0 720 __IO uint32_t TxDescriptorNumber;
lharoon 0:22612ae617a0 721 __IO uint32_t TxProduceIndex;
lharoon 0:22612ae617a0 722 __I uint32_t TxConsumeIndex;
lharoon 0:22612ae617a0 723 uint32_t RESERVED2[10];
lharoon 0:22612ae617a0 724 __I uint32_t TSV0;
lharoon 0:22612ae617a0 725 __I uint32_t TSV1;
lharoon 0:22612ae617a0 726 __I uint32_t RSV;
lharoon 0:22612ae617a0 727 uint32_t RESERVED3[3];
lharoon 0:22612ae617a0 728 __IO uint32_t FlowControlCounter;
lharoon 0:22612ae617a0 729 __I uint32_t FlowControlStatus;
lharoon 0:22612ae617a0 730 uint32_t RESERVED4[34];
lharoon 0:22612ae617a0 731 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
lharoon 0:22612ae617a0 732 __IO uint32_t RxFilterWoLStatus;
lharoon 0:22612ae617a0 733 __IO uint32_t RxFilterWoLClear;
lharoon 0:22612ae617a0 734 uint32_t RESERVED5;
lharoon 0:22612ae617a0 735 __IO uint32_t HashFilterL;
lharoon 0:22612ae617a0 736 __IO uint32_t HashFilterH;
lharoon 0:22612ae617a0 737 uint32_t RESERVED6[882];
lharoon 0:22612ae617a0 738 __I uint32_t IntStatus; /* Module Control Registers */
lharoon 0:22612ae617a0 739 __IO uint32_t IntEnable;
lharoon 0:22612ae617a0 740 __O uint32_t IntClear;
lharoon 0:22612ae617a0 741 __O uint32_t IntSet;
lharoon 0:22612ae617a0 742 uint32_t RESERVED7;
lharoon 0:22612ae617a0 743 __IO uint32_t PowerDown;
lharoon 0:22612ae617a0 744 uint32_t RESERVED8;
lharoon 0:22612ae617a0 745 __IO uint32_t Module_ID;
lharoon 0:22612ae617a0 746 } LPC_EMAC_TypeDef;
lharoon 0:22612ae617a0 747
lharoon 0:22612ae617a0 748 #if defined ( __CC_ARM )
lharoon 0:22612ae617a0 749 #pragma no_anon_unions
lharoon 0:22612ae617a0 750 #endif
lharoon 0:22612ae617a0 751
lharoon 0:22612ae617a0 752 /******************************************************************************/
lharoon 0:22612ae617a0 753 /* Peripheral memory map */
lharoon 0:22612ae617a0 754 /******************************************************************************/
lharoon 0:22612ae617a0 755 /* Base addresses */
lharoon 0:22612ae617a0 756
lharoon 0:22612ae617a0 757 /* AHB Peripheral # 0 */
lharoon 0:22612ae617a0 758
lharoon 0:22612ae617a0 759 /*
lharoon 0:22612ae617a0 760 #define FLASH_BASE (0x00000000UL)
lharoon 0:22612ae617a0 761 #define RAM_BASE (0x10000000UL)
lharoon 0:22612ae617a0 762 #define GPIO_BASE (0x2009C000UL)
lharoon 0:22612ae617a0 763 #define APB0_BASE (0x40000000UL)
lharoon 0:22612ae617a0 764 #define APB1_BASE (0x40080000UL)
lharoon 0:22612ae617a0 765 #define AHB_BASE (0x50000000UL)
lharoon 0:22612ae617a0 766 #define CM3_BASE (0xE0000000UL)
lharoon 0:22612ae617a0 767 */
lharoon 0:22612ae617a0 768
lharoon 0:22612ae617a0 769 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
lharoon 0:22612ae617a0 770
lharoon 0:22612ae617a0 771 #define LPC_WDT_BASE (0xE0000000)
lharoon 0:22612ae617a0 772 #define LPC_TIM0_BASE (0xE0004000)
lharoon 0:22612ae617a0 773 #define LPC_TIM1_BASE (0xE0008000)
lharoon 0:22612ae617a0 774 #define LPC_UART0_BASE (0xE000C000)
lharoon 0:22612ae617a0 775 #define LPC_UART1_BASE (0xE0010000)
lharoon 0:22612ae617a0 776 #define LPC_PWM1_BASE (0xE0018000)
lharoon 0:22612ae617a0 777 #define LPC_I2C0_BASE (0xE001C000)
lharoon 0:22612ae617a0 778 #define LPC_SPI_BASE (0xE0020000)
lharoon 0:22612ae617a0 779 #define LPC_RTC_BASE (0xE0024000)
lharoon 0:22612ae617a0 780 #define LPC_GPIOINT_BASE (0xE0028080)
lharoon 0:22612ae617a0 781 #define LPC_PINCON_BASE (0xE002C000)
lharoon 0:22612ae617a0 782 #define LPC_SSP1_BASE (0xE0030000)
lharoon 0:22612ae617a0 783 #define LPC_ADC_BASE (0xE0034000)
lharoon 0:22612ae617a0 784 #define LPC_CANAF_RAM_BASE (0xE0038000)
lharoon 0:22612ae617a0 785 #define LPC_CANAF_BASE (0xE003C000)
lharoon 0:22612ae617a0 786 #define LPC_CANCR_BASE (0xE0040000)
lharoon 0:22612ae617a0 787 #define LPC_CAN1_BASE (0xE0044000)
lharoon 0:22612ae617a0 788 #define LPC_CAN2_BASE (0xE0048000)
lharoon 0:22612ae617a0 789 #define LPC_I2C1_BASE (0xE005C000)
lharoon 0:22612ae617a0 790 #define LPC_SSP0_BASE (0xE0068000)
lharoon 0:22612ae617a0 791 #define LPC_DAC_BASE (0xE006C000)
lharoon 0:22612ae617a0 792 #define LPC_TIM2_BASE (0xE0070000)
lharoon 0:22612ae617a0 793 #define LPC_TIM3_BASE (0xE0074000)
lharoon 0:22612ae617a0 794 #define LPC_UART2_BASE (0xE0078000)
lharoon 0:22612ae617a0 795 #define LPC_UART3_BASE (0xE007C000)
lharoon 0:22612ae617a0 796 #define LPC_I2C2_BASE (0xE0080000)
lharoon 0:22612ae617a0 797 #define LPC_I2S_BASE (0xE0088000)
lharoon 0:22612ae617a0 798 #define LPC_MCI_BASE (0xE008C000)
lharoon 0:22612ae617a0 799 #define LPC_SC_BASE (0xE01FC000)
lharoon 0:22612ae617a0 800 #define LPC_EMAC_BASE (0xFFE00000)
lharoon 0:22612ae617a0 801 #define LPC_GPDMA_BASE (0xFFE04000)
lharoon 0:22612ae617a0 802 #define LPC_GPDMACH0_BASE (0xFFE04100)
lharoon 0:22612ae617a0 803 #define LPC_GPDMACH1_BASE (0xFFE04120)
lharoon 0:22612ae617a0 804 #define LPC_USB_BASE (0xFFE0C000)
lharoon 0:22612ae617a0 805 #define LPC_VIC_BASE (0xFFFFF000)
lharoon 0:22612ae617a0 806
lharoon 0:22612ae617a0 807 /* GPIOs */
lharoon 0:22612ae617a0 808 #define LPC_GPIO0_BASE (0x3FFFC000)
lharoon 0:22612ae617a0 809 #define LPC_GPIO1_BASE (0x3FFFC020)
lharoon 0:22612ae617a0 810 #define LPC_GPIO2_BASE (0x3FFFC040)
lharoon 0:22612ae617a0 811 #define LPC_GPIO3_BASE (0x3FFFC060)
lharoon 0:22612ae617a0 812 #define LPC_GPIO4_BASE (0x3FFFC080)
lharoon 0:22612ae617a0 813
lharoon 0:22612ae617a0 814
lharoon 0:22612ae617a0 815 /******************************************************************************/
lharoon 0:22612ae617a0 816 /* Peripheral declaration */
lharoon 0:22612ae617a0 817 /******************************************************************************/
lharoon 0:22612ae617a0 818 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
lharoon 0:22612ae617a0 819 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
lharoon 0:22612ae617a0 820 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
lharoon 0:22612ae617a0 821 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
lharoon 0:22612ae617a0 822 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
lharoon 0:22612ae617a0 823 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
lharoon 0:22612ae617a0 824 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
lharoon 0:22612ae617a0 825 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
lharoon 0:22612ae617a0 826 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
lharoon 0:22612ae617a0 827 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
lharoon 0:22612ae617a0 828 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
lharoon 0:22612ae617a0 829 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
lharoon 0:22612ae617a0 830 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
lharoon 0:22612ae617a0 831 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
lharoon 0:22612ae617a0 832 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
lharoon 0:22612ae617a0 833 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
lharoon 0:22612ae617a0 834 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
lharoon 0:22612ae617a0 835 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
lharoon 0:22612ae617a0 836 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
lharoon 0:22612ae617a0 837 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
lharoon 0:22612ae617a0 838 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
lharoon 0:22612ae617a0 839 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
lharoon 0:22612ae617a0 840 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
lharoon 0:22612ae617a0 841 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
lharoon 0:22612ae617a0 842 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
lharoon 0:22612ae617a0 843 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
lharoon 0:22612ae617a0 844 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
lharoon 0:22612ae617a0 845 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
lharoon 0:22612ae617a0 846 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
lharoon 0:22612ae617a0 847 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
lharoon 0:22612ae617a0 848 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
lharoon 0:22612ae617a0 849 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
lharoon 0:22612ae617a0 850 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
lharoon 0:22612ae617a0 851 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
lharoon 0:22612ae617a0 852 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
lharoon 0:22612ae617a0 853 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
lharoon 0:22612ae617a0 854 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
lharoon 0:22612ae617a0 855 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
lharoon 0:22612ae617a0 856 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
lharoon 0:22612ae617a0 857 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
lharoon 0:22612ae617a0 858
lharoon 0:22612ae617a0 859 #ifdef __cplusplus
lharoon 0:22612ae617a0 860 }
lharoon 0:22612ae617a0 861 #endif
lharoon 0:22612ae617a0 862
lharoon 0:22612ae617a0 863 #endif // __LPC23xx_H
lharoon 0:22612ae617a0 864