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LPC1768/core_cmInstr.h@46:890817bdcffb, 2012-11-26 (annotated)

Committer:
emimon01
Date:
Mon Nov 26 10:13:56 2012 +0000
Revision:
46:890817bdcffb
Parent:
40:976df7c37ad5 
Update CMSIS-CORE to v3.02

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 40:976df7c37ad5 1 /**************************************************************************//**
emilmont 40:976df7c37ad5 2 * @file core_cmInstr.h
emilmont 40:976df7c37ad5 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
emimon01 46:890817bdcffb 4 * @version V3.03
emimon01 46:890817bdcffb 5 * @date 29. August 2012
emilmont 40:976df7c37ad5 6 *
emilmont 40:976df7c37ad5 7 * @note
emimon01 46:890817bdcffb 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
emilmont 40:976df7c37ad5 9 *
emilmont 40:976df7c37ad5 10 * @par
emimon01 46:890817bdcffb 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
emimon01 46:890817bdcffb 12 * processor based microcontrollers. This file can be freely distributed
emimon01 46:890817bdcffb 13 * within development tools that are supporting such ARM based processors.
emilmont 40:976df7c37ad5 14 *
emilmont 40:976df7c37ad5 15 * @par
emilmont 40:976df7c37ad5 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
emilmont 40:976df7c37ad5 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
emilmont 40:976df7c37ad5 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
emilmont 40:976df7c37ad5 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
emilmont 40:976df7c37ad5 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
emilmont 40:976df7c37ad5 21 *
emilmont 40:976df7c37ad5 22 ******************************************************************************/
emilmont 40:976df7c37ad5 23
emilmont 40:976df7c37ad5 24 #ifndef __CORE_CMINSTR_H
emilmont 40:976df7c37ad5 25 #define __CORE_CMINSTR_H
emilmont 40:976df7c37ad5 26
emilmont 40:976df7c37ad5 27
emilmont 40:976df7c37ad5 28 /* ########################## Core Instruction Access ######################### */
emilmont 40:976df7c37ad5 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
emilmont 40:976df7c37ad5 30 Access to dedicated instructions
emilmont 40:976df7c37ad5 31 @{
emilmont 40:976df7c37ad5 32 */
emilmont 40:976df7c37ad5 33
emilmont 40:976df7c37ad5 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 40:976df7c37ad5 35 /* ARM armcc specific functions */
emilmont 40:976df7c37ad5 36
emilmont 40:976df7c37ad5 37 #if (__ARMCC_VERSION < 400677)
emilmont 40:976df7c37ad5 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 40:976df7c37ad5 39 #endif
emilmont 40:976df7c37ad5 40
emilmont 40:976df7c37ad5 41
emilmont 40:976df7c37ad5 42 /** \brief No Operation
emilmont 40:976df7c37ad5 43
emilmont 40:976df7c37ad5 44 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 40:976df7c37ad5 45 */
emilmont 40:976df7c37ad5 46 #define __NOP __nop
emilmont 40:976df7c37ad5 47
emilmont 40:976df7c37ad5 48
emilmont 40:976df7c37ad5 49 /** \brief Wait For Interrupt
emilmont 40:976df7c37ad5 50
emilmont 40:976df7c37ad5 51 Wait For Interrupt is a hint instruction that suspends execution
emilmont 40:976df7c37ad5 52 until one of a number of events occurs.
emilmont 40:976df7c37ad5 53 */
emilmont 40:976df7c37ad5 54 #define __WFI __wfi
emilmont 40:976df7c37ad5 55
emilmont 40:976df7c37ad5 56
emilmont 40:976df7c37ad5 57 /** \brief Wait For Event
emilmont 40:976df7c37ad5 58
emilmont 40:976df7c37ad5 59 Wait For Event is a hint instruction that permits the processor to enter
emilmont 40:976df7c37ad5 60 a low-power state until one of a number of events occurs.
emilmont 40:976df7c37ad5 61 */
emilmont 40:976df7c37ad5 62 #define __WFE __wfe
emilmont 40:976df7c37ad5 63
emilmont 40:976df7c37ad5 64
emilmont 40:976df7c37ad5 65 /** \brief Send Event
emilmont 40:976df7c37ad5 66
emilmont 40:976df7c37ad5 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 40:976df7c37ad5 68 */
emilmont 40:976df7c37ad5 69 #define __SEV __sev
emilmont 40:976df7c37ad5 70
emilmont 40:976df7c37ad5 71
emilmont 40:976df7c37ad5 72 /** \brief Instruction Synchronization Barrier
emilmont 40:976df7c37ad5 73
emimon01 46:890817bdcffb 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
emimon01 46:890817bdcffb 75 so that all instructions following the ISB are fetched from cache or
emilmont 40:976df7c37ad5 76 memory, after the instruction has been completed.
emilmont 40:976df7c37ad5 77 */
emilmont 40:976df7c37ad5 78 #define __ISB() __isb(0xF)
emilmont 40:976df7c37ad5 79
emilmont 40:976df7c37ad5 80
emilmont 40:976df7c37ad5 81 /** \brief Data Synchronization Barrier
emilmont 40:976df7c37ad5 82
emimon01 46:890817bdcffb 83 This function acts as a special kind of Data Memory Barrier.
emilmont 40:976df7c37ad5 84 It completes when all explicit memory accesses before this instruction complete.
emilmont 40:976df7c37ad5 85 */
emilmont 40:976df7c37ad5 86 #define __DSB() __dsb(0xF)
emilmont 40:976df7c37ad5 87
emilmont 40:976df7c37ad5 88
emilmont 40:976df7c37ad5 89 /** \brief Data Memory Barrier
emilmont 40:976df7c37ad5 90
emimon01 46:890817bdcffb 91 This function ensures the apparent order of the explicit memory operations before
emilmont 40:976df7c37ad5 92 and after the instruction, without ensuring their completion.
emilmont 40:976df7c37ad5 93 */
emilmont 40:976df7c37ad5 94 #define __DMB() __dmb(0xF)
emilmont 40:976df7c37ad5 95
emilmont 40:976df7c37ad5 96
emilmont 40:976df7c37ad5 97 /** \brief Reverse byte order (32 bit)
emilmont 40:976df7c37ad5 98
emilmont 40:976df7c37ad5 99 This function reverses the byte order in integer value.
emilmont 40:976df7c37ad5 100
emilmont 40:976df7c37ad5 101 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 102 \return Reversed value
emilmont 40:976df7c37ad5 103 */
emilmont 40:976df7c37ad5 104 #define __REV __rev
emilmont 40:976df7c37ad5 105
emilmont 40:976df7c37ad5 106
emilmont 40:976df7c37ad5 107 /** \brief Reverse byte order (16 bit)
emilmont 40:976df7c37ad5 108
emilmont 40:976df7c37ad5 109 This function reverses the byte order in two unsigned short values.
emilmont 40:976df7c37ad5 110
emilmont 40:976df7c37ad5 111 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 112 \return Reversed value
emilmont 40:976df7c37ad5 113 */
emimon01 46:890817bdcffb 114 #ifndef __NO_EMBEDDED_ASM
emimon01 46:890817bdcffb 115 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
emilmont 40:976df7c37ad5 116 {
emilmont 40:976df7c37ad5 117 rev16 r0, r0
emilmont 40:976df7c37ad5 118 bx lr
emilmont 40:976df7c37ad5 119 }
emimon01 46:890817bdcffb 120 #endif
emilmont 40:976df7c37ad5 121
emilmont 40:976df7c37ad5 122 /** \brief Reverse byte order in signed short value
emilmont 40:976df7c37ad5 123
emilmont 40:976df7c37ad5 124 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 40:976df7c37ad5 125
emilmont 40:976df7c37ad5 126 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 127 \return Reversed value
emilmont 40:976df7c37ad5 128 */
emimon01 46:890817bdcffb 129 #ifndef __NO_EMBEDDED_ASM
emimon01 46:890817bdcffb 130 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
emilmont 40:976df7c37ad5 131 {
emilmont 40:976df7c37ad5 132 revsh r0, r0
emilmont 40:976df7c37ad5 133 bx lr
emilmont 40:976df7c37ad5 134 }
emimon01 46:890817bdcffb 135 #endif
emimon01 46:890817bdcffb 136
emimon01 46:890817bdcffb 137
emimon01 46:890817bdcffb 138 /** \brief Rotate Right in unsigned value (32 bit)
emimon01 46:890817bdcffb 139
emimon01 46:890817bdcffb 140 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emimon01 46:890817bdcffb 141
emimon01 46:890817bdcffb 142 \param [in] value Value to rotate
emimon01 46:890817bdcffb 143 \param [in] value Number of Bits to rotate
emimon01 46:890817bdcffb 144 \return Rotated value
emimon01 46:890817bdcffb 145 */
emimon01 46:890817bdcffb 146 #define __ROR __ror
emimon01 46:890817bdcffb 147
emimon01 46:890817bdcffb 148
emimon01 46:890817bdcffb 149 /** \brief Breakpoint
emimon01 46:890817bdcffb 150
emimon01 46:890817bdcffb 151 This function causes the processor to enter Debug state.
emimon01 46:890817bdcffb 152 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emimon01 46:890817bdcffb 153
emimon01 46:890817bdcffb 154 \param [in] value is ignored by the processor.
emimon01 46:890817bdcffb 155 If required, a debugger can use it to store additional information about the breakpoint.
emimon01 46:890817bdcffb 156 */
emimon01 46:890817bdcffb 157 #define __BKPT(value) __breakpoint(value)
emilmont 40:976df7c37ad5 158
emilmont 40:976df7c37ad5 159
emilmont 40:976df7c37ad5 160 #if (__CORTEX_M >= 0x03)
emilmont 40:976df7c37ad5 161
emilmont 40:976df7c37ad5 162 /** \brief Reverse bit order of value
emilmont 40:976df7c37ad5 163
emilmont 40:976df7c37ad5 164 This function reverses the bit order of the given value.
emilmont 40:976df7c37ad5 165
emilmont 40:976df7c37ad5 166 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 167 \return Reversed value
emilmont 40:976df7c37ad5 168 */
emilmont 40:976df7c37ad5 169 #define __RBIT __rbit
emilmont 40:976df7c37ad5 170
emilmont 40:976df7c37ad5 171
emilmont 40:976df7c37ad5 172 /** \brief LDR Exclusive (8 bit)
emilmont 40:976df7c37ad5 173
emilmont 40:976df7c37ad5 174 This function performs a exclusive LDR command for 8 bit value.
emilmont 40:976df7c37ad5 175
emilmont 40:976df7c37ad5 176 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 177 \return value of type uint8_t at (*ptr)
emilmont 40:976df7c37ad5 178 */
emilmont 40:976df7c37ad5 179 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
emilmont 40:976df7c37ad5 180
emilmont 40:976df7c37ad5 181
emilmont 40:976df7c37ad5 182 /** \brief LDR Exclusive (16 bit)
emilmont 40:976df7c37ad5 183
emilmont 40:976df7c37ad5 184 This function performs a exclusive LDR command for 16 bit values.
emilmont 40:976df7c37ad5 185
emilmont 40:976df7c37ad5 186 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 187 \return value of type uint16_t at (*ptr)
emilmont 40:976df7c37ad5 188 */
emilmont 40:976df7c37ad5 189 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
emilmont 40:976df7c37ad5 190
emilmont 40:976df7c37ad5 191
emilmont 40:976df7c37ad5 192 /** \brief LDR Exclusive (32 bit)
emilmont 40:976df7c37ad5 193
emilmont 40:976df7c37ad5 194 This function performs a exclusive LDR command for 32 bit values.
emilmont 40:976df7c37ad5 195
emilmont 40:976df7c37ad5 196 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 197 \return value of type uint32_t at (*ptr)
emilmont 40:976df7c37ad5 198 */
emilmont 40:976df7c37ad5 199 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
emilmont 40:976df7c37ad5 200
emilmont 40:976df7c37ad5 201
emilmont 40:976df7c37ad5 202 /** \brief STR Exclusive (8 bit)
emilmont 40:976df7c37ad5 203
emilmont 40:976df7c37ad5 204 This function performs a exclusive STR command for 8 bit values.
emilmont 40:976df7c37ad5 205
emilmont 40:976df7c37ad5 206 \param [in] value Value to store
emilmont 40:976df7c37ad5 207 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 208 \return 0 Function succeeded
emilmont 40:976df7c37ad5 209 \return 1 Function failed
emilmont 40:976df7c37ad5 210 */
emilmont 40:976df7c37ad5 211 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 40:976df7c37ad5 212
emilmont 40:976df7c37ad5 213
emilmont 40:976df7c37ad5 214 /** \brief STR Exclusive (16 bit)
emilmont 40:976df7c37ad5 215
emilmont 40:976df7c37ad5 216 This function performs a exclusive STR command for 16 bit values.
emilmont 40:976df7c37ad5 217
emilmont 40:976df7c37ad5 218 \param [in] value Value to store
emilmont 40:976df7c37ad5 219 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 220 \return 0 Function succeeded
emilmont 40:976df7c37ad5 221 \return 1 Function failed
emilmont 40:976df7c37ad5 222 */
emilmont 40:976df7c37ad5 223 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 40:976df7c37ad5 224
emilmont 40:976df7c37ad5 225
emilmont 40:976df7c37ad5 226 /** \brief STR Exclusive (32 bit)
emilmont 40:976df7c37ad5 227
emilmont 40:976df7c37ad5 228 This function performs a exclusive STR command for 32 bit values.
emilmont 40:976df7c37ad5 229
emilmont 40:976df7c37ad5 230 \param [in] value Value to store
emilmont 40:976df7c37ad5 231 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 232 \return 0 Function succeeded
emilmont 40:976df7c37ad5 233 \return 1 Function failed
emilmont 40:976df7c37ad5 234 */
emilmont 40:976df7c37ad5 235 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 40:976df7c37ad5 236
emilmont 40:976df7c37ad5 237
emilmont 40:976df7c37ad5 238 /** \brief Remove the exclusive lock
emilmont 40:976df7c37ad5 239
emilmont 40:976df7c37ad5 240 This function removes the exclusive lock which is created by LDREX.
emilmont 40:976df7c37ad5 241
emilmont 40:976df7c37ad5 242 */
emilmont 40:976df7c37ad5 243 #define __CLREX __clrex
emilmont 40:976df7c37ad5 244
emilmont 40:976df7c37ad5 245
emilmont 40:976df7c37ad5 246 /** \brief Signed Saturate
emilmont 40:976df7c37ad5 247
emilmont 40:976df7c37ad5 248 This function saturates a signed value.
emilmont 40:976df7c37ad5 249
emilmont 40:976df7c37ad5 250 \param [in] value Value to be saturated
emilmont 40:976df7c37ad5 251 \param [in] sat Bit position to saturate to (1..32)
emilmont 40:976df7c37ad5 252 \return Saturated value
emilmont 40:976df7c37ad5 253 */
emilmont 40:976df7c37ad5 254 #define __SSAT __ssat
emilmont 40:976df7c37ad5 255
emilmont 40:976df7c37ad5 256
emilmont 40:976df7c37ad5 257 /** \brief Unsigned Saturate
emilmont 40:976df7c37ad5 258
emilmont 40:976df7c37ad5 259 This function saturates an unsigned value.
emilmont 40:976df7c37ad5 260
emilmont 40:976df7c37ad5 261 \param [in] value Value to be saturated
emilmont 40:976df7c37ad5 262 \param [in] sat Bit position to saturate to (0..31)
emilmont 40:976df7c37ad5 263 \return Saturated value
emilmont 40:976df7c37ad5 264 */
emilmont 40:976df7c37ad5 265 #define __USAT __usat
emilmont 40:976df7c37ad5 266
emilmont 40:976df7c37ad5 267
emilmont 40:976df7c37ad5 268 /** \brief Count leading zeros
emilmont 40:976df7c37ad5 269
emilmont 40:976df7c37ad5 270 This function counts the number of leading zeros of a data value.
emilmont 40:976df7c37ad5 271
emilmont 40:976df7c37ad5 272 \param [in] value Value to count the leading zeros
emilmont 40:976df7c37ad5 273 \return number of leading zeros in value
emilmont 40:976df7c37ad5 274 */
emimon01 46:890817bdcffb 275 #define __CLZ __clz
emilmont 40:976df7c37ad5 276
emilmont 40:976df7c37ad5 277 #endif /* (__CORTEX_M >= 0x03) */
emilmont 40:976df7c37ad5 278
emilmont 40:976df7c37ad5 279
emilmont 40:976df7c37ad5 280
emilmont 40:976df7c37ad5 281 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
emilmont 40:976df7c37ad5 282 /* IAR iccarm specific functions */
emilmont 40:976df7c37ad5 283
emilmont 40:976df7c37ad5 284 #include <cmsis_iar.h>
emilmont 40:976df7c37ad5 285
emilmont 40:976df7c37ad5 286
emimon01 46:890817bdcffb 287 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
emimon01 46:890817bdcffb 288 /* TI CCS specific functions */
emimon01 46:890817bdcffb 289
emimon01 46:890817bdcffb 290 #include <cmsis_ccs.h>
emimon01 46:890817bdcffb 291
emimon01 46:890817bdcffb 292
emilmont 40:976df7c37ad5 293 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 40:976df7c37ad5 294 /* GNU gcc specific functions */
emilmont 40:976df7c37ad5 295
emilmont 40:976df7c37ad5 296 /** \brief No Operation
emilmont 40:976df7c37ad5 297
emilmont 40:976df7c37ad5 298 No Operation does nothing. This instruction can be used for code alignment purposes.
emilmont 40:976df7c37ad5 299 */
emimon01 46:890817bdcffb 300 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
emilmont 40:976df7c37ad5 301 {
emilmont 40:976df7c37ad5 302 __ASM volatile ("nop");
emilmont 40:976df7c37ad5 303 }
emilmont 40:976df7c37ad5 304
emilmont 40:976df7c37ad5 305
emilmont 40:976df7c37ad5 306 /** \brief Wait For Interrupt
emilmont 40:976df7c37ad5 307
emilmont 40:976df7c37ad5 308 Wait For Interrupt is a hint instruction that suspends execution
emilmont 40:976df7c37ad5 309 until one of a number of events occurs.
emilmont 40:976df7c37ad5 310 */
emimon01 46:890817bdcffb 311 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
emilmont 40:976df7c37ad5 312 {
emilmont 40:976df7c37ad5 313 __ASM volatile ("wfi");
emilmont 40:976df7c37ad5 314 }
emilmont 40:976df7c37ad5 315
emilmont 40:976df7c37ad5 316
emilmont 40:976df7c37ad5 317 /** \brief Wait For Event
emilmont 40:976df7c37ad5 318
emilmont 40:976df7c37ad5 319 Wait For Event is a hint instruction that permits the processor to enter
emilmont 40:976df7c37ad5 320 a low-power state until one of a number of events occurs.
emilmont 40:976df7c37ad5 321 */
emimon01 46:890817bdcffb 322 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
emilmont 40:976df7c37ad5 323 {
emilmont 40:976df7c37ad5 324 __ASM volatile ("wfe");
emilmont 40:976df7c37ad5 325 }
emilmont 40:976df7c37ad5 326
emilmont 40:976df7c37ad5 327
emilmont 40:976df7c37ad5 328 /** \brief Send Event
emilmont 40:976df7c37ad5 329
emilmont 40:976df7c37ad5 330 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
emilmont 40:976df7c37ad5 331 */
emimon01 46:890817bdcffb 332 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
emilmont 40:976df7c37ad5 333 {
emilmont 40:976df7c37ad5 334 __ASM volatile ("sev");
emilmont 40:976df7c37ad5 335 }
emilmont 40:976df7c37ad5 336
emilmont 40:976df7c37ad5 337
emilmont 40:976df7c37ad5 338 /** \brief Instruction Synchronization Barrier
emilmont 40:976df7c37ad5 339
emimon01 46:890817bdcffb 340 Instruction Synchronization Barrier flushes the pipeline in the processor,
emimon01 46:890817bdcffb 341 so that all instructions following the ISB are fetched from cache or
emilmont 40:976df7c37ad5 342 memory, after the instruction has been completed.
emilmont 40:976df7c37ad5 343 */
emimon01 46:890817bdcffb 344 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
emilmont 40:976df7c37ad5 345 {
emilmont 40:976df7c37ad5 346 __ASM volatile ("isb");
emilmont 40:976df7c37ad5 347 }
emilmont 40:976df7c37ad5 348
emilmont 40:976df7c37ad5 349
emilmont 40:976df7c37ad5 350 /** \brief Data Synchronization Barrier
emilmont 40:976df7c37ad5 351
emimon01 46:890817bdcffb 352 This function acts as a special kind of Data Memory Barrier.
emilmont 40:976df7c37ad5 353 It completes when all explicit memory accesses before this instruction complete.
emilmont 40:976df7c37ad5 354 */
emimon01 46:890817bdcffb 355 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
emilmont 40:976df7c37ad5 356 {
emilmont 40:976df7c37ad5 357 __ASM volatile ("dsb");
emilmont 40:976df7c37ad5 358 }
emilmont 40:976df7c37ad5 359
emilmont 40:976df7c37ad5 360
emilmont 40:976df7c37ad5 361 /** \brief Data Memory Barrier
emilmont 40:976df7c37ad5 362
emimon01 46:890817bdcffb 363 This function ensures the apparent order of the explicit memory operations before
emilmont 40:976df7c37ad5 364 and after the instruction, without ensuring their completion.
emilmont 40:976df7c37ad5 365 */
emimon01 46:890817bdcffb 366 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
emilmont 40:976df7c37ad5 367 {
emilmont 40:976df7c37ad5 368 __ASM volatile ("dmb");
emilmont 40:976df7c37ad5 369 }
emilmont 40:976df7c37ad5 370
emilmont 40:976df7c37ad5 371
emilmont 40:976df7c37ad5 372 /** \brief Reverse byte order (32 bit)
emilmont 40:976df7c37ad5 373
emilmont 40:976df7c37ad5 374 This function reverses the byte order in integer value.
emilmont 40:976df7c37ad5 375
emilmont 40:976df7c37ad5 376 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 377 \return Reversed value
emilmont 40:976df7c37ad5 378 */
emimon01 46:890817bdcffb 379 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
emilmont 40:976df7c37ad5 380 {
emilmont 40:976df7c37ad5 381 uint32_t result;
emimon01 46:890817bdcffb 382
emilmont 40:976df7c37ad5 383 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 384 return(result);
emilmont 40:976df7c37ad5 385 }
emilmont 40:976df7c37ad5 386
emilmont 40:976df7c37ad5 387
emilmont 40:976df7c37ad5 388 /** \brief Reverse byte order (16 bit)
emilmont 40:976df7c37ad5 389
emilmont 40:976df7c37ad5 390 This function reverses the byte order in two unsigned short values.
emilmont 40:976df7c37ad5 391
emilmont 40:976df7c37ad5 392 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 393 \return Reversed value
emilmont 40:976df7c37ad5 394 */
emimon01 46:890817bdcffb 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
emilmont 40:976df7c37ad5 396 {
emilmont 40:976df7c37ad5 397 uint32_t result;
emimon01 46:890817bdcffb 398
emilmont 40:976df7c37ad5 399 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 400 return(result);
emilmont 40:976df7c37ad5 401 }
emilmont 40:976df7c37ad5 402
emilmont 40:976df7c37ad5 403
emilmont 40:976df7c37ad5 404 /** \brief Reverse byte order in signed short value
emilmont 40:976df7c37ad5 405
emilmont 40:976df7c37ad5 406 This function reverses the byte order in a signed short value with sign extension to integer.
emilmont 40:976df7c37ad5 407
emilmont 40:976df7c37ad5 408 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 409 \return Reversed value
emilmont 40:976df7c37ad5 410 */
emimon01 46:890817bdcffb 411 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
emilmont 40:976df7c37ad5 412 {
emilmont 40:976df7c37ad5 413 uint32_t result;
emimon01 46:890817bdcffb 414
emilmont 40:976df7c37ad5 415 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 416 return(result);
emilmont 40:976df7c37ad5 417 }
emilmont 40:976df7c37ad5 418
emilmont 40:976df7c37ad5 419
emimon01 46:890817bdcffb 420 /** \brief Rotate Right in unsigned value (32 bit)
emimon01 46:890817bdcffb 421
emimon01 46:890817bdcffb 422 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
emimon01 46:890817bdcffb 423
emimon01 46:890817bdcffb 424 \param [in] value Value to rotate
emimon01 46:890817bdcffb 425 \param [in] value Number of Bits to rotate
emimon01 46:890817bdcffb 426 \return Rotated value
emimon01 46:890817bdcffb 427 */
emimon01 46:890817bdcffb 428 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
emimon01 46:890817bdcffb 429 {
emimon01 46:890817bdcffb 430
emimon01 46:890817bdcffb 431 __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
emimon01 46:890817bdcffb 432 return(op1);
emimon01 46:890817bdcffb 433 }
emimon01 46:890817bdcffb 434
emimon01 46:890817bdcffb 435
emimon01 46:890817bdcffb 436 /** \brief Breakpoint
emimon01 46:890817bdcffb 437
emimon01 46:890817bdcffb 438 This function causes the processor to enter Debug state.
emimon01 46:890817bdcffb 439 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
emimon01 46:890817bdcffb 440
emimon01 46:890817bdcffb 441 \param [in] value is ignored by the processor.
emimon01 46:890817bdcffb 442 If required, a debugger can use it to store additional information about the breakpoint.
emimon01 46:890817bdcffb 443 */
emimon01 46:890817bdcffb 444 #define __BKPT(value) __ASM volatile ("bkpt "#value)
emimon01 46:890817bdcffb 445
emimon01 46:890817bdcffb 446
emilmont 40:976df7c37ad5 447 #if (__CORTEX_M >= 0x03)
emilmont 40:976df7c37ad5 448
emilmont 40:976df7c37ad5 449 /** \brief Reverse bit order of value
emilmont 40:976df7c37ad5 450
emilmont 40:976df7c37ad5 451 This function reverses the bit order of the given value.
emilmont 40:976df7c37ad5 452
emilmont 40:976df7c37ad5 453 \param [in] value Value to reverse
emilmont 40:976df7c37ad5 454 \return Reversed value
emilmont 40:976df7c37ad5 455 */
emimon01 46:890817bdcffb 456 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
emilmont 40:976df7c37ad5 457 {
emilmont 40:976df7c37ad5 458 uint32_t result;
emimon01 46:890817bdcffb 459
emilmont 40:976df7c37ad5 460 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 461 return(result);
emilmont 40:976df7c37ad5 462 }
emilmont 40:976df7c37ad5 463
emilmont 40:976df7c37ad5 464
emilmont 40:976df7c37ad5 465 /** \brief LDR Exclusive (8 bit)
emilmont 40:976df7c37ad5 466
emilmont 40:976df7c37ad5 467 This function performs a exclusive LDR command for 8 bit value.
emilmont 40:976df7c37ad5 468
emilmont 40:976df7c37ad5 469 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 470 \return value of type uint8_t at (*ptr)
emilmont 40:976df7c37ad5 471 */
emimon01 46:890817bdcffb 472 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
emilmont 40:976df7c37ad5 473 {
emilmont 40:976df7c37ad5 474 uint8_t result;
emimon01 46:890817bdcffb 475
emilmont 40:976df7c37ad5 476 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 40:976df7c37ad5 477 return(result);
emilmont 40:976df7c37ad5 478 }
emilmont 40:976df7c37ad5 479
emilmont 40:976df7c37ad5 480
emilmont 40:976df7c37ad5 481 /** \brief LDR Exclusive (16 bit)
emilmont 40:976df7c37ad5 482
emilmont 40:976df7c37ad5 483 This function performs a exclusive LDR command for 16 bit values.
emilmont 40:976df7c37ad5 484
emilmont 40:976df7c37ad5 485 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 486 \return value of type uint16_t at (*ptr)
emilmont 40:976df7c37ad5 487 */
emimon01 46:890817bdcffb 488 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
emilmont 40:976df7c37ad5 489 {
emilmont 40:976df7c37ad5 490 uint16_t result;
emimon01 46:890817bdcffb 491
emilmont 40:976df7c37ad5 492 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 40:976df7c37ad5 493 return(result);
emilmont 40:976df7c37ad5 494 }
emilmont 40:976df7c37ad5 495
emilmont 40:976df7c37ad5 496
emilmont 40:976df7c37ad5 497 /** \brief LDR Exclusive (32 bit)
emilmont 40:976df7c37ad5 498
emilmont 40:976df7c37ad5 499 This function performs a exclusive LDR command for 32 bit values.
emilmont 40:976df7c37ad5 500
emilmont 40:976df7c37ad5 501 \param [in] ptr Pointer to data
emilmont 40:976df7c37ad5 502 \return value of type uint32_t at (*ptr)
emilmont 40:976df7c37ad5 503 */
emimon01 46:890817bdcffb 504 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
emilmont 40:976df7c37ad5 505 {
emilmont 40:976df7c37ad5 506 uint32_t result;
emimon01 46:890817bdcffb 507
emilmont 40:976df7c37ad5 508 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
emilmont 40:976df7c37ad5 509 return(result);
emilmont 40:976df7c37ad5 510 }
emilmont 40:976df7c37ad5 511
emilmont 40:976df7c37ad5 512
emilmont 40:976df7c37ad5 513 /** \brief STR Exclusive (8 bit)
emilmont 40:976df7c37ad5 514
emilmont 40:976df7c37ad5 515 This function performs a exclusive STR command for 8 bit values.
emilmont 40:976df7c37ad5 516
emilmont 40:976df7c37ad5 517 \param [in] value Value to store
emilmont 40:976df7c37ad5 518 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 519 \return 0 Function succeeded
emilmont 40:976df7c37ad5 520 \return 1 Function failed
emilmont 40:976df7c37ad5 521 */
emimon01 46:890817bdcffb 522 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
emilmont 40:976df7c37ad5 523 {
emilmont 40:976df7c37ad5 524 uint32_t result;
emimon01 46:890817bdcffb 525
emilmont 40:976df7c37ad5 526 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 40:976df7c37ad5 527 return(result);
emilmont 40:976df7c37ad5 528 }
emilmont 40:976df7c37ad5 529
emilmont 40:976df7c37ad5 530
emilmont 40:976df7c37ad5 531 /** \brief STR Exclusive (16 bit)
emilmont 40:976df7c37ad5 532
emilmont 40:976df7c37ad5 533 This function performs a exclusive STR command for 16 bit values.
emilmont 40:976df7c37ad5 534
emilmont 40:976df7c37ad5 535 \param [in] value Value to store
emilmont 40:976df7c37ad5 536 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 537 \return 0 Function succeeded
emilmont 40:976df7c37ad5 538 \return 1 Function failed
emilmont 40:976df7c37ad5 539 */
emimon01 46:890817bdcffb 540 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
emilmont 40:976df7c37ad5 541 {
emilmont 40:976df7c37ad5 542 uint32_t result;
emimon01 46:890817bdcffb 543
emilmont 40:976df7c37ad5 544 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 40:976df7c37ad5 545 return(result);
emilmont 40:976df7c37ad5 546 }
emilmont 40:976df7c37ad5 547
emilmont 40:976df7c37ad5 548
emilmont 40:976df7c37ad5 549 /** \brief STR Exclusive (32 bit)
emilmont 40:976df7c37ad5 550
emilmont 40:976df7c37ad5 551 This function performs a exclusive STR command for 32 bit values.
emilmont 40:976df7c37ad5 552
emilmont 40:976df7c37ad5 553 \param [in] value Value to store
emilmont 40:976df7c37ad5 554 \param [in] ptr Pointer to location
emilmont 40:976df7c37ad5 555 \return 0 Function succeeded
emilmont 40:976df7c37ad5 556 \return 1 Function failed
emilmont 40:976df7c37ad5 557 */
emimon01 46:890817bdcffb 558 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
emilmont 40:976df7c37ad5 559 {
emilmont 40:976df7c37ad5 560 uint32_t result;
emimon01 46:890817bdcffb 561
emilmont 40:976df7c37ad5 562 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
emilmont 40:976df7c37ad5 563 return(result);
emilmont 40:976df7c37ad5 564 }
emilmont 40:976df7c37ad5 565
emilmont 40:976df7c37ad5 566
emilmont 40:976df7c37ad5 567 /** \brief Remove the exclusive lock
emilmont 40:976df7c37ad5 568
emilmont 40:976df7c37ad5 569 This function removes the exclusive lock which is created by LDREX.
emilmont 40:976df7c37ad5 570
emilmont 40:976df7c37ad5 571 */
emimon01 46:890817bdcffb 572 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
emilmont 40:976df7c37ad5 573 {
emilmont 40:976df7c37ad5 574 __ASM volatile ("clrex");
emilmont 40:976df7c37ad5 575 }
emilmont 40:976df7c37ad5 576
emilmont 40:976df7c37ad5 577
emilmont 40:976df7c37ad5 578 /** \brief Signed Saturate
emilmont 40:976df7c37ad5 579
emilmont 40:976df7c37ad5 580 This function saturates a signed value.
emilmont 40:976df7c37ad5 581
emilmont 40:976df7c37ad5 582 \param [in] value Value to be saturated
emilmont 40:976df7c37ad5 583 \param [in] sat Bit position to saturate to (1..32)
emilmont 40:976df7c37ad5 584 \return Saturated value
emilmont 40:976df7c37ad5 585 */
emilmont 40:976df7c37ad5 586 #define __SSAT(ARG1,ARG2) \
emilmont 40:976df7c37ad5 587 ({ \
emilmont 40:976df7c37ad5 588 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 40:976df7c37ad5 589 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 40:976df7c37ad5 590 __RES; \
emilmont 40:976df7c37ad5 591 })
emilmont 40:976df7c37ad5 592
emilmont 40:976df7c37ad5 593
emilmont 40:976df7c37ad5 594 /** \brief Unsigned Saturate
emilmont 40:976df7c37ad5 595
emilmont 40:976df7c37ad5 596 This function saturates an unsigned value.
emilmont 40:976df7c37ad5 597
emilmont 40:976df7c37ad5 598 \param [in] value Value to be saturated
emilmont 40:976df7c37ad5 599 \param [in] sat Bit position to saturate to (0..31)
emilmont 40:976df7c37ad5 600 \return Saturated value
emilmont 40:976df7c37ad5 601 */
emilmont 40:976df7c37ad5 602 #define __USAT(ARG1,ARG2) \
emilmont 40:976df7c37ad5 603 ({ \
emilmont 40:976df7c37ad5 604 uint32_t __RES, __ARG1 = (ARG1); \
emilmont 40:976df7c37ad5 605 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
emilmont 40:976df7c37ad5 606 __RES; \
emilmont 40:976df7c37ad5 607 })
emilmont 40:976df7c37ad5 608
emilmont 40:976df7c37ad5 609
emilmont 40:976df7c37ad5 610 /** \brief Count leading zeros
emilmont 40:976df7c37ad5 611
emilmont 40:976df7c37ad5 612 This function counts the number of leading zeros of a data value.
emilmont 40:976df7c37ad5 613
emilmont 40:976df7c37ad5 614 \param [in] value Value to count the leading zeros
emilmont 40:976df7c37ad5 615 \return number of leading zeros in value
emilmont 40:976df7c37ad5 616 */
emimon01 46:890817bdcffb 617 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
emilmont 40:976df7c37ad5 618 {
emilmont 40:976df7c37ad5 619 uint8_t result;
emimon01 46:890817bdcffb 620
emilmont 40:976df7c37ad5 621 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
emilmont 40:976df7c37ad5 622 return(result);
emilmont 40:976df7c37ad5 623 }
emilmont 40:976df7c37ad5 624
emilmont 40:976df7c37ad5 625 #endif /* (__CORTEX_M >= 0x03) */
emilmont 40:976df7c37ad5 626
emilmont 40:976df7c37ad5 627
emilmont 40:976df7c37ad5 628
emilmont 40:976df7c37ad5 629
emilmont 40:976df7c37ad5 630 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 40:976df7c37ad5 631 /* TASKING carm specific functions */
emilmont 40:976df7c37ad5 632
emilmont 40:976df7c37ad5 633 /*
emilmont 40:976df7c37ad5 634 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 40:976df7c37ad5 635 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 40:976df7c37ad5 636 * Including the CMSIS ones.
emilmont 40:976df7c37ad5 637 */
emilmont 40:976df7c37ad5 638
emilmont 40:976df7c37ad5 639 #endif
emilmont 40:976df7c37ad5 640
emilmont 40:976df7c37ad5 641 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
emilmont 40:976df7c37ad5 642
emilmont 40:976df7c37ad5 643 #endif /* __CORE_CMINSTR_H */