The official mbed C/C SDK provides the software platform and libraries to build your applications.
Fork of mbed by
LPC812/core_cmFunc.h@62:7e6c9f46b3bd, 2013-04-17 (annotated)
- Committer:
- emilmont
- Date:
- Wed Apr 17 15:30:58 2013 +0100
- Revision:
- 62:7e6c9f46b3bd
Add NXP LPC812
[KL25Z] Use channel 0 as a prescaler for channel 1
[CodeSourcery] Fix standard library retargeting removing duplicate "_isatty"
Move parse_pins in RPC module
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 62:7e6c9f46b3bd | 1 | /**************************************************************************//** |
emilmont | 62:7e6c9f46b3bd | 2 | * @file core_cmFunc.h |
emilmont | 62:7e6c9f46b3bd | 3 | * @brief CMSIS Cortex-M Core Function Access Header File |
emilmont | 62:7e6c9f46b3bd | 4 | * @version V3.02 |
emilmont | 62:7e6c9f46b3bd | 5 | * @date 24. May 2012 |
emilmont | 62:7e6c9f46b3bd | 6 | * |
emilmont | 62:7e6c9f46b3bd | 7 | * @note |
emilmont | 62:7e6c9f46b3bd | 8 | * Copyright (C) 2009-2012 ARM Limited. All rights reserved. |
emilmont | 62:7e6c9f46b3bd | 9 | * |
emilmont | 62:7e6c9f46b3bd | 10 | * @par |
emilmont | 62:7e6c9f46b3bd | 11 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
emilmont | 62:7e6c9f46b3bd | 12 | * processor based microcontrollers. This file can be freely distributed |
emilmont | 62:7e6c9f46b3bd | 13 | * within development tools that are supporting such ARM based processors. |
emilmont | 62:7e6c9f46b3bd | 14 | * |
emilmont | 62:7e6c9f46b3bd | 15 | * @par |
emilmont | 62:7e6c9f46b3bd | 16 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
emilmont | 62:7e6c9f46b3bd | 17 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
emilmont | 62:7e6c9f46b3bd | 18 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
emilmont | 62:7e6c9f46b3bd | 19 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
emilmont | 62:7e6c9f46b3bd | 20 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
emilmont | 62:7e6c9f46b3bd | 21 | * |
emilmont | 62:7e6c9f46b3bd | 22 | ******************************************************************************/ |
emilmont | 62:7e6c9f46b3bd | 23 | |
emilmont | 62:7e6c9f46b3bd | 24 | #ifndef __CORE_CMFUNC_H |
emilmont | 62:7e6c9f46b3bd | 25 | #define __CORE_CMFUNC_H |
emilmont | 62:7e6c9f46b3bd | 26 | |
emilmont | 62:7e6c9f46b3bd | 27 | |
emilmont | 62:7e6c9f46b3bd | 28 | /* ########################### Core Function Access ########################### */ |
emilmont | 62:7e6c9f46b3bd | 29 | /** \ingroup CMSIS_Core_FunctionInterface |
emilmont | 62:7e6c9f46b3bd | 30 | \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions |
emilmont | 62:7e6c9f46b3bd | 31 | @{ |
emilmont | 62:7e6c9f46b3bd | 32 | */ |
emilmont | 62:7e6c9f46b3bd | 33 | |
emilmont | 62:7e6c9f46b3bd | 34 | #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ |
emilmont | 62:7e6c9f46b3bd | 35 | /* ARM armcc specific functions */ |
emilmont | 62:7e6c9f46b3bd | 36 | |
emilmont | 62:7e6c9f46b3bd | 37 | #if (__ARMCC_VERSION < 400677) |
emilmont | 62:7e6c9f46b3bd | 38 | #error "Please use ARM Compiler Toolchain V4.0.677 or later!" |
emilmont | 62:7e6c9f46b3bd | 39 | #endif |
emilmont | 62:7e6c9f46b3bd | 40 | |
emilmont | 62:7e6c9f46b3bd | 41 | /* intrinsic void __enable_irq(); */ |
emilmont | 62:7e6c9f46b3bd | 42 | /* intrinsic void __disable_irq(); */ |
emilmont | 62:7e6c9f46b3bd | 43 | |
emilmont | 62:7e6c9f46b3bd | 44 | /** \brief Get Control Register |
emilmont | 62:7e6c9f46b3bd | 45 | |
emilmont | 62:7e6c9f46b3bd | 46 | This function returns the content of the Control Register. |
emilmont | 62:7e6c9f46b3bd | 47 | |
emilmont | 62:7e6c9f46b3bd | 48 | \return Control Register value |
emilmont | 62:7e6c9f46b3bd | 49 | */ |
emilmont | 62:7e6c9f46b3bd | 50 | __STATIC_INLINE uint32_t __get_CONTROL(void) |
emilmont | 62:7e6c9f46b3bd | 51 | { |
emilmont | 62:7e6c9f46b3bd | 52 | register uint32_t __regControl __ASM("control"); |
emilmont | 62:7e6c9f46b3bd | 53 | return(__regControl); |
emilmont | 62:7e6c9f46b3bd | 54 | } |
emilmont | 62:7e6c9f46b3bd | 55 | |
emilmont | 62:7e6c9f46b3bd | 56 | |
emilmont | 62:7e6c9f46b3bd | 57 | /** \brief Set Control Register |
emilmont | 62:7e6c9f46b3bd | 58 | |
emilmont | 62:7e6c9f46b3bd | 59 | This function writes the given value to the Control Register. |
emilmont | 62:7e6c9f46b3bd | 60 | |
emilmont | 62:7e6c9f46b3bd | 61 | \param [in] control Control Register value to set |
emilmont | 62:7e6c9f46b3bd | 62 | */ |
emilmont | 62:7e6c9f46b3bd | 63 | __STATIC_INLINE void __set_CONTROL(uint32_t control) |
emilmont | 62:7e6c9f46b3bd | 64 | { |
emilmont | 62:7e6c9f46b3bd | 65 | register uint32_t __regControl __ASM("control"); |
emilmont | 62:7e6c9f46b3bd | 66 | __regControl = control; |
emilmont | 62:7e6c9f46b3bd | 67 | } |
emilmont | 62:7e6c9f46b3bd | 68 | |
emilmont | 62:7e6c9f46b3bd | 69 | |
emilmont | 62:7e6c9f46b3bd | 70 | /** \brief Get IPSR Register |
emilmont | 62:7e6c9f46b3bd | 71 | |
emilmont | 62:7e6c9f46b3bd | 72 | This function returns the content of the IPSR Register. |
emilmont | 62:7e6c9f46b3bd | 73 | |
emilmont | 62:7e6c9f46b3bd | 74 | \return IPSR Register value |
emilmont | 62:7e6c9f46b3bd | 75 | */ |
emilmont | 62:7e6c9f46b3bd | 76 | __STATIC_INLINE uint32_t __get_IPSR(void) |
emilmont | 62:7e6c9f46b3bd | 77 | { |
emilmont | 62:7e6c9f46b3bd | 78 | register uint32_t __regIPSR __ASM("ipsr"); |
emilmont | 62:7e6c9f46b3bd | 79 | return(__regIPSR); |
emilmont | 62:7e6c9f46b3bd | 80 | } |
emilmont | 62:7e6c9f46b3bd | 81 | |
emilmont | 62:7e6c9f46b3bd | 82 | |
emilmont | 62:7e6c9f46b3bd | 83 | /** \brief Get APSR Register |
emilmont | 62:7e6c9f46b3bd | 84 | |
emilmont | 62:7e6c9f46b3bd | 85 | This function returns the content of the APSR Register. |
emilmont | 62:7e6c9f46b3bd | 86 | |
emilmont | 62:7e6c9f46b3bd | 87 | \return APSR Register value |
emilmont | 62:7e6c9f46b3bd | 88 | */ |
emilmont | 62:7e6c9f46b3bd | 89 | __STATIC_INLINE uint32_t __get_APSR(void) |
emilmont | 62:7e6c9f46b3bd | 90 | { |
emilmont | 62:7e6c9f46b3bd | 91 | register uint32_t __regAPSR __ASM("apsr"); |
emilmont | 62:7e6c9f46b3bd | 92 | return(__regAPSR); |
emilmont | 62:7e6c9f46b3bd | 93 | } |
emilmont | 62:7e6c9f46b3bd | 94 | |
emilmont | 62:7e6c9f46b3bd | 95 | |
emilmont | 62:7e6c9f46b3bd | 96 | /** \brief Get xPSR Register |
emilmont | 62:7e6c9f46b3bd | 97 | |
emilmont | 62:7e6c9f46b3bd | 98 | This function returns the content of the xPSR Register. |
emilmont | 62:7e6c9f46b3bd | 99 | |
emilmont | 62:7e6c9f46b3bd | 100 | \return xPSR Register value |
emilmont | 62:7e6c9f46b3bd | 101 | */ |
emilmont | 62:7e6c9f46b3bd | 102 | __STATIC_INLINE uint32_t __get_xPSR(void) |
emilmont | 62:7e6c9f46b3bd | 103 | { |
emilmont | 62:7e6c9f46b3bd | 104 | register uint32_t __regXPSR __ASM("xpsr"); |
emilmont | 62:7e6c9f46b3bd | 105 | return(__regXPSR); |
emilmont | 62:7e6c9f46b3bd | 106 | } |
emilmont | 62:7e6c9f46b3bd | 107 | |
emilmont | 62:7e6c9f46b3bd | 108 | |
emilmont | 62:7e6c9f46b3bd | 109 | /** \brief Get Process Stack Pointer |
emilmont | 62:7e6c9f46b3bd | 110 | |
emilmont | 62:7e6c9f46b3bd | 111 | This function returns the current value of the Process Stack Pointer (PSP). |
emilmont | 62:7e6c9f46b3bd | 112 | |
emilmont | 62:7e6c9f46b3bd | 113 | \return PSP Register value |
emilmont | 62:7e6c9f46b3bd | 114 | */ |
emilmont | 62:7e6c9f46b3bd | 115 | __STATIC_INLINE uint32_t __get_PSP(void) |
emilmont | 62:7e6c9f46b3bd | 116 | { |
emilmont | 62:7e6c9f46b3bd | 117 | register uint32_t __regProcessStackPointer __ASM("psp"); |
emilmont | 62:7e6c9f46b3bd | 118 | return(__regProcessStackPointer); |
emilmont | 62:7e6c9f46b3bd | 119 | } |
emilmont | 62:7e6c9f46b3bd | 120 | |
emilmont | 62:7e6c9f46b3bd | 121 | |
emilmont | 62:7e6c9f46b3bd | 122 | /** \brief Set Process Stack Pointer |
emilmont | 62:7e6c9f46b3bd | 123 | |
emilmont | 62:7e6c9f46b3bd | 124 | This function assigns the given value to the Process Stack Pointer (PSP). |
emilmont | 62:7e6c9f46b3bd | 125 | |
emilmont | 62:7e6c9f46b3bd | 126 | \param [in] topOfProcStack Process Stack Pointer value to set |
emilmont | 62:7e6c9f46b3bd | 127 | */ |
emilmont | 62:7e6c9f46b3bd | 128 | __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
emilmont | 62:7e6c9f46b3bd | 129 | { |
emilmont | 62:7e6c9f46b3bd | 130 | register uint32_t __regProcessStackPointer __ASM("psp"); |
emilmont | 62:7e6c9f46b3bd | 131 | __regProcessStackPointer = topOfProcStack; |
emilmont | 62:7e6c9f46b3bd | 132 | } |
emilmont | 62:7e6c9f46b3bd | 133 | |
emilmont | 62:7e6c9f46b3bd | 134 | |
emilmont | 62:7e6c9f46b3bd | 135 | /** \brief Get Main Stack Pointer |
emilmont | 62:7e6c9f46b3bd | 136 | |
emilmont | 62:7e6c9f46b3bd | 137 | This function returns the current value of the Main Stack Pointer (MSP). |
emilmont | 62:7e6c9f46b3bd | 138 | |
emilmont | 62:7e6c9f46b3bd | 139 | \return MSP Register value |
emilmont | 62:7e6c9f46b3bd | 140 | */ |
emilmont | 62:7e6c9f46b3bd | 141 | __STATIC_INLINE uint32_t __get_MSP(void) |
emilmont | 62:7e6c9f46b3bd | 142 | { |
emilmont | 62:7e6c9f46b3bd | 143 | register uint32_t __regMainStackPointer __ASM("msp"); |
emilmont | 62:7e6c9f46b3bd | 144 | return(__regMainStackPointer); |
emilmont | 62:7e6c9f46b3bd | 145 | } |
emilmont | 62:7e6c9f46b3bd | 146 | |
emilmont | 62:7e6c9f46b3bd | 147 | |
emilmont | 62:7e6c9f46b3bd | 148 | /** \brief Set Main Stack Pointer |
emilmont | 62:7e6c9f46b3bd | 149 | |
emilmont | 62:7e6c9f46b3bd | 150 | This function assigns the given value to the Main Stack Pointer (MSP). |
emilmont | 62:7e6c9f46b3bd | 151 | |
emilmont | 62:7e6c9f46b3bd | 152 | \param [in] topOfMainStack Main Stack Pointer value to set |
emilmont | 62:7e6c9f46b3bd | 153 | */ |
emilmont | 62:7e6c9f46b3bd | 154 | __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
emilmont | 62:7e6c9f46b3bd | 155 | { |
emilmont | 62:7e6c9f46b3bd | 156 | register uint32_t __regMainStackPointer __ASM("msp"); |
emilmont | 62:7e6c9f46b3bd | 157 | __regMainStackPointer = topOfMainStack; |
emilmont | 62:7e6c9f46b3bd | 158 | } |
emilmont | 62:7e6c9f46b3bd | 159 | |
emilmont | 62:7e6c9f46b3bd | 160 | |
emilmont | 62:7e6c9f46b3bd | 161 | /** \brief Get Priority Mask |
emilmont | 62:7e6c9f46b3bd | 162 | |
emilmont | 62:7e6c9f46b3bd | 163 | This function returns the current state of the priority mask bit from the Priority Mask Register. |
emilmont | 62:7e6c9f46b3bd | 164 | |
emilmont | 62:7e6c9f46b3bd | 165 | \return Priority Mask value |
emilmont | 62:7e6c9f46b3bd | 166 | */ |
emilmont | 62:7e6c9f46b3bd | 167 | __STATIC_INLINE uint32_t __get_PRIMASK(void) |
emilmont | 62:7e6c9f46b3bd | 168 | { |
emilmont | 62:7e6c9f46b3bd | 169 | register uint32_t __regPriMask __ASM("primask"); |
emilmont | 62:7e6c9f46b3bd | 170 | return(__regPriMask); |
emilmont | 62:7e6c9f46b3bd | 171 | } |
emilmont | 62:7e6c9f46b3bd | 172 | |
emilmont | 62:7e6c9f46b3bd | 173 | |
emilmont | 62:7e6c9f46b3bd | 174 | /** \brief Set Priority Mask |
emilmont | 62:7e6c9f46b3bd | 175 | |
emilmont | 62:7e6c9f46b3bd | 176 | This function assigns the given value to the Priority Mask Register. |
emilmont | 62:7e6c9f46b3bd | 177 | |
emilmont | 62:7e6c9f46b3bd | 178 | \param [in] priMask Priority Mask |
emilmont | 62:7e6c9f46b3bd | 179 | */ |
emilmont | 62:7e6c9f46b3bd | 180 | __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
emilmont | 62:7e6c9f46b3bd | 181 | { |
emilmont | 62:7e6c9f46b3bd | 182 | register uint32_t __regPriMask __ASM("primask"); |
emilmont | 62:7e6c9f46b3bd | 183 | __regPriMask = (priMask); |
emilmont | 62:7e6c9f46b3bd | 184 | } |
emilmont | 62:7e6c9f46b3bd | 185 | |
emilmont | 62:7e6c9f46b3bd | 186 | |
emilmont | 62:7e6c9f46b3bd | 187 | #if (__CORTEX_M >= 0x03) |
emilmont | 62:7e6c9f46b3bd | 188 | |
emilmont | 62:7e6c9f46b3bd | 189 | /** \brief Enable FIQ |
emilmont | 62:7e6c9f46b3bd | 190 | |
emilmont | 62:7e6c9f46b3bd | 191 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
emilmont | 62:7e6c9f46b3bd | 192 | Can only be executed in Privileged modes. |
emilmont | 62:7e6c9f46b3bd | 193 | */ |
emilmont | 62:7e6c9f46b3bd | 194 | #define __enable_fault_irq __enable_fiq |
emilmont | 62:7e6c9f46b3bd | 195 | |
emilmont | 62:7e6c9f46b3bd | 196 | |
emilmont | 62:7e6c9f46b3bd | 197 | /** \brief Disable FIQ |
emilmont | 62:7e6c9f46b3bd | 198 | |
emilmont | 62:7e6c9f46b3bd | 199 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
emilmont | 62:7e6c9f46b3bd | 200 | Can only be executed in Privileged modes. |
emilmont | 62:7e6c9f46b3bd | 201 | */ |
emilmont | 62:7e6c9f46b3bd | 202 | #define __disable_fault_irq __disable_fiq |
emilmont | 62:7e6c9f46b3bd | 203 | |
emilmont | 62:7e6c9f46b3bd | 204 | |
emilmont | 62:7e6c9f46b3bd | 205 | /** \brief Get Base Priority |
emilmont | 62:7e6c9f46b3bd | 206 | |
emilmont | 62:7e6c9f46b3bd | 207 | This function returns the current value of the Base Priority register. |
emilmont | 62:7e6c9f46b3bd | 208 | |
emilmont | 62:7e6c9f46b3bd | 209 | \return Base Priority register value |
emilmont | 62:7e6c9f46b3bd | 210 | */ |
emilmont | 62:7e6c9f46b3bd | 211 | __STATIC_INLINE uint32_t __get_BASEPRI(void) |
emilmont | 62:7e6c9f46b3bd | 212 | { |
emilmont | 62:7e6c9f46b3bd | 213 | register uint32_t __regBasePri __ASM("basepri"); |
emilmont | 62:7e6c9f46b3bd | 214 | return(__regBasePri); |
emilmont | 62:7e6c9f46b3bd | 215 | } |
emilmont | 62:7e6c9f46b3bd | 216 | |
emilmont | 62:7e6c9f46b3bd | 217 | |
emilmont | 62:7e6c9f46b3bd | 218 | /** \brief Set Base Priority |
emilmont | 62:7e6c9f46b3bd | 219 | |
emilmont | 62:7e6c9f46b3bd | 220 | This function assigns the given value to the Base Priority register. |
emilmont | 62:7e6c9f46b3bd | 221 | |
emilmont | 62:7e6c9f46b3bd | 222 | \param [in] basePri Base Priority value to set |
emilmont | 62:7e6c9f46b3bd | 223 | */ |
emilmont | 62:7e6c9f46b3bd | 224 | __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) |
emilmont | 62:7e6c9f46b3bd | 225 | { |
emilmont | 62:7e6c9f46b3bd | 226 | register uint32_t __regBasePri __ASM("basepri"); |
emilmont | 62:7e6c9f46b3bd | 227 | __regBasePri = (basePri & 0xff); |
emilmont | 62:7e6c9f46b3bd | 228 | } |
emilmont | 62:7e6c9f46b3bd | 229 | |
emilmont | 62:7e6c9f46b3bd | 230 | |
emilmont | 62:7e6c9f46b3bd | 231 | /** \brief Get Fault Mask |
emilmont | 62:7e6c9f46b3bd | 232 | |
emilmont | 62:7e6c9f46b3bd | 233 | This function returns the current value of the Fault Mask register. |
emilmont | 62:7e6c9f46b3bd | 234 | |
emilmont | 62:7e6c9f46b3bd | 235 | \return Fault Mask register value |
emilmont | 62:7e6c9f46b3bd | 236 | */ |
emilmont | 62:7e6c9f46b3bd | 237 | __STATIC_INLINE uint32_t __get_FAULTMASK(void) |
emilmont | 62:7e6c9f46b3bd | 238 | { |
emilmont | 62:7e6c9f46b3bd | 239 | register uint32_t __regFaultMask __ASM("faultmask"); |
emilmont | 62:7e6c9f46b3bd | 240 | return(__regFaultMask); |
emilmont | 62:7e6c9f46b3bd | 241 | } |
emilmont | 62:7e6c9f46b3bd | 242 | |
emilmont | 62:7e6c9f46b3bd | 243 | |
emilmont | 62:7e6c9f46b3bd | 244 | /** \brief Set Fault Mask |
emilmont | 62:7e6c9f46b3bd | 245 | |
emilmont | 62:7e6c9f46b3bd | 246 | This function assigns the given value to the Fault Mask register. |
emilmont | 62:7e6c9f46b3bd | 247 | |
emilmont | 62:7e6c9f46b3bd | 248 | \param [in] faultMask Fault Mask value to set |
emilmont | 62:7e6c9f46b3bd | 249 | */ |
emilmont | 62:7e6c9f46b3bd | 250 | __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
emilmont | 62:7e6c9f46b3bd | 251 | { |
emilmont | 62:7e6c9f46b3bd | 252 | register uint32_t __regFaultMask __ASM("faultmask"); |
emilmont | 62:7e6c9f46b3bd | 253 | __regFaultMask = (faultMask & (uint32_t)1); |
emilmont | 62:7e6c9f46b3bd | 254 | } |
emilmont | 62:7e6c9f46b3bd | 255 | |
emilmont | 62:7e6c9f46b3bd | 256 | #endif /* (__CORTEX_M >= 0x03) */ |
emilmont | 62:7e6c9f46b3bd | 257 | |
emilmont | 62:7e6c9f46b3bd | 258 | |
emilmont | 62:7e6c9f46b3bd | 259 | #if (__CORTEX_M == 0x04) |
emilmont | 62:7e6c9f46b3bd | 260 | |
emilmont | 62:7e6c9f46b3bd | 261 | /** \brief Get FPSCR |
emilmont | 62:7e6c9f46b3bd | 262 | |
emilmont | 62:7e6c9f46b3bd | 263 | This function returns the current value of the Floating Point Status/Control register. |
emilmont | 62:7e6c9f46b3bd | 264 | |
emilmont | 62:7e6c9f46b3bd | 265 | \return Floating Point Status/Control register value |
emilmont | 62:7e6c9f46b3bd | 266 | */ |
emilmont | 62:7e6c9f46b3bd | 267 | __STATIC_INLINE uint32_t __get_FPSCR(void) |
emilmont | 62:7e6c9f46b3bd | 268 | { |
emilmont | 62:7e6c9f46b3bd | 269 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
emilmont | 62:7e6c9f46b3bd | 270 | register uint32_t __regfpscr __ASM("fpscr"); |
emilmont | 62:7e6c9f46b3bd | 271 | return(__regfpscr); |
emilmont | 62:7e6c9f46b3bd | 272 | #else |
emilmont | 62:7e6c9f46b3bd | 273 | return(0); |
emilmont | 62:7e6c9f46b3bd | 274 | #endif |
emilmont | 62:7e6c9f46b3bd | 275 | } |
emilmont | 62:7e6c9f46b3bd | 276 | |
emilmont | 62:7e6c9f46b3bd | 277 | |
emilmont | 62:7e6c9f46b3bd | 278 | /** \brief Set FPSCR |
emilmont | 62:7e6c9f46b3bd | 279 | |
emilmont | 62:7e6c9f46b3bd | 280 | This function assigns the given value to the Floating Point Status/Control register. |
emilmont | 62:7e6c9f46b3bd | 281 | |
emilmont | 62:7e6c9f46b3bd | 282 | \param [in] fpscr Floating Point Status/Control value to set |
emilmont | 62:7e6c9f46b3bd | 283 | */ |
emilmont | 62:7e6c9f46b3bd | 284 | __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
emilmont | 62:7e6c9f46b3bd | 285 | { |
emilmont | 62:7e6c9f46b3bd | 286 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
emilmont | 62:7e6c9f46b3bd | 287 | register uint32_t __regfpscr __ASM("fpscr"); |
emilmont | 62:7e6c9f46b3bd | 288 | __regfpscr = (fpscr); |
emilmont | 62:7e6c9f46b3bd | 289 | #endif |
emilmont | 62:7e6c9f46b3bd | 290 | } |
emilmont | 62:7e6c9f46b3bd | 291 | |
emilmont | 62:7e6c9f46b3bd | 292 | #endif /* (__CORTEX_M == 0x04) */ |
emilmont | 62:7e6c9f46b3bd | 293 | |
emilmont | 62:7e6c9f46b3bd | 294 | |
emilmont | 62:7e6c9f46b3bd | 295 | #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ |
emilmont | 62:7e6c9f46b3bd | 296 | /* IAR iccarm specific functions */ |
emilmont | 62:7e6c9f46b3bd | 297 | |
emilmont | 62:7e6c9f46b3bd | 298 | #include <cmsis_iar.h> |
emilmont | 62:7e6c9f46b3bd | 299 | |
emilmont | 62:7e6c9f46b3bd | 300 | |
emilmont | 62:7e6c9f46b3bd | 301 | #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ |
emilmont | 62:7e6c9f46b3bd | 302 | /* TI CCS specific functions */ |
emilmont | 62:7e6c9f46b3bd | 303 | |
emilmont | 62:7e6c9f46b3bd | 304 | #include <cmsis_ccs.h> |
emilmont | 62:7e6c9f46b3bd | 305 | |
emilmont | 62:7e6c9f46b3bd | 306 | |
emilmont | 62:7e6c9f46b3bd | 307 | #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ |
emilmont | 62:7e6c9f46b3bd | 308 | /* GNU gcc specific functions */ |
emilmont | 62:7e6c9f46b3bd | 309 | |
emilmont | 62:7e6c9f46b3bd | 310 | /** \brief Enable IRQ Interrupts |
emilmont | 62:7e6c9f46b3bd | 311 | |
emilmont | 62:7e6c9f46b3bd | 312 | This function enables IRQ interrupts by clearing the I-bit in the CPSR. |
emilmont | 62:7e6c9f46b3bd | 313 | Can only be executed in Privileged modes. |
emilmont | 62:7e6c9f46b3bd | 314 | */ |
emilmont | 62:7e6c9f46b3bd | 315 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) |
emilmont | 62:7e6c9f46b3bd | 316 | { |
emilmont | 62:7e6c9f46b3bd | 317 | __ASM volatile ("cpsie i" : : : "memory"); |
emilmont | 62:7e6c9f46b3bd | 318 | } |
emilmont | 62:7e6c9f46b3bd | 319 | |
emilmont | 62:7e6c9f46b3bd | 320 | |
emilmont | 62:7e6c9f46b3bd | 321 | /** \brief Disable IRQ Interrupts |
emilmont | 62:7e6c9f46b3bd | 322 | |
emilmont | 62:7e6c9f46b3bd | 323 | This function disables IRQ interrupts by setting the I-bit in the CPSR. |
emilmont | 62:7e6c9f46b3bd | 324 | Can only be executed in Privileged modes. |
emilmont | 62:7e6c9f46b3bd | 325 | */ |
emilmont | 62:7e6c9f46b3bd | 326 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) |
emilmont | 62:7e6c9f46b3bd | 327 | { |
emilmont | 62:7e6c9f46b3bd | 328 | __ASM volatile ("cpsid i" : : : "memory"); |
emilmont | 62:7e6c9f46b3bd | 329 | } |
emilmont | 62:7e6c9f46b3bd | 330 | |
emilmont | 62:7e6c9f46b3bd | 331 | |
emilmont | 62:7e6c9f46b3bd | 332 | /** \brief Get Control Register |
emilmont | 62:7e6c9f46b3bd | 333 | |
emilmont | 62:7e6c9f46b3bd | 334 | This function returns the content of the Control Register. |
emilmont | 62:7e6c9f46b3bd | 335 | |
emilmont | 62:7e6c9f46b3bd | 336 | \return Control Register value |
emilmont | 62:7e6c9f46b3bd | 337 | */ |
emilmont | 62:7e6c9f46b3bd | 338 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) |
emilmont | 62:7e6c9f46b3bd | 339 | { |
emilmont | 62:7e6c9f46b3bd | 340 | uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 341 | |
emilmont | 62:7e6c9f46b3bd | 342 | __ASM volatile ("MRS %0, control" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 343 | return(result); |
emilmont | 62:7e6c9f46b3bd | 344 | } |
emilmont | 62:7e6c9f46b3bd | 345 | |
emilmont | 62:7e6c9f46b3bd | 346 | |
emilmont | 62:7e6c9f46b3bd | 347 | /** \brief Set Control Register |
emilmont | 62:7e6c9f46b3bd | 348 | |
emilmont | 62:7e6c9f46b3bd | 349 | This function writes the given value to the Control Register. |
emilmont | 62:7e6c9f46b3bd | 350 | |
emilmont | 62:7e6c9f46b3bd | 351 | \param [in] control Control Register value to set |
emilmont | 62:7e6c9f46b3bd | 352 | */ |
emilmont | 62:7e6c9f46b3bd | 353 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) |
emilmont | 62:7e6c9f46b3bd | 354 | { |
emilmont | 62:7e6c9f46b3bd | 355 | __ASM volatile ("MSR control, %0" : : "r" (control) ); |
emilmont | 62:7e6c9f46b3bd | 356 | } |
emilmont | 62:7e6c9f46b3bd | 357 | |
emilmont | 62:7e6c9f46b3bd | 358 | |
emilmont | 62:7e6c9f46b3bd | 359 | /** \brief Get IPSR Register |
emilmont | 62:7e6c9f46b3bd | 360 | |
emilmont | 62:7e6c9f46b3bd | 361 | This function returns the content of the IPSR Register. |
emilmont | 62:7e6c9f46b3bd | 362 | |
emilmont | 62:7e6c9f46b3bd | 363 | \return IPSR Register value |
emilmont | 62:7e6c9f46b3bd | 364 | */ |
emilmont | 62:7e6c9f46b3bd | 365 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) |
emilmont | 62:7e6c9f46b3bd | 366 | { |
emilmont | 62:7e6c9f46b3bd | 367 | uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 368 | |
emilmont | 62:7e6c9f46b3bd | 369 | __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 370 | return(result); |
emilmont | 62:7e6c9f46b3bd | 371 | } |
emilmont | 62:7e6c9f46b3bd | 372 | |
emilmont | 62:7e6c9f46b3bd | 373 | |
emilmont | 62:7e6c9f46b3bd | 374 | /** \brief Get APSR Register |
emilmont | 62:7e6c9f46b3bd | 375 | |
emilmont | 62:7e6c9f46b3bd | 376 | This function returns the content of the APSR Register. |
emilmont | 62:7e6c9f46b3bd | 377 | |
emilmont | 62:7e6c9f46b3bd | 378 | \return APSR Register value |
emilmont | 62:7e6c9f46b3bd | 379 | */ |
emilmont | 62:7e6c9f46b3bd | 380 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) |
emilmont | 62:7e6c9f46b3bd | 381 | { |
emilmont | 62:7e6c9f46b3bd | 382 | uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 383 | |
emilmont | 62:7e6c9f46b3bd | 384 | __ASM volatile ("MRS %0, apsr" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 385 | return(result); |
emilmont | 62:7e6c9f46b3bd | 386 | } |
emilmont | 62:7e6c9f46b3bd | 387 | |
emilmont | 62:7e6c9f46b3bd | 388 | |
emilmont | 62:7e6c9f46b3bd | 389 | /** \brief Get xPSR Register |
emilmont | 62:7e6c9f46b3bd | 390 | |
emilmont | 62:7e6c9f46b3bd | 391 | This function returns the content of the xPSR Register. |
emilmont | 62:7e6c9f46b3bd | 392 | |
emilmont | 62:7e6c9f46b3bd | 393 | \return xPSR Register value |
emilmont | 62:7e6c9f46b3bd | 394 | */ |
emilmont | 62:7e6c9f46b3bd | 395 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) |
emilmont | 62:7e6c9f46b3bd | 396 | { |
emilmont | 62:7e6c9f46b3bd | 397 | uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 398 | |
emilmont | 62:7e6c9f46b3bd | 399 | __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 400 | return(result); |
emilmont | 62:7e6c9f46b3bd | 401 | } |
emilmont | 62:7e6c9f46b3bd | 402 | |
emilmont | 62:7e6c9f46b3bd | 403 | |
emilmont | 62:7e6c9f46b3bd | 404 | /** \brief Get Process Stack Pointer |
emilmont | 62:7e6c9f46b3bd | 405 | |
emilmont | 62:7e6c9f46b3bd | 406 | This function returns the current value of the Process Stack Pointer (PSP). |
emilmont | 62:7e6c9f46b3bd | 407 | |
emilmont | 62:7e6c9f46b3bd | 408 | \return PSP Register value |
emilmont | 62:7e6c9f46b3bd | 409 | */ |
emilmont | 62:7e6c9f46b3bd | 410 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) |
emilmont | 62:7e6c9f46b3bd | 411 | { |
emilmont | 62:7e6c9f46b3bd | 412 | register uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 413 | |
emilmont | 62:7e6c9f46b3bd | 414 | __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 415 | return(result); |
emilmont | 62:7e6c9f46b3bd | 416 | } |
emilmont | 62:7e6c9f46b3bd | 417 | |
emilmont | 62:7e6c9f46b3bd | 418 | |
emilmont | 62:7e6c9f46b3bd | 419 | /** \brief Set Process Stack Pointer |
emilmont | 62:7e6c9f46b3bd | 420 | |
emilmont | 62:7e6c9f46b3bd | 421 | This function assigns the given value to the Process Stack Pointer (PSP). |
emilmont | 62:7e6c9f46b3bd | 422 | |
emilmont | 62:7e6c9f46b3bd | 423 | \param [in] topOfProcStack Process Stack Pointer value to set |
emilmont | 62:7e6c9f46b3bd | 424 | */ |
emilmont | 62:7e6c9f46b3bd | 425 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) |
emilmont | 62:7e6c9f46b3bd | 426 | { |
emilmont | 62:7e6c9f46b3bd | 427 | __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); |
emilmont | 62:7e6c9f46b3bd | 428 | } |
emilmont | 62:7e6c9f46b3bd | 429 | |
emilmont | 62:7e6c9f46b3bd | 430 | |
emilmont | 62:7e6c9f46b3bd | 431 | /** \brief Get Main Stack Pointer |
emilmont | 62:7e6c9f46b3bd | 432 | |
emilmont | 62:7e6c9f46b3bd | 433 | This function returns the current value of the Main Stack Pointer (MSP). |
emilmont | 62:7e6c9f46b3bd | 434 | |
emilmont | 62:7e6c9f46b3bd | 435 | \return MSP Register value |
emilmont | 62:7e6c9f46b3bd | 436 | */ |
emilmont | 62:7e6c9f46b3bd | 437 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) |
emilmont | 62:7e6c9f46b3bd | 438 | { |
emilmont | 62:7e6c9f46b3bd | 439 | register uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 440 | |
emilmont | 62:7e6c9f46b3bd | 441 | __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 442 | return(result); |
emilmont | 62:7e6c9f46b3bd | 443 | } |
emilmont | 62:7e6c9f46b3bd | 444 | |
emilmont | 62:7e6c9f46b3bd | 445 | |
emilmont | 62:7e6c9f46b3bd | 446 | /** \brief Set Main Stack Pointer |
emilmont | 62:7e6c9f46b3bd | 447 | |
emilmont | 62:7e6c9f46b3bd | 448 | This function assigns the given value to the Main Stack Pointer (MSP). |
emilmont | 62:7e6c9f46b3bd | 449 | |
emilmont | 62:7e6c9f46b3bd | 450 | \param [in] topOfMainStack Main Stack Pointer value to set |
emilmont | 62:7e6c9f46b3bd | 451 | */ |
emilmont | 62:7e6c9f46b3bd | 452 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) |
emilmont | 62:7e6c9f46b3bd | 453 | { |
emilmont | 62:7e6c9f46b3bd | 454 | __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); |
emilmont | 62:7e6c9f46b3bd | 455 | } |
emilmont | 62:7e6c9f46b3bd | 456 | |
emilmont | 62:7e6c9f46b3bd | 457 | |
emilmont | 62:7e6c9f46b3bd | 458 | /** \brief Get Priority Mask |
emilmont | 62:7e6c9f46b3bd | 459 | |
emilmont | 62:7e6c9f46b3bd | 460 | This function returns the current state of the priority mask bit from the Priority Mask Register. |
emilmont | 62:7e6c9f46b3bd | 461 | |
emilmont | 62:7e6c9f46b3bd | 462 | \return Priority Mask value |
emilmont | 62:7e6c9f46b3bd | 463 | */ |
emilmont | 62:7e6c9f46b3bd | 464 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) |
emilmont | 62:7e6c9f46b3bd | 465 | { |
emilmont | 62:7e6c9f46b3bd | 466 | uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 467 | |
emilmont | 62:7e6c9f46b3bd | 468 | __ASM volatile ("MRS %0, primask" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 469 | return(result); |
emilmont | 62:7e6c9f46b3bd | 470 | } |
emilmont | 62:7e6c9f46b3bd | 471 | |
emilmont | 62:7e6c9f46b3bd | 472 | |
emilmont | 62:7e6c9f46b3bd | 473 | /** \brief Set Priority Mask |
emilmont | 62:7e6c9f46b3bd | 474 | |
emilmont | 62:7e6c9f46b3bd | 475 | This function assigns the given value to the Priority Mask Register. |
emilmont | 62:7e6c9f46b3bd | 476 | |
emilmont | 62:7e6c9f46b3bd | 477 | \param [in] priMask Priority Mask |
emilmont | 62:7e6c9f46b3bd | 478 | */ |
emilmont | 62:7e6c9f46b3bd | 479 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) |
emilmont | 62:7e6c9f46b3bd | 480 | { |
emilmont | 62:7e6c9f46b3bd | 481 | __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); |
emilmont | 62:7e6c9f46b3bd | 482 | } |
emilmont | 62:7e6c9f46b3bd | 483 | |
emilmont | 62:7e6c9f46b3bd | 484 | |
emilmont | 62:7e6c9f46b3bd | 485 | #if (__CORTEX_M >= 0x03) |
emilmont | 62:7e6c9f46b3bd | 486 | |
emilmont | 62:7e6c9f46b3bd | 487 | /** \brief Enable FIQ |
emilmont | 62:7e6c9f46b3bd | 488 | |
emilmont | 62:7e6c9f46b3bd | 489 | This function enables FIQ interrupts by clearing the F-bit in the CPSR. |
emilmont | 62:7e6c9f46b3bd | 490 | Can only be executed in Privileged modes. |
emilmont | 62:7e6c9f46b3bd | 491 | */ |
emilmont | 62:7e6c9f46b3bd | 492 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) |
emilmont | 62:7e6c9f46b3bd | 493 | { |
emilmont | 62:7e6c9f46b3bd | 494 | __ASM volatile ("cpsie f" : : : "memory"); |
emilmont | 62:7e6c9f46b3bd | 495 | } |
emilmont | 62:7e6c9f46b3bd | 496 | |
emilmont | 62:7e6c9f46b3bd | 497 | |
emilmont | 62:7e6c9f46b3bd | 498 | /** \brief Disable FIQ |
emilmont | 62:7e6c9f46b3bd | 499 | |
emilmont | 62:7e6c9f46b3bd | 500 | This function disables FIQ interrupts by setting the F-bit in the CPSR. |
emilmont | 62:7e6c9f46b3bd | 501 | Can only be executed in Privileged modes. |
emilmont | 62:7e6c9f46b3bd | 502 | */ |
emilmont | 62:7e6c9f46b3bd | 503 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) |
emilmont | 62:7e6c9f46b3bd | 504 | { |
emilmont | 62:7e6c9f46b3bd | 505 | __ASM volatile ("cpsid f" : : : "memory"); |
emilmont | 62:7e6c9f46b3bd | 506 | } |
emilmont | 62:7e6c9f46b3bd | 507 | |
emilmont | 62:7e6c9f46b3bd | 508 | |
emilmont | 62:7e6c9f46b3bd | 509 | /** \brief Get Base Priority |
emilmont | 62:7e6c9f46b3bd | 510 | |
emilmont | 62:7e6c9f46b3bd | 511 | This function returns the current value of the Base Priority register. |
emilmont | 62:7e6c9f46b3bd | 512 | |
emilmont | 62:7e6c9f46b3bd | 513 | \return Base Priority register value |
emilmont | 62:7e6c9f46b3bd | 514 | */ |
emilmont | 62:7e6c9f46b3bd | 515 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) |
emilmont | 62:7e6c9f46b3bd | 516 | { |
emilmont | 62:7e6c9f46b3bd | 517 | uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 518 | |
emilmont | 62:7e6c9f46b3bd | 519 | __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 520 | return(result); |
emilmont | 62:7e6c9f46b3bd | 521 | } |
emilmont | 62:7e6c9f46b3bd | 522 | |
emilmont | 62:7e6c9f46b3bd | 523 | |
emilmont | 62:7e6c9f46b3bd | 524 | /** \brief Set Base Priority |
emilmont | 62:7e6c9f46b3bd | 525 | |
emilmont | 62:7e6c9f46b3bd | 526 | This function assigns the given value to the Base Priority register. |
emilmont | 62:7e6c9f46b3bd | 527 | |
emilmont | 62:7e6c9f46b3bd | 528 | \param [in] basePri Base Priority value to set |
emilmont | 62:7e6c9f46b3bd | 529 | */ |
emilmont | 62:7e6c9f46b3bd | 530 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) |
emilmont | 62:7e6c9f46b3bd | 531 | { |
emilmont | 62:7e6c9f46b3bd | 532 | __ASM volatile ("MSR basepri, %0" : : "r" (value) ); |
emilmont | 62:7e6c9f46b3bd | 533 | } |
emilmont | 62:7e6c9f46b3bd | 534 | |
emilmont | 62:7e6c9f46b3bd | 535 | |
emilmont | 62:7e6c9f46b3bd | 536 | /** \brief Get Fault Mask |
emilmont | 62:7e6c9f46b3bd | 537 | |
emilmont | 62:7e6c9f46b3bd | 538 | This function returns the current value of the Fault Mask register. |
emilmont | 62:7e6c9f46b3bd | 539 | |
emilmont | 62:7e6c9f46b3bd | 540 | \return Fault Mask register value |
emilmont | 62:7e6c9f46b3bd | 541 | */ |
emilmont | 62:7e6c9f46b3bd | 542 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) |
emilmont | 62:7e6c9f46b3bd | 543 | { |
emilmont | 62:7e6c9f46b3bd | 544 | uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 545 | |
emilmont | 62:7e6c9f46b3bd | 546 | __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 547 | return(result); |
emilmont | 62:7e6c9f46b3bd | 548 | } |
emilmont | 62:7e6c9f46b3bd | 549 | |
emilmont | 62:7e6c9f46b3bd | 550 | |
emilmont | 62:7e6c9f46b3bd | 551 | /** \brief Set Fault Mask |
emilmont | 62:7e6c9f46b3bd | 552 | |
emilmont | 62:7e6c9f46b3bd | 553 | This function assigns the given value to the Fault Mask register. |
emilmont | 62:7e6c9f46b3bd | 554 | |
emilmont | 62:7e6c9f46b3bd | 555 | \param [in] faultMask Fault Mask value to set |
emilmont | 62:7e6c9f46b3bd | 556 | */ |
emilmont | 62:7e6c9f46b3bd | 557 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) |
emilmont | 62:7e6c9f46b3bd | 558 | { |
emilmont | 62:7e6c9f46b3bd | 559 | __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); |
emilmont | 62:7e6c9f46b3bd | 560 | } |
emilmont | 62:7e6c9f46b3bd | 561 | |
emilmont | 62:7e6c9f46b3bd | 562 | #endif /* (__CORTEX_M >= 0x03) */ |
emilmont | 62:7e6c9f46b3bd | 563 | |
emilmont | 62:7e6c9f46b3bd | 564 | |
emilmont | 62:7e6c9f46b3bd | 565 | #if (__CORTEX_M == 0x04) |
emilmont | 62:7e6c9f46b3bd | 566 | |
emilmont | 62:7e6c9f46b3bd | 567 | /** \brief Get FPSCR |
emilmont | 62:7e6c9f46b3bd | 568 | |
emilmont | 62:7e6c9f46b3bd | 569 | This function returns the current value of the Floating Point Status/Control register. |
emilmont | 62:7e6c9f46b3bd | 570 | |
emilmont | 62:7e6c9f46b3bd | 571 | \return Floating Point Status/Control register value |
emilmont | 62:7e6c9f46b3bd | 572 | */ |
emilmont | 62:7e6c9f46b3bd | 573 | __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) |
emilmont | 62:7e6c9f46b3bd | 574 | { |
emilmont | 62:7e6c9f46b3bd | 575 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
emilmont | 62:7e6c9f46b3bd | 576 | uint32_t result; |
emilmont | 62:7e6c9f46b3bd | 577 | |
emilmont | 62:7e6c9f46b3bd | 578 | __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); |
emilmont | 62:7e6c9f46b3bd | 579 | return(result); |
emilmont | 62:7e6c9f46b3bd | 580 | #else |
emilmont | 62:7e6c9f46b3bd | 581 | return(0); |
emilmont | 62:7e6c9f46b3bd | 582 | #endif |
emilmont | 62:7e6c9f46b3bd | 583 | } |
emilmont | 62:7e6c9f46b3bd | 584 | |
emilmont | 62:7e6c9f46b3bd | 585 | |
emilmont | 62:7e6c9f46b3bd | 586 | /** \brief Set FPSCR |
emilmont | 62:7e6c9f46b3bd | 587 | |
emilmont | 62:7e6c9f46b3bd | 588 | This function assigns the given value to the Floating Point Status/Control register. |
emilmont | 62:7e6c9f46b3bd | 589 | |
emilmont | 62:7e6c9f46b3bd | 590 | \param [in] fpscr Floating Point Status/Control value to set |
emilmont | 62:7e6c9f46b3bd | 591 | */ |
emilmont | 62:7e6c9f46b3bd | 592 | __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) |
emilmont | 62:7e6c9f46b3bd | 593 | { |
emilmont | 62:7e6c9f46b3bd | 594 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
emilmont | 62:7e6c9f46b3bd | 595 | __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); |
emilmont | 62:7e6c9f46b3bd | 596 | #endif |
emilmont | 62:7e6c9f46b3bd | 597 | } |
emilmont | 62:7e6c9f46b3bd | 598 | |
emilmont | 62:7e6c9f46b3bd | 599 | #endif /* (__CORTEX_M == 0x04) */ |
emilmont | 62:7e6c9f46b3bd | 600 | |
emilmont | 62:7e6c9f46b3bd | 601 | |
emilmont | 62:7e6c9f46b3bd | 602 | #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ |
emilmont | 62:7e6c9f46b3bd | 603 | /* TASKING carm specific functions */ |
emilmont | 62:7e6c9f46b3bd | 604 | |
emilmont | 62:7e6c9f46b3bd | 605 | /* |
emilmont | 62:7e6c9f46b3bd | 606 | * The CMSIS functions have been implemented as intrinsics in the compiler. |
emilmont | 62:7e6c9f46b3bd | 607 | * Please use "carm -?i" to get an up to date list of all instrinsics, |
emilmont | 62:7e6c9f46b3bd | 608 | * Including the CMSIS ones. |
emilmont | 62:7e6c9f46b3bd | 609 | */ |
emilmont | 62:7e6c9f46b3bd | 610 | |
emilmont | 62:7e6c9f46b3bd | 611 | #endif |
emilmont | 62:7e6c9f46b3bd | 612 | |
emilmont | 62:7e6c9f46b3bd | 613 | /*@} end of CMSIS_Core_RegAccFunctions */ |
emilmont | 62:7e6c9f46b3bd | 614 | |
emilmont | 62:7e6c9f46b3bd | 615 | |
emilmont | 62:7e6c9f46b3bd | 616 | #endif /* __CORE_CMFUNC_H */ |