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CMSIS DSP Lib

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cmsis_dsp/BasicMathFunctions/arm_shift_q7.c@3:7a284390b0ce, 2013-11-08 (annotated)

Committer:
mbed_official
Date:
Fri Nov 08 13:45:10 2013 +0000
Revision:
3:7a284390b0ce
Parent:
2:da51fb522205 
Synchronized with git revision e69956aba2f68a2a26ac26b051f8d349deaa1ce8

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 3:7a284390b0ce 2 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 3:7a284390b0ce 4 * $Date: 17. January 2013
mbed_official 3:7a284390b0ce 5 * $Revision: V1.4.1
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_shift_q7.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Processing function for the Q7 Shifting
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
mbed_official 3:7a284390b0ce 14 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 15 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 16 * are met:
mbed_official 3:7a284390b0ce 17 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 18 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 19 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 20 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 21 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 22 * distribution.
mbed_official 3:7a284390b0ce 23 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 24 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 25 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 26 *
mbed_official 3:7a284390b0ce 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 38 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 39 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 42
emilmont 1:fdd22bb7aa52 43 /**
emilmont 1:fdd22bb7aa52 44 * @ingroup groupMath
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47 /**
emilmont 1:fdd22bb7aa52 48 * @addtogroup shift
emilmont 1:fdd22bb7aa52 49 * @{
emilmont 1:fdd22bb7aa52 50 */
emilmont 1:fdd22bb7aa52 51
emilmont 1:fdd22bb7aa52 52
emilmont 1:fdd22bb7aa52 53 /**
emilmont 1:fdd22bb7aa52 54 * @brief Shifts the elements of a Q7 vector a specified number of bits.
emilmont 1:fdd22bb7aa52 55 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 56 * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
emilmont 1:fdd22bb7aa52 57 * @param[out] *pDst points to the output vector
emilmont 1:fdd22bb7aa52 58 * @param[in] blockSize number of samples in the vector
emilmont 1:fdd22bb7aa52 59 * @return none.
emilmont 1:fdd22bb7aa52 60 *
emilmont 1:fdd22bb7aa52 61 * \par Conditions for optimum performance
emilmont 1:fdd22bb7aa52 62 * Input and output buffers should be aligned by 32-bit
emilmont 1:fdd22bb7aa52 63 *
emilmont 1:fdd22bb7aa52 64 *
emilmont 1:fdd22bb7aa52 65 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 66 * \par
emilmont 1:fdd22bb7aa52 67 * The function uses saturating arithmetic.
emilmont 1:fdd22bb7aa52 68 * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated.
emilmont 1:fdd22bb7aa52 69 */
emilmont 1:fdd22bb7aa52 70
emilmont 1:fdd22bb7aa52 71 void arm_shift_q7(
emilmont 1:fdd22bb7aa52 72 q7_t * pSrc,
emilmont 1:fdd22bb7aa52 73 int8_t shiftBits,
emilmont 1:fdd22bb7aa52 74 q7_t * pDst,
emilmont 1:fdd22bb7aa52 75 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 76 {
emilmont 1:fdd22bb7aa52 77 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 78 uint8_t sign; /* Sign of shiftBits */
emilmont 1:fdd22bb7aa52 79
mbed_official 3:7a284390b0ce 80 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 81
emilmont 1:fdd22bb7aa52 82 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 83 q7_t in1; /* Input value1 */
emilmont 1:fdd22bb7aa52 84 q7_t in2; /* Input value2 */
emilmont 1:fdd22bb7aa52 85 q7_t in3; /* Input value3 */
emilmont 1:fdd22bb7aa52 86 q7_t in4; /* Input value4 */
emilmont 1:fdd22bb7aa52 87
emilmont 1:fdd22bb7aa52 88
emilmont 1:fdd22bb7aa52 89 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 90 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 91
emilmont 1:fdd22bb7aa52 92 /* Getting the sign of shiftBits */
emilmont 1:fdd22bb7aa52 93 sign = (shiftBits & 0x80);
emilmont 1:fdd22bb7aa52 94
emilmont 1:fdd22bb7aa52 95 /* If the shift value is positive then do right shift else left shift */
emilmont 1:fdd22bb7aa52 96 if(sign == 0u)
emilmont 1:fdd22bb7aa52 97 {
emilmont 1:fdd22bb7aa52 98 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 99 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 100 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 101 {
emilmont 1:fdd22bb7aa52 102 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 103 /* Read 4 inputs */
emilmont 1:fdd22bb7aa52 104 in1 = *pSrc;
emilmont 1:fdd22bb7aa52 105 in2 = *(pSrc + 1);
emilmont 1:fdd22bb7aa52 106 in3 = *(pSrc + 2);
emilmont 1:fdd22bb7aa52 107 in4 = *(pSrc + 3);
emilmont 1:fdd22bb7aa52 108
emilmont 1:fdd22bb7aa52 109 /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
emilmont 1:fdd22bb7aa52 110 *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8),
emilmont 1:fdd22bb7aa52 111 __SSAT((in2 << shiftBits), 8),
emilmont 1:fdd22bb7aa52 112 __SSAT((in3 << shiftBits), 8),
emilmont 1:fdd22bb7aa52 113 __SSAT((in4 << shiftBits), 8));
emilmont 1:fdd22bb7aa52 114 /* Update source pointer to process next sampels */
emilmont 1:fdd22bb7aa52 115 pSrc += 4u;
emilmont 1:fdd22bb7aa52 116
emilmont 1:fdd22bb7aa52 117 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 118 blkCnt--;
emilmont 1:fdd22bb7aa52 119 }
emilmont 1:fdd22bb7aa52 120
emilmont 1:fdd22bb7aa52 121 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 122 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 123 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 124
emilmont 1:fdd22bb7aa52 125 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 126 {
emilmont 1:fdd22bb7aa52 127 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 128 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 129 *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8);
emilmont 1:fdd22bb7aa52 130
emilmont 1:fdd22bb7aa52 131 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 132 blkCnt--;
emilmont 1:fdd22bb7aa52 133 }
emilmont 1:fdd22bb7aa52 134 }
emilmont 1:fdd22bb7aa52 135 else
emilmont 1:fdd22bb7aa52 136 {
emilmont 1:fdd22bb7aa52 137 shiftBits = -shiftBits;
emilmont 1:fdd22bb7aa52 138 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 139 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 140 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 141 {
emilmont 1:fdd22bb7aa52 142 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 143 /* Read 4 inputs */
emilmont 1:fdd22bb7aa52 144 in1 = *pSrc;
emilmont 1:fdd22bb7aa52 145 in2 = *(pSrc + 1);
emilmont 1:fdd22bb7aa52 146 in3 = *(pSrc + 2);
emilmont 1:fdd22bb7aa52 147 in4 = *(pSrc + 3);
emilmont 1:fdd22bb7aa52 148
emilmont 1:fdd22bb7aa52 149 /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */
emilmont 1:fdd22bb7aa52 150 *__SIMD32(pDst)++ = __PACKq7((in1 >> shiftBits), (in2 >> shiftBits),
emilmont 1:fdd22bb7aa52 151 (in3 >> shiftBits), (in4 >> shiftBits));
emilmont 1:fdd22bb7aa52 152
emilmont 1:fdd22bb7aa52 153
emilmont 1:fdd22bb7aa52 154 pSrc += 4u;
emilmont 1:fdd22bb7aa52 155
emilmont 1:fdd22bb7aa52 156 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 157 blkCnt--;
emilmont 1:fdd22bb7aa52 158 }
emilmont 1:fdd22bb7aa52 159
emilmont 1:fdd22bb7aa52 160 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 161 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 162 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 163
emilmont 1:fdd22bb7aa52 164 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 165 {
emilmont 1:fdd22bb7aa52 166 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 167 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 168 in1 = *pSrc++;
emilmont 1:fdd22bb7aa52 169 *pDst++ = (in1 >> shiftBits);
emilmont 1:fdd22bb7aa52 170
emilmont 1:fdd22bb7aa52 171 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 172 blkCnt--;
emilmont 1:fdd22bb7aa52 173 }
emilmont 1:fdd22bb7aa52 174 }
emilmont 1:fdd22bb7aa52 175
emilmont 1:fdd22bb7aa52 176 #else
emilmont 1:fdd22bb7aa52 177
emilmont 1:fdd22bb7aa52 178 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 179
emilmont 1:fdd22bb7aa52 180 /* Getting the sign of shiftBits */
emilmont 1:fdd22bb7aa52 181 sign = (shiftBits & 0x80);
emilmont 1:fdd22bb7aa52 182
emilmont 1:fdd22bb7aa52 183 /* If the shift value is positive then do right shift else left shift */
emilmont 1:fdd22bb7aa52 184 if(sign == 0u)
emilmont 1:fdd22bb7aa52 185 {
emilmont 1:fdd22bb7aa52 186 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 187 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 188
emilmont 1:fdd22bb7aa52 189 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 190 {
emilmont 1:fdd22bb7aa52 191 /* C = A << shiftBits */
emilmont 1:fdd22bb7aa52 192 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 193 *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8);
emilmont 1:fdd22bb7aa52 194
emilmont 1:fdd22bb7aa52 195 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 196 blkCnt--;
emilmont 1:fdd22bb7aa52 197 }
emilmont 1:fdd22bb7aa52 198 }
emilmont 1:fdd22bb7aa52 199 else
emilmont 1:fdd22bb7aa52 200 {
emilmont 1:fdd22bb7aa52 201 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 202 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 203
emilmont 1:fdd22bb7aa52 204 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 205 {
emilmont 1:fdd22bb7aa52 206 /* C = A >> shiftBits */
emilmont 1:fdd22bb7aa52 207 /* Shift the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 208 *pDst++ = (*pSrc++ >> -shiftBits);
emilmont 1:fdd22bb7aa52 209
emilmont 1:fdd22bb7aa52 210 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 211 blkCnt--;
emilmont 1:fdd22bb7aa52 212 }
emilmont 1:fdd22bb7aa52 213 }
emilmont 1:fdd22bb7aa52 214
mbed_official 3:7a284390b0ce 215 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 216 }
emilmont 1:fdd22bb7aa52 217
emilmont 1:fdd22bb7aa52 218 /**
emilmont 1:fdd22bb7aa52 219 * @} end of shift group
emilmont 1:fdd22bb7aa52 220 */