Lars Knudsen / USBDevice_WebUSB

This fork re-enables FRDM boards and adds WebUSB CDC functionality

Fork of USBDevice_STM32F103 by Devan Lai

USBDevice/USBHAL_KL25Z.cpp@72:1d8a6665d607, 2017-07-11 (annotated)

Committer:
Lars Knudsen
Date:
Tue Jul 11 21:02:39 2017 +0200
Revision:
72:1d8a6665d607
Parent:
71:4e9a69384cac 
Adding MS OS 2.0 support

Who changed what in which revision?

UserRevisionLine numberNew contents of line
larsgk 71:4e9a69384cac 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
larsgk 71:4e9a69384cac 2 *
larsgk 71:4e9a69384cac 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
larsgk 71:4e9a69384cac 4 * and associated documentation files (the "Software"), to deal in the Software without
larsgk 71:4e9a69384cac 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
larsgk 71:4e9a69384cac 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
larsgk 71:4e9a69384cac 7 * Software is furnished to do so, subject to the following conditions:
larsgk 71:4e9a69384cac 8 *
larsgk 71:4e9a69384cac 9 * The above copyright notice and this permission notice shall be included in all copies or
larsgk 71:4e9a69384cac 10 * substantial portions of the Software.
larsgk 71:4e9a69384cac 11 *
larsgk 71:4e9a69384cac 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
larsgk 71:4e9a69384cac 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
larsgk 71:4e9a69384cac 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
larsgk 71:4e9a69384cac 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
larsgk 71:4e9a69384cac 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
larsgk 71:4e9a69384cac 17 */
larsgk 71:4e9a69384cac 18
larsgk 71:4e9a69384cac 19 #if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
larsgk 71:4e9a69384cac 20
larsgk 71:4e9a69384cac 21 #include "USBHAL.h"
larsgk 71:4e9a69384cac 22
larsgk 71:4e9a69384cac 23 USBHAL * USBHAL::instance;
larsgk 71:4e9a69384cac 24
larsgk 71:4e9a69384cac 25 static volatile int epComplete = 0;
larsgk 71:4e9a69384cac 26
larsgk 71:4e9a69384cac 27 // Convert physical endpoint number to register bit
larsgk 71:4e9a69384cac 28 #define EP(endpoint) (1<<(endpoint))
larsgk 71:4e9a69384cac 29
larsgk 71:4e9a69384cac 30 // Convert physical to logical
larsgk 71:4e9a69384cac 31 #define PHY_TO_LOG(endpoint) ((endpoint)>>1)
larsgk 71:4e9a69384cac 32
larsgk 71:4e9a69384cac 33 // Get endpoint direction
larsgk 71:4e9a69384cac 34 #define IN_EP(endpoint) ((endpoint) & 1U ? true : false)
larsgk 71:4e9a69384cac 35 #define OUT_EP(endpoint) ((endpoint) & 1U ? false : true)
larsgk 71:4e9a69384cac 36
larsgk 71:4e9a69384cac 37 #define BD_OWN_MASK (1<<7)
larsgk 71:4e9a69384cac 38 #define BD_DATA01_MASK (1<<6)
larsgk 71:4e9a69384cac 39 #define BD_KEEP_MASK (1<<5)
larsgk 71:4e9a69384cac 40 #define BD_NINC_MASK (1<<4)
larsgk 71:4e9a69384cac 41 #define BD_DTS_MASK (1<<3)
larsgk 71:4e9a69384cac 42 #define BD_STALL_MASK (1<<2)
larsgk 71:4e9a69384cac 43
larsgk 71:4e9a69384cac 44 #define TX 1
larsgk 71:4e9a69384cac 45 #define RX 0
larsgk 71:4e9a69384cac 46 #define ODD 0
larsgk 71:4e9a69384cac 47 #define EVEN 1
larsgk 71:4e9a69384cac 48 // this macro waits a physical endpoint number
larsgk 71:4e9a69384cac 49 #define EP_BDT_IDX(ep, dir, odd) (((ep * 4) + (2 * dir) + (1 * odd)))
larsgk 71:4e9a69384cac 50
larsgk 71:4e9a69384cac 51 #define SETUP_TOKEN 0x0D
larsgk 71:4e9a69384cac 52 #define IN_TOKEN 0x09
larsgk 71:4e9a69384cac 53 #define OUT_TOKEN 0x01
larsgk 71:4e9a69384cac 54 #define TOK_PID(idx) ((bdt[idx].info >> 2) & 0x0F)
larsgk 71:4e9a69384cac 55
larsgk 71:4e9a69384cac 56 // for each endpt: 8 bytes
larsgk 71:4e9a69384cac 57 typedef struct BDT {
larsgk 71:4e9a69384cac 58 uint8_t info; // BD[0:7]
larsgk 71:4e9a69384cac 59 uint8_t dummy; // RSVD: BD[8:15]
larsgk 71:4e9a69384cac 60 uint16_t byte_count; // BD[16:32]
larsgk 71:4e9a69384cac 61 uint32_t address; // Addr
larsgk 71:4e9a69384cac 62 } BDT;
larsgk 71:4e9a69384cac 63
larsgk 71:4e9a69384cac 64
larsgk 71:4e9a69384cac 65 // there are:
larsgk 71:4e9a69384cac 66 // * 16 bidirectionnal endpt -> 32 physical endpt
larsgk 71:4e9a69384cac 67 // * as there are ODD and EVEN buffer -> 32*2 bdt
larsgk 71:4e9a69384cac 68 __attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
larsgk 71:4e9a69384cac 69 uint8_t * endpoint_buffer[(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2];
larsgk 71:4e9a69384cac 70 uint8_t * endpoint_buffer_iso[2*2];
larsgk 71:4e9a69384cac 71
larsgk 71:4e9a69384cac 72 static uint8_t set_addr = 0;
larsgk 71:4e9a69384cac 73 static uint8_t addr = 0;
larsgk 71:4e9a69384cac 74
larsgk 71:4e9a69384cac 75 static uint32_t Data1 = 0x55555555;
larsgk 71:4e9a69384cac 76
larsgk 71:4e9a69384cac 77 static uint32_t frameNumber() {
larsgk 71:4e9a69384cac 78 return((USB0->FRMNUML | (USB0->FRMNUMH << 8)) & 0x07FF);
larsgk 71:4e9a69384cac 79 }
larsgk 71:4e9a69384cac 80
larsgk 71:4e9a69384cac 81 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
larsgk 71:4e9a69384cac 82 return 0;
larsgk 71:4e9a69384cac 83 }
larsgk 71:4e9a69384cac 84
larsgk 71:4e9a69384cac 85 USBHAL::USBHAL(void) {
larsgk 71:4e9a69384cac 86 // Disable IRQ
larsgk 71:4e9a69384cac 87 NVIC_DisableIRQ(USB0_IRQn);
larsgk 71:4e9a69384cac 88
larsgk 71:4e9a69384cac 89 #if defined(TARGET_K64F)
larsgk 71:4e9a69384cac 90 MPU->CESR=0;
larsgk 71:4e9a69384cac 91 #endif
larsgk 71:4e9a69384cac 92 // fill in callback array
larsgk 71:4e9a69384cac 93 epCallback[0] = &USBHAL::EP1_OUT_callback;
larsgk 71:4e9a69384cac 94 epCallback[1] = &USBHAL::EP1_IN_callback;
larsgk 71:4e9a69384cac 95 epCallback[2] = &USBHAL::EP2_OUT_callback;
larsgk 71:4e9a69384cac 96 epCallback[3] = &USBHAL::EP2_IN_callback;
larsgk 71:4e9a69384cac 97 epCallback[4] = &USBHAL::EP3_OUT_callback;
larsgk 71:4e9a69384cac 98 epCallback[5] = &USBHAL::EP3_IN_callback;
larsgk 71:4e9a69384cac 99 epCallback[6] = &USBHAL::EP4_OUT_callback;
larsgk 71:4e9a69384cac 100 epCallback[7] = &USBHAL::EP4_IN_callback;
larsgk 71:4e9a69384cac 101 epCallback[8] = &USBHAL::EP5_OUT_callback;
larsgk 71:4e9a69384cac 102 epCallback[9] = &USBHAL::EP5_IN_callback;
larsgk 71:4e9a69384cac 103 epCallback[10] = &USBHAL::EP6_OUT_callback;
larsgk 71:4e9a69384cac 104 epCallback[11] = &USBHAL::EP6_IN_callback;
larsgk 71:4e9a69384cac 105 epCallback[12] = &USBHAL::EP7_OUT_callback;
larsgk 71:4e9a69384cac 106 epCallback[13] = &USBHAL::EP7_IN_callback;
larsgk 71:4e9a69384cac 107 epCallback[14] = &USBHAL::EP8_OUT_callback;
larsgk 71:4e9a69384cac 108 epCallback[15] = &USBHAL::EP8_IN_callback;
larsgk 71:4e9a69384cac 109 epCallback[16] = &USBHAL::EP9_OUT_callback;
larsgk 71:4e9a69384cac 110 epCallback[17] = &USBHAL::EP9_IN_callback;
larsgk 71:4e9a69384cac 111 epCallback[18] = &USBHAL::EP10_OUT_callback;
larsgk 71:4e9a69384cac 112 epCallback[19] = &USBHAL::EP10_IN_callback;
larsgk 71:4e9a69384cac 113 epCallback[20] = &USBHAL::EP11_OUT_callback;
larsgk 71:4e9a69384cac 114 epCallback[21] = &USBHAL::EP11_IN_callback;
larsgk 71:4e9a69384cac 115 epCallback[22] = &USBHAL::EP12_OUT_callback;
larsgk 71:4e9a69384cac 116 epCallback[23] = &USBHAL::EP12_IN_callback;
larsgk 71:4e9a69384cac 117 epCallback[24] = &USBHAL::EP13_OUT_callback;
larsgk 71:4e9a69384cac 118 epCallback[25] = &USBHAL::EP13_IN_callback;
larsgk 71:4e9a69384cac 119 epCallback[26] = &USBHAL::EP14_OUT_callback;
larsgk 71:4e9a69384cac 120 epCallback[27] = &USBHAL::EP14_IN_callback;
larsgk 71:4e9a69384cac 121 epCallback[28] = &USBHAL::EP15_OUT_callback;
larsgk 71:4e9a69384cac 122 epCallback[29] = &USBHAL::EP15_IN_callback;
larsgk 71:4e9a69384cac 123
larsgk 71:4e9a69384cac 124 #if defined(TARGET_KL43Z)
larsgk 71:4e9a69384cac 125 // enable USBFS clock
larsgk 71:4e9a69384cac 126 SIM->SCGC4 |= SIM_SCGC4_USBFS_MASK;
larsgk 71:4e9a69384cac 127
larsgk 71:4e9a69384cac 128 // enable the IRC48M clock
larsgk 71:4e9a69384cac 129 USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;
larsgk 71:4e9a69384cac 130
larsgk 71:4e9a69384cac 131 // enable the USB clock recovery tuning
larsgk 71:4e9a69384cac 132 USB0->CLK_RECOVER_CTRL |= USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK;
larsgk 71:4e9a69384cac 133
larsgk 71:4e9a69384cac 134 // choose usb src clock
larsgk 71:4e9a69384cac 135 SIM->SOPT2 |= SIM_SOPT2_USBSRC_MASK;
larsgk 71:4e9a69384cac 136 #else
larsgk 71:4e9a69384cac 137 // choose usb src as PLL
larsgk 71:4e9a69384cac 138 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK;
larsgk 71:4e9a69384cac 139 SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | (1 << SIM_SOPT2_PLLFLLSEL_SHIFT));
larsgk 71:4e9a69384cac 140
larsgk 71:4e9a69384cac 141 // enable OTG clock
larsgk 71:4e9a69384cac 142 SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;
larsgk 71:4e9a69384cac 143 #endif
larsgk 71:4e9a69384cac 144
larsgk 71:4e9a69384cac 145 // Attach IRQ
larsgk 71:4e9a69384cac 146 instance = this;
larsgk 71:4e9a69384cac 147 NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
larsgk 71:4e9a69384cac 148 NVIC_EnableIRQ(USB0_IRQn);
larsgk 71:4e9a69384cac 149
larsgk 71:4e9a69384cac 150 // USB Module Configuration
larsgk 71:4e9a69384cac 151 // Reset USB Module
larsgk 71:4e9a69384cac 152 USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
larsgk 71:4e9a69384cac 153 while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);
larsgk 71:4e9a69384cac 154
larsgk 71:4e9a69384cac 155 // Set BDT Base Register
larsgk 71:4e9a69384cac 156 USB0->BDTPAGE1 = (uint8_t)((uint32_t)bdt>>8);
larsgk 71:4e9a69384cac 157 USB0->BDTPAGE2 = (uint8_t)((uint32_t)bdt>>16);
larsgk 71:4e9a69384cac 158 USB0->BDTPAGE3 = (uint8_t)((uint32_t)bdt>>24);
larsgk 71:4e9a69384cac 159
larsgk 71:4e9a69384cac 160 // Clear interrupt flag
larsgk 71:4e9a69384cac 161 USB0->ISTAT = 0xff;
larsgk 71:4e9a69384cac 162
larsgk 71:4e9a69384cac 163 // USB Interrupt Enablers
larsgk 71:4e9a69384cac 164 USB0->INTEN |= USB_INTEN_TOKDNEEN_MASK |
larsgk 71:4e9a69384cac 165 USB_INTEN_SOFTOKEN_MASK |
larsgk 71:4e9a69384cac 166 USB_INTEN_ERROREN_MASK |
larsgk 71:4e9a69384cac 167 USB_INTEN_USBRSTEN_MASK;
larsgk 71:4e9a69384cac 168
larsgk 71:4e9a69384cac 169 // Disable weak pull downs
larsgk 71:4e9a69384cac 170 USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
larsgk 71:4e9a69384cac 171
larsgk 71:4e9a69384cac 172 USB0->USBTRC0 |= 0x40;
larsgk 71:4e9a69384cac 173 }
larsgk 71:4e9a69384cac 174
larsgk 71:4e9a69384cac 175 USBHAL::~USBHAL(void) { }
larsgk 71:4e9a69384cac 176
larsgk 71:4e9a69384cac 177 void USBHAL::connect(void) {
larsgk 71:4e9a69384cac 178 // enable USB
larsgk 71:4e9a69384cac 179 USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
larsgk 71:4e9a69384cac 180 // Pull up enable
larsgk 71:4e9a69384cac 181 USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
larsgk 71:4e9a69384cac 182 }
larsgk 71:4e9a69384cac 183
larsgk 71:4e9a69384cac 184 void USBHAL::disconnect(void) {
larsgk 71:4e9a69384cac 185 // disable USB
larsgk 71:4e9a69384cac 186 USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;
larsgk 71:4e9a69384cac 187 // Pull up disable
larsgk 71:4e9a69384cac 188 USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;
larsgk 71:4e9a69384cac 189
larsgk 71:4e9a69384cac 190 //Free buffers if required:
larsgk 71:4e9a69384cac 191 for (int i = 0; i<(NUMBER_OF_PHYSICAL_ENDPOINTS - 2) * 2; i++) {
larsgk 71:4e9a69384cac 192 free(endpoint_buffer[i]);
larsgk 71:4e9a69384cac 193 endpoint_buffer[i] = NULL;
larsgk 71:4e9a69384cac 194 }
larsgk 71:4e9a69384cac 195 free(endpoint_buffer_iso[2]);
larsgk 71:4e9a69384cac 196 endpoint_buffer_iso[2] = NULL;
larsgk 71:4e9a69384cac 197 free(endpoint_buffer_iso[0]);
larsgk 71:4e9a69384cac 198 endpoint_buffer_iso[0] = NULL;
larsgk 71:4e9a69384cac 199 }
larsgk 71:4e9a69384cac 200
larsgk 71:4e9a69384cac 201 void USBHAL::configureDevice(void) {
larsgk 71:4e9a69384cac 202 // not needed
larsgk 71:4e9a69384cac 203 }
larsgk 71:4e9a69384cac 204
larsgk 71:4e9a69384cac 205 void USBHAL::unconfigureDevice(void) {
larsgk 71:4e9a69384cac 206 // not needed
larsgk 71:4e9a69384cac 207 }
larsgk 71:4e9a69384cac 208
larsgk 71:4e9a69384cac 209 void USBHAL::setAddress(uint8_t address) {
larsgk 71:4e9a69384cac 210 // we don't set the address now otherwise the usb controller does not ack
larsgk 71:4e9a69384cac 211 // we set a flag instead
larsgk 71:4e9a69384cac 212 // see usbisr when an IN token is received
larsgk 71:4e9a69384cac 213 set_addr = 1;
larsgk 71:4e9a69384cac 214 addr = address;
larsgk 71:4e9a69384cac 215 }
larsgk 71:4e9a69384cac 216
larsgk 71:4e9a69384cac 217 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
larsgk 71:4e9a69384cac 218 uint32_t handshake_flag = 0;
larsgk 71:4e9a69384cac 219 uint8_t * buf;
larsgk 71:4e9a69384cac 220
larsgk 71:4e9a69384cac 221 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
larsgk 71:4e9a69384cac 222 return false;
larsgk 71:4e9a69384cac 223 }
larsgk 71:4e9a69384cac 224
larsgk 71:4e9a69384cac 225 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
larsgk 71:4e9a69384cac 226
larsgk 71:4e9a69384cac 227 if ((flags & ISOCHRONOUS) == 0) {
larsgk 71:4e9a69384cac 228 handshake_flag = USB_ENDPT_EPHSHK_MASK;
larsgk 71:4e9a69384cac 229 if (IN_EP(endpoint)) {
larsgk 71:4e9a69384cac 230 if (endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] == NULL)
larsgk 71:4e9a69384cac 231 endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)] = (uint8_t *) malloc (64);
larsgk 71:4e9a69384cac 232 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, TX, ODD)][0];
larsgk 71:4e9a69384cac 233 } else {
larsgk 71:4e9a69384cac 234 if (endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] == NULL)
larsgk 71:4e9a69384cac 235 endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)] = (uint8_t *) malloc (64);
larsgk 71:4e9a69384cac 236 buf = &endpoint_buffer[EP_BDT_IDX(log_endpoint, RX, ODD)][0];
larsgk 71:4e9a69384cac 237 }
larsgk 71:4e9a69384cac 238 } else {
larsgk 71:4e9a69384cac 239 if (IN_EP(endpoint)) {
larsgk 71:4e9a69384cac 240 if (endpoint_buffer_iso[2] == NULL)
larsgk 71:4e9a69384cac 241 endpoint_buffer_iso[2] = (uint8_t *) malloc (1023);
larsgk 71:4e9a69384cac 242 buf = &endpoint_buffer_iso[2][0];
larsgk 71:4e9a69384cac 243 } else {
larsgk 71:4e9a69384cac 244 if (endpoint_buffer_iso[0] == NULL)
larsgk 71:4e9a69384cac 245 endpoint_buffer_iso[0] = (uint8_t *) malloc (1023);
larsgk 71:4e9a69384cac 246 buf = &endpoint_buffer_iso[0][0];
larsgk 71:4e9a69384cac 247 }
larsgk 71:4e9a69384cac 248 }
larsgk 71:4e9a69384cac 249
larsgk 71:4e9a69384cac 250 // IN endpt -> device to host (TX)
larsgk 71:4e9a69384cac 251 if (IN_EP(endpoint)) {
larsgk 71:4e9a69384cac 252 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
larsgk 71:4e9a69384cac 253 USB_ENDPT_EPTXEN_MASK; // en TX (IN) tran
larsgk 71:4e9a69384cac 254 bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = (uint32_t) buf;
larsgk 71:4e9a69384cac 255 bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = 0;
larsgk 71:4e9a69384cac 256 }
larsgk 71:4e9a69384cac 257 // OUT endpt -> host to device (RX)
larsgk 71:4e9a69384cac 258 else {
larsgk 71:4e9a69384cac 259 USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag | // ep handshaking (not if iso endpoint)
larsgk 71:4e9a69384cac 260 USB_ENDPT_EPRXEN_MASK; // en RX (OUT) tran.
larsgk 71:4e9a69384cac 261 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].byte_count = maxPacket;
larsgk 71:4e9a69384cac 262 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address = (uint32_t) buf;
larsgk 71:4e9a69384cac 263 bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info = BD_OWN_MASK | BD_DTS_MASK;
larsgk 71:4e9a69384cac 264 bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info = 0;
larsgk 71:4e9a69384cac 265 }
larsgk 71:4e9a69384cac 266
larsgk 71:4e9a69384cac 267 Data1 |= (1 << endpoint);
larsgk 71:4e9a69384cac 268
larsgk 71:4e9a69384cac 269 return true;
larsgk 71:4e9a69384cac 270 }
larsgk 71:4e9a69384cac 271
larsgk 71:4e9a69384cac 272 // read setup packet
larsgk 71:4e9a69384cac 273 void USBHAL::EP0setup(uint8_t *buffer) {
larsgk 71:4e9a69384cac 274 uint32_t sz;
larsgk 71:4e9a69384cac 275 endpointReadResult(EP0OUT, buffer, &sz);
larsgk 71:4e9a69384cac 276 }
larsgk 71:4e9a69384cac 277
larsgk 71:4e9a69384cac 278 void USBHAL::EP0readStage(void) {
larsgk 71:4e9a69384cac 279 Data1 &= ~1UL; // set DATA0
larsgk 71:4e9a69384cac 280 bdt[0].info = (BD_DTS_MASK | BD_OWN_MASK);
larsgk 71:4e9a69384cac 281 }
larsgk 71:4e9a69384cac 282
larsgk 71:4e9a69384cac 283 void USBHAL::EP0read(void) {
larsgk 71:4e9a69384cac 284 uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
larsgk 71:4e9a69384cac 285 bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
larsgk 71:4e9a69384cac 286 }
larsgk 71:4e9a69384cac 287
larsgk 71:4e9a69384cac 288 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
larsgk 71:4e9a69384cac 289 uint32_t sz;
larsgk 71:4e9a69384cac 290 endpointReadResult(EP0OUT, buffer, &sz);
larsgk 71:4e9a69384cac 291 return sz;
larsgk 71:4e9a69384cac 292 }
larsgk 71:4e9a69384cac 293
larsgk 71:4e9a69384cac 294 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
larsgk 71:4e9a69384cac 295 endpointWrite(EP0IN, buffer, size);
larsgk 71:4e9a69384cac 296 }
larsgk 71:4e9a69384cac 297
larsgk 71:4e9a69384cac 298 void USBHAL::EP0getWriteResult(void) {
larsgk 71:4e9a69384cac 299 }
larsgk 71:4e9a69384cac 300
larsgk 71:4e9a69384cac 301 void USBHAL::EP0stall(void) {
larsgk 71:4e9a69384cac 302 stallEndpoint(EP0OUT);
larsgk 71:4e9a69384cac 303 }
larsgk 71:4e9a69384cac 304
larsgk 71:4e9a69384cac 305 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
larsgk 71:4e9a69384cac 306 endpoint = PHY_TO_LOG(endpoint);
larsgk 71:4e9a69384cac 307 uint32_t idx = EP_BDT_IDX(endpoint, RX, 0);
larsgk 71:4e9a69384cac 308 bdt[idx].byte_count = maximumSize;
larsgk 71:4e9a69384cac 309 return EP_PENDING;
larsgk 71:4e9a69384cac 310 }
larsgk 71:4e9a69384cac 311
larsgk 71:4e9a69384cac 312 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
larsgk 71:4e9a69384cac 313 uint32_t n, sz, idx, setup = 0;
larsgk 71:4e9a69384cac 314 uint8_t not_iso;
larsgk 71:4e9a69384cac 315 uint8_t * ep_buf;
larsgk 71:4e9a69384cac 316
larsgk 71:4e9a69384cac 317 uint32_t log_endpoint = PHY_TO_LOG(endpoint);
larsgk 71:4e9a69384cac 318
larsgk 71:4e9a69384cac 319 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
larsgk 71:4e9a69384cac 320 return EP_INVALID;
larsgk 71:4e9a69384cac 321 }
larsgk 71:4e9a69384cac 322
larsgk 71:4e9a69384cac 323 // if read on a IN endpoint -> error
larsgk 71:4e9a69384cac 324 if (IN_EP(endpoint)) {
larsgk 71:4e9a69384cac 325 return EP_INVALID;
larsgk 71:4e9a69384cac 326 }
larsgk 71:4e9a69384cac 327
larsgk 71:4e9a69384cac 328 idx = EP_BDT_IDX(log_endpoint, RX, 0);
larsgk 71:4e9a69384cac 329 sz = bdt[idx].byte_count;
larsgk 71:4e9a69384cac 330 not_iso = USB0->ENDPOINT[log_endpoint].ENDPT & USB_ENDPT_EPHSHK_MASK;
larsgk 71:4e9a69384cac 331
larsgk 71:4e9a69384cac 332 //for isochronous endpoint, we don't wait an interrupt
larsgk 71:4e9a69384cac 333 if ((log_endpoint != 0) && not_iso && !(epComplete & EP(endpoint))) {
larsgk 71:4e9a69384cac 334 return EP_PENDING;
larsgk 71:4e9a69384cac 335 }
larsgk 71:4e9a69384cac 336
larsgk 71:4e9a69384cac 337 if ((log_endpoint == 0) && (TOK_PID(idx) == SETUP_TOKEN)) {
larsgk 71:4e9a69384cac 338 setup = 1;
larsgk 71:4e9a69384cac 339 }
larsgk 71:4e9a69384cac 340
larsgk 71:4e9a69384cac 341 // non iso endpoint
larsgk 71:4e9a69384cac 342 if (not_iso) {
larsgk 71:4e9a69384cac 343 ep_buf = endpoint_buffer[idx];
larsgk 71:4e9a69384cac 344 } else {
larsgk 71:4e9a69384cac 345 ep_buf = endpoint_buffer_iso[0];
larsgk 71:4e9a69384cac 346 }
larsgk 71:4e9a69384cac 347
larsgk 71:4e9a69384cac 348 for (n = 0; n < sz; n++) {
larsgk 71:4e9a69384cac 349 buffer[n] = ep_buf[n];
larsgk 71:4e9a69384cac 350 }
larsgk 71:4e9a69384cac 351
larsgk 71:4e9a69384cac 352 if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
larsgk 71:4e9a69384cac 353 if (setup && (buffer[6] == 0)) // if no setup data stage,
larsgk 71:4e9a69384cac 354 Data1 &= ~1UL; // set DATA0
larsgk 71:4e9a69384cac 355 else
larsgk 71:4e9a69384cac 356 Data1 ^= (1 << endpoint);
larsgk 71:4e9a69384cac 357 }
larsgk 71:4e9a69384cac 358
larsgk 71:4e9a69384cac 359 if (((Data1 >> endpoint) & 1)) {
larsgk 71:4e9a69384cac 360 bdt[idx].info = BD_DTS_MASK | BD_DATA01_MASK | BD_OWN_MASK;
larsgk 71:4e9a69384cac 361 }
larsgk 71:4e9a69384cac 362 else {
larsgk 71:4e9a69384cac 363 bdt[idx].info = BD_DTS_MASK | BD_OWN_MASK;
larsgk 71:4e9a69384cac 364 }
larsgk 71:4e9a69384cac 365
larsgk 71:4e9a69384cac 366 USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
larsgk 71:4e9a69384cac 367 *bytesRead = sz;
larsgk 71:4e9a69384cac 368
larsgk 71:4e9a69384cac 369 epComplete &= ~EP(endpoint);
larsgk 71:4e9a69384cac 370 return EP_COMPLETED;
larsgk 71:4e9a69384cac 371 }
larsgk 71:4e9a69384cac 372
larsgk 71:4e9a69384cac 373 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
larsgk 71:4e9a69384cac 374 uint32_t idx, n;
larsgk 71:4e9a69384cac 375 uint8_t * ep_buf;
larsgk 71:4e9a69384cac 376
larsgk 71:4e9a69384cac 377 if (endpoint > NUMBER_OF_PHYSICAL_ENDPOINTS - 1) {
larsgk 71:4e9a69384cac 378 return EP_INVALID;
larsgk 71:4e9a69384cac 379 }
larsgk 71:4e9a69384cac 380
larsgk 71:4e9a69384cac 381 // if write on a OUT endpoint -> error
larsgk 71:4e9a69384cac 382 if (OUT_EP(endpoint)) {
larsgk 71:4e9a69384cac 383 return EP_INVALID;
larsgk 71:4e9a69384cac 384 }
larsgk 71:4e9a69384cac 385
larsgk 71:4e9a69384cac 386 idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);
larsgk 71:4e9a69384cac 387 bdt[idx].byte_count = size;
larsgk 71:4e9a69384cac 388
larsgk 71:4e9a69384cac 389
larsgk 71:4e9a69384cac 390 // non iso endpoint
larsgk 71:4e9a69384cac 391 if (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPHSHK_MASK) {
larsgk 71:4e9a69384cac 392 ep_buf = endpoint_buffer[idx];
larsgk 71:4e9a69384cac 393 } else {
larsgk 71:4e9a69384cac 394 ep_buf = endpoint_buffer_iso[2];
larsgk 71:4e9a69384cac 395 }
larsgk 71:4e9a69384cac 396
larsgk 71:4e9a69384cac 397 for (n = 0; n < size; n++) {
larsgk 71:4e9a69384cac 398 ep_buf[n] = data[n];
larsgk 71:4e9a69384cac 399 }
larsgk 71:4e9a69384cac 400
larsgk 71:4e9a69384cac 401 if ((Data1 >> endpoint) & 1) {
larsgk 71:4e9a69384cac 402 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
larsgk 71:4e9a69384cac 403 } else {
larsgk 71:4e9a69384cac 404 bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | BD_DATA01_MASK;
larsgk 71:4e9a69384cac 405 }
larsgk 71:4e9a69384cac 406
larsgk 71:4e9a69384cac 407 Data1 ^= (1 << endpoint);
larsgk 71:4e9a69384cac 408
larsgk 71:4e9a69384cac 409 return EP_PENDING;
larsgk 71:4e9a69384cac 410 }
larsgk 71:4e9a69384cac 411
larsgk 71:4e9a69384cac 412 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
larsgk 71:4e9a69384cac 413 if (epComplete & EP(endpoint)) {
larsgk 71:4e9a69384cac 414 epComplete &= ~EP(endpoint);
larsgk 71:4e9a69384cac 415 return EP_COMPLETED;
larsgk 71:4e9a69384cac 416 }
larsgk 71:4e9a69384cac 417
larsgk 71:4e9a69384cac 418 return EP_PENDING;
larsgk 71:4e9a69384cac 419 }
larsgk 71:4e9a69384cac 420
larsgk 71:4e9a69384cac 421 void USBHAL::stallEndpoint(uint8_t endpoint) {
larsgk 71:4e9a69384cac 422 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
larsgk 71:4e9a69384cac 423 }
larsgk 71:4e9a69384cac 424
larsgk 71:4e9a69384cac 425 void USBHAL::unstallEndpoint(uint8_t endpoint) {
larsgk 71:4e9a69384cac 426 USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
larsgk 71:4e9a69384cac 427 }
larsgk 71:4e9a69384cac 428
larsgk 71:4e9a69384cac 429 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
larsgk 71:4e9a69384cac 430 uint8_t stall = (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK);
larsgk 71:4e9a69384cac 431 return (stall) ? true : false;
larsgk 71:4e9a69384cac 432 }
larsgk 71:4e9a69384cac 433
larsgk 71:4e9a69384cac 434 void USBHAL::remoteWakeup(void) {
larsgk 71:4e9a69384cac 435 // [TODO]
larsgk 71:4e9a69384cac 436 }
larsgk 71:4e9a69384cac 437
larsgk 71:4e9a69384cac 438
larsgk 71:4e9a69384cac 439 void USBHAL::_usbisr(void) {
larsgk 71:4e9a69384cac 440 instance->usbisr();
larsgk 71:4e9a69384cac 441 }
larsgk 71:4e9a69384cac 442
larsgk 71:4e9a69384cac 443
larsgk 71:4e9a69384cac 444 void USBHAL::usbisr(void) {
larsgk 71:4e9a69384cac 445 uint8_t i;
larsgk 71:4e9a69384cac 446 uint8_t istat = USB0->ISTAT;
larsgk 71:4e9a69384cac 447
larsgk 71:4e9a69384cac 448 // reset interrupt
larsgk 71:4e9a69384cac 449 if (istat & USB_ISTAT_USBRST_MASK) {
larsgk 71:4e9a69384cac 450 // disable all endpt
larsgk 71:4e9a69384cac 451 for(i = 0; i < 16; i++) {
larsgk 71:4e9a69384cac 452 USB0->ENDPOINT[i].ENDPT = 0x00;
larsgk 71:4e9a69384cac 453 }
larsgk 71:4e9a69384cac 454
larsgk 71:4e9a69384cac 455 // enable control endpoint
larsgk 71:4e9a69384cac 456 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
larsgk 71:4e9a69384cac 457 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
larsgk 71:4e9a69384cac 458
larsgk 71:4e9a69384cac 459 Data1 = 0x55555555;
larsgk 71:4e9a69384cac 460 USB0->CTL |= USB_CTL_ODDRST_MASK;
larsgk 71:4e9a69384cac 461
larsgk 71:4e9a69384cac 462 USB0->ISTAT = 0xFF; // clear all interrupt status flags
larsgk 71:4e9a69384cac 463 USB0->ERRSTAT = 0xFF; // clear all error flags
larsgk 71:4e9a69384cac 464 USB0->ERREN = 0xFF; // enable error interrupt sources
larsgk 71:4e9a69384cac 465 USB0->ADDR = 0x00; // set default address
larsgk 71:4e9a69384cac 466
larsgk 71:4e9a69384cac 467 return;
larsgk 71:4e9a69384cac 468 }
larsgk 71:4e9a69384cac 469
larsgk 71:4e9a69384cac 470 // resume interrupt
larsgk 71:4e9a69384cac 471 if (istat & USB_ISTAT_RESUME_MASK) {
larsgk 71:4e9a69384cac 472 USB0->ISTAT = USB_ISTAT_RESUME_MASK;
larsgk 71:4e9a69384cac 473 }
larsgk 71:4e9a69384cac 474
larsgk 71:4e9a69384cac 475 // SOF interrupt
larsgk 71:4e9a69384cac 476 if (istat & USB_ISTAT_SOFTOK_MASK) {
larsgk 71:4e9a69384cac 477 USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
larsgk 71:4e9a69384cac 478 // SOF event, read frame number
larsgk 71:4e9a69384cac 479 SOF(frameNumber());
larsgk 71:4e9a69384cac 480 }
larsgk 71:4e9a69384cac 481
larsgk 71:4e9a69384cac 482 // stall interrupt
larsgk 71:4e9a69384cac 483 if (istat & 1<<7) {
larsgk 71:4e9a69384cac 484 if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK)
larsgk 71:4e9a69384cac 485 USB0->ENDPOINT[0].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
larsgk 71:4e9a69384cac 486 USB0->ISTAT |= USB_ISTAT_STALL_MASK;
larsgk 71:4e9a69384cac 487 }
larsgk 71:4e9a69384cac 488
larsgk 71:4e9a69384cac 489 // token interrupt
larsgk 71:4e9a69384cac 490 if (istat & 1<<3) {
larsgk 71:4e9a69384cac 491 uint32_t num = (USB0->STAT >> 4) & 0x0F;
larsgk 71:4e9a69384cac 492 uint32_t dir = (USB0->STAT >> 3) & 0x01;
larsgk 71:4e9a69384cac 493 uint32_t ev_odd = (USB0->STAT >> 2) & 0x01;
larsgk 71:4e9a69384cac 494 int endpoint = (num << 1) | dir;
larsgk 71:4e9a69384cac 495
larsgk 71:4e9a69384cac 496 // setup packet
larsgk 71:4e9a69384cac 497 if ((num == 0) && (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == SETUP_TOKEN)) {
larsgk 71:4e9a69384cac 498 Data1 &= ~0x02;
larsgk 71:4e9a69384cac 499 bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
larsgk 71:4e9a69384cac 500 bdt[EP_BDT_IDX(0, TX, ODD)].info &= ~BD_OWN_MASK;
larsgk 71:4e9a69384cac 501
larsgk 71:4e9a69384cac 502 // EP0 SETUP event (SETUP data received)
larsgk 71:4e9a69384cac 503 EP0setupCallback();
larsgk 71:4e9a69384cac 504
larsgk 71:4e9a69384cac 505 } else {
larsgk 71:4e9a69384cac 506 // OUT packet
larsgk 71:4e9a69384cac 507 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == OUT_TOKEN) {
larsgk 71:4e9a69384cac 508 if (num == 0)
larsgk 71:4e9a69384cac 509 EP0out();
larsgk 71:4e9a69384cac 510 else {
larsgk 71:4e9a69384cac 511 epComplete |= EP(endpoint);
larsgk 71:4e9a69384cac 512 if ((instance->*(epCallback[endpoint - 2]))()) {
larsgk 71:4e9a69384cac 513 epComplete &= ~EP(endpoint);
larsgk 71:4e9a69384cac 514 }
larsgk 71:4e9a69384cac 515 }
larsgk 71:4e9a69384cac 516 }
larsgk 71:4e9a69384cac 517
larsgk 71:4e9a69384cac 518 // IN packet
larsgk 71:4e9a69384cac 519 if (TOK_PID((EP_BDT_IDX(num, dir, ev_odd))) == IN_TOKEN) {
larsgk 71:4e9a69384cac 520 if (num == 0) {
larsgk 71:4e9a69384cac 521 EP0in();
larsgk 71:4e9a69384cac 522 if (set_addr == 1) {
larsgk 71:4e9a69384cac 523 USB0->ADDR = addr & 0x7F;
larsgk 71:4e9a69384cac 524 set_addr = 0;
larsgk 71:4e9a69384cac 525 }
larsgk 71:4e9a69384cac 526 }
larsgk 71:4e9a69384cac 527 else {
larsgk 71:4e9a69384cac 528 epComplete |= EP(endpoint);
larsgk 71:4e9a69384cac 529 if ((instance->*(epCallback[endpoint - 2]))()) {
larsgk 71:4e9a69384cac 530 epComplete &= ~EP(endpoint);
larsgk 71:4e9a69384cac 531 }
larsgk 71:4e9a69384cac 532 }
larsgk 71:4e9a69384cac 533 }
larsgk 71:4e9a69384cac 534 }
larsgk 71:4e9a69384cac 535
larsgk 71:4e9a69384cac 536 USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
larsgk 71:4e9a69384cac 537 }
larsgk 71:4e9a69384cac 538
larsgk 71:4e9a69384cac 539 // sleep interrupt
larsgk 71:4e9a69384cac 540 if (istat & 1<<4) {
larsgk 71:4e9a69384cac 541 USB0->ISTAT |= USB_ISTAT_SLEEP_MASK;
larsgk 71:4e9a69384cac 542 }
larsgk 71:4e9a69384cac 543
larsgk 71:4e9a69384cac 544 // error interrupt
larsgk 71:4e9a69384cac 545 if (istat & USB_ISTAT_ERROR_MASK) {
larsgk 71:4e9a69384cac 546 USB0->ERRSTAT = 0xFF;
larsgk 71:4e9a69384cac 547 USB0->ISTAT |= USB_ISTAT_ERROR_MASK;
larsgk 71:4e9a69384cac 548 }
larsgk 71:4e9a69384cac 549 }
larsgk 71:4e9a69384cac 550
larsgk 71:4e9a69384cac 551
larsgk 71:4e9a69384cac 552 #endif