Diff: SLCD.cpp

Revision:

4:ec7b3c9b2aeb

Parent:

3:f70873bc6121

Child:

6:f4773221794b

diff -r f70873bc6121 -r ec7b3c9b2aeb SLCD.cpp
--- a/SLCD.cpp	Mon Jan 27 21:57:38 2014 +0000
+++ b/SLCD.cpp	Thu Feb 27 21:57:22 2014 +0000
@@ -99,10 +99,15 @@
   PORTC->PCR[22] = 0x00000000;     //VCAP2
   PORTC->PCR[23] = 0x00000000;     //VCAP1     
     // Enable IRCLK 
-     MCG->C1  = MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK;
-     MCG->C2 &= ~MCG_C2_IRCS_MASK ;  //0 32KHZ internal reference clock; 1= 4MHz irc     
+     MCG->C1  |= MCG_C1_IRCLKEN_MASK | MCG_C1_IREFSTEN_MASK;
+     MCG->C2  |= MCG_C2_IRCS_MASK ;  //0 32KHZ internal reference clock; 1= 4MHz irc
+     
+     //Check if the Fast reference has its divide by 2 enabled (default):
+     if ((MCG->SC & MCG_SC_FCRDIV_MASK) != 1<<1)
+        error("Invalid clock configuration for SLCD\n"); 
      LCD->GCR = 0x0;
-     LCD->AR  = 0x0;     
+     LCD->AR  = 0x0;   
+
     // LCD configurartion     
       LCD->GCR =   ( LCD_GCR_RVEN_MASK*_LCDRVEN  
                    | LCD_GCR_RVTRIM(_LCDRVTRIM)         //0-15
@@ -110,13 +115,13 @@
                    | LCD_GCR_LADJ(_LCDLOADADJUST)       //0-3
                    | LCD_GCR_VSUPPLY_MASK*_LCDSUPPLY    //0-1
                    |!LCD_GCR_FDCIEN_MASK
-                   | LCD_GCR_ALTDIV(_LCDALTDIV)         //0-3
+                   | LCD_GCR_ALTDIV(1)         //divide by something
                    |!LCD_GCR_LCDDOZE_MASK  
                    |!LCD_GCR_LCDSTP_MASK
                    |!LCD_GCR_LCDEN_MASK                 //WILL BE ENABLE ON SUBSEQUENT STEP
-                   | LCD_GCR_SOURCE_MASK*_LCDCLKSOURCE
-                   | LCD_GCR_ALTSOURCE_MASK*_LCDALRCLKSOURCE  
-                   | LCD_GCR_LCLK(_LCDLCK)    //0-7
+                   | LCD_GCR_SOURCE_MASK*1
+                   | LCD_GCR_ALTSOURCE_MASK*0  
+                   | LCD_GCR_LCLK(0)    //0-7
                    | LCD_GCR_DUTY(_LCDDUTY)   //0-7
                  );    
    uint8_t i;
@@ -240,4 +245,16 @@
             else {lbpLCDWF[(uint8_t)WF_ORDERING_TABLE[7]]&=~1;}                 
 }
  
-
+void SLCD::blink(int blink) {
+    if (( blink > 7) || (blink < 0))
+        LCD->AR &= ~LCD_AR_BLINK_MASK;
+    else
+        LCD->AR |= LCD_AR_BLINK_MASK | blink;
+}
+    
+void SLCD::deepsleepEnable(bool enable) {
+    MCG->C1 &= ~MCG_C1_IREFSTEN_MASK;
+    MCG->C1 |= enable << MCG_C1_IREFSTEN_SHIFT;
+    LCD->GCR &= ~LCD_GCR_LCDSTP_MASK;
+    LCD->GCR |= (!enable) << LCD_GCR_LCDSTP_SHIFT;
+}