Akila Kasunjith Hettiarachchi / Mbed 2 deprecated Atmega-Microchip-QT2160

Qtouch AT42QT2160 driver library for mbed

Dependencies:   mbed

QT2160.h@0:8961c5b1e7cb, 2018-02-16 (annotated)

Committer:
ksnjth
Date:
Fri Feb 16 10:29:39 2018 +0000
Revision:
0:8961c5b1e7cb
Rev 0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ksnjth 0:8961c5b1e7cb 1 /******************
ksnjth 0:8961c5b1e7cb 2 QT2160.h
ksnjth 0:8961c5b1e7cb 3 Created on: Feb 16, 2017
ksnjth 0:8961c5b1e7cb 4 Author: Akila Kasunjith Hettiarachchi
ksnjth 0:8961c5b1e7cb 5 */
ksnjth 0:8961c5b1e7cb 6
ksnjth 0:8961c5b1e7cb 7
ksnjth 0:8961c5b1e7cb 8 #ifndef QT2160
ksnjth 0:8961c5b1e7cb 9 #define QT2160
ksnjth 0:8961c5b1e7cb 10
ksnjth 0:8961c5b1e7cb 11 #define reg_chipID 0
ksnjth 0:8961c5b1e7cb 12 #define reg_generalStatus 2
ksnjth 0:8961c5b1e7cb 13 #define reg_keyStatus1 3
ksnjth 0:8961c5b1e7cb 14 #define reg_keyStatus2 4
ksnjth 0:8961c5b1e7cb 15 #define reg_sliderTouchPosition 5
ksnjth 0:8961c5b1e7cb 16 #define reg_GPIORead 6
ksnjth 0:8961c5b1e7cb 17 #define reg_subRevision 7
ksnjth 0:8961c5b1e7cb 18 #define reg_calibrate 10
ksnjth 0:8961c5b1e7cb 19 #define reg_reset 11
ksnjth 0:8961c5b1e7cb 20 #define reg_LPMode 12
ksnjth 0:8961c5b1e7cb 21 #define reg_burstRepetition 13
ksnjth 0:8961c5b1e7cb 22 #define reg_NegDC 15
ksnjth 0:8961c5b1e7cb 23 #define reg_posDC 16
ksnjth 0:8961c5b1e7cb 24 #define reg_normalDILimit 17
ksnjth 0:8961c5b1e7cb 25 #define reg_negRecalDelay 18
ksnjth 0:8961c5b1e7cb 26 #define reg_driftHoldTime 19
ksnjth 0:8961c5b1e7cb 27 #define reg_sliderControl 20
ksnjth 0:8961c5b1e7cb 28 #define reg_sliderOptions 21
ksnjth 0:8961c5b1e7cb 29
ksnjth 0:8961c5b1e7cb 30 //key control registers
ksnjth 0:8961c5b1e7cb 31
ksnjth 0:8961c5b1e7cb 32 #define reg_key_0_control 22
ksnjth 0:8961c5b1e7cb 33 #define reg_key_1_control 23
ksnjth 0:8961c5b1e7cb 34 #define reg_key_2_control 24
ksnjth 0:8961c5b1e7cb 35 #define reg_key_3_control 25
ksnjth 0:8961c5b1e7cb 36 #define reg_key_4_control 26
ksnjth 0:8961c5b1e7cb 37 #define reg_key_5_control 27
ksnjth 0:8961c5b1e7cb 38 #define reg_key_6_control 28
ksnjth 0:8961c5b1e7cb 39 #define reg_key_7_control 29
ksnjth 0:8961c5b1e7cb 40 #define reg_key_8_control 30
ksnjth 0:8961c5b1e7cb 41 #define reg_key_9_control 31
ksnjth 0:8961c5b1e7cb 42 #define reg_key_10_control 32
ksnjth 0:8961c5b1e7cb 43 #define reg_key_11_control 33
ksnjth 0:8961c5b1e7cb 44 #define reg_key_12_control 34
ksnjth 0:8961c5b1e7cb 45 #define reg_key_13_control 35
ksnjth 0:8961c5b1e7cb 46 #define reg_key_14_control 36
ksnjth 0:8961c5b1e7cb 47 #define reg_key_15_control 37
ksnjth 0:8961c5b1e7cb 48
ksnjth 0:8961c5b1e7cb 49 // Negative threshold control registers
ksnjth 0:8961c5b1e7cb 50
ksnjth 0:8961c5b1e7cb 51 #define reg_key_0_NTHR 38
ksnjth 0:8961c5b1e7cb 52 #define reg_key_1_NTHR 39
ksnjth 0:8961c5b1e7cb 53 #define reg_key_2_NTHR 40
ksnjth 0:8961c5b1e7cb 54 #define reg_key_3_NTHR 41
ksnjth 0:8961c5b1e7cb 55 #define reg_key_4_NTHR 42
ksnjth 0:8961c5b1e7cb 56 #define reg_key_5_NTHR 43
ksnjth 0:8961c5b1e7cb 57 #define reg_key_6_NTHR 44
ksnjth 0:8961c5b1e7cb 58 #define reg_key_7_NTHR 45
ksnjth 0:8961c5b1e7cb 59 #define reg_key_8_NTHR 46
ksnjth 0:8961c5b1e7cb 60 #define reg_key_9_NTHR 47
ksnjth 0:8961c5b1e7cb 61 #define reg_key_10_NTHR 48
ksnjth 0:8961c5b1e7cb 62 #define reg_key_11_NTHR 49
ksnjth 0:8961c5b1e7cb 63 #define reg_key_12_NTHR 50
ksnjth 0:8961c5b1e7cb 64 #define reg_key_13_NTHR 51
ksnjth 0:8961c5b1e7cb 65 #define reg_key_14_NTHR 52
ksnjth 0:8961c5b1e7cb 66 #define reg_key_15_NTHR 53
ksnjth 0:8961c5b1e7cb 67
ksnjth 0:8961c5b1e7cb 68 //Burst length control registers
ksnjth 0:8961c5b1e7cb 69
ksnjth 0:8961c5b1e7cb 70 #define reg_key_0_BL 54
ksnjth 0:8961c5b1e7cb 71 #define reg_key_1_BL 55
ksnjth 0:8961c5b1e7cb 72 #define reg_key_2_BL 56
ksnjth 0:8961c5b1e7cb 73 #define reg_key_3_BL 57
ksnjth 0:8961c5b1e7cb 74 #define reg_key_4_BL 58
ksnjth 0:8961c5b1e7cb 75 #define reg_key_5_BL 59
ksnjth 0:8961c5b1e7cb 76 #define reg_key_6_BL 60
ksnjth 0:8961c5b1e7cb 77 #define reg_key_7_BL 61
ksnjth 0:8961c5b1e7cb 78 #define reg_key_8_BL 62
ksnjth 0:8961c5b1e7cb 79 #define reg_key_9_BL 63
ksnjth 0:8961c5b1e7cb 80 #define reg_key_10_BL 64
ksnjth 0:8961c5b1e7cb 81 #define reg_key_11_BL 65
ksnjth 0:8961c5b1e7cb 82 #define reg_key_12_BL 66
ksnjth 0:8961c5b1e7cb 83 #define reg_key_13_BL 67
ksnjth 0:8961c5b1e7cb 84 #define reg_key_14_BL 68
ksnjth 0:8961c5b1e7cb 85 #define reg_key_15_BL 69
ksnjth 0:8961c5b1e7cb 86
ksnjth 0:8961c5b1e7cb 87 #define reg_GPIODrive1 70
ksnjth 0:8961c5b1e7cb 88 #define reg_GPIODrive2 71
ksnjth 0:8961c5b1e7cb 89 #define reg_GPIODirection2 73
ksnjth 0:8961c5b1e7cb 90 #define reg_GPIOPWM1 74
ksnjth 0:8961c5b1e7cb 91 #define reg_GPIOPWM2 75
ksnjth 0:8961c5b1e7cb 92 #define reg_PWMLevel 76
ksnjth 0:8961c5b1e7cb 93 #define reg_GPIOWake 77
ksnjth 0:8961c5b1e7cb 94 #define reg_commonChangeKeys1 78
ksnjth 0:8961c5b1e7cb 95 #define reg_commonChangeKeys2 79
ksnjth 0:8961c5b1e7cb 96
ksnjth 0:8961c5b1e7cb 97 #define i2cDelay 50
ksnjth 0:8961c5b1e7cb 98
ksnjth 0:8961c5b1e7cb 99
ksnjth 0:8961c5b1e7cb 100 struct readRegs
ksnjth 0:8961c5b1e7cb 101 {
ksnjth 0:8961c5b1e7cb 102 char generalStatus;
ksnjth 0:8961c5b1e7cb 103 char keyStatus1;
ksnjth 0:8961c5b1e7cb 104 char keyStatus2;
ksnjth 0:8961c5b1e7cb 105 char sliderTouchPosition;
ksnjth 0:8961c5b1e7cb 106 char GPIORead;
ksnjth 0:8961c5b1e7cb 107 };
ksnjth 0:8961c5b1e7cb 108
ksnjth 0:8961c5b1e7cb 109 union readRegsUnion {
ksnjth 0:8961c5b1e7cb 110 char all[5];
ksnjth 0:8961c5b1e7cb 111 struct readRegs Regs;
ksnjth 0:8961c5b1e7cb 112 };
ksnjth 0:8961c5b1e7cb 113
ksnjth 0:8961c5b1e7cb 114 struct QT
ksnjth 0:8961c5b1e7cb 115 {
ksnjth 0:8961c5b1e7cb 116 I2C &i2c;
ksnjth 0:8961c5b1e7cb 117 uint8_t ADDR;
ksnjth 0:8961c5b1e7cb 118 uint8_t LPmode;
ksnjth 0:8961c5b1e7cb 119 uint8_t BREP;
ksnjth 0:8961c5b1e7cb 120 uint8_t NDRIFT;
ksnjth 0:8961c5b1e7cb 121 uint8_t PDRIFT;
ksnjth 0:8961c5b1e7cb 122 uint8_t NDIL;
ksnjth 0:8961c5b1e7cb 123 uint8_t NRD;
ksnjth 0:8961c5b1e7cb 124 uint8_t DHT;
ksnjth 0:8961c5b1e7cb 125 uint8_t SliderControl;
ksnjth 0:8961c5b1e7cb 126 uint8_t RESOLUTION;
ksnjth 0:8961c5b1e7cb 127 uint8_t KEY_CONT[16];
ksnjth 0:8961c5b1e7cb 128 uint8_t NTHR[16];
ksnjth 0:8961c5b1e7cb 129 uint8_t BL[16];
ksnjth 0:8961c5b1e7cb 130 uint8_t GPIODrive1;
ksnjth 0:8961c5b1e7cb 131 uint8_t GPIODrive2;
ksnjth 0:8961c5b1e7cb 132 uint8_t GPIODirection;
ksnjth 0:8961c5b1e7cb 133 uint8_t GPIOPWM1;
ksnjth 0:8961c5b1e7cb 134 uint8_t GPIOPWM2;
ksnjth 0:8961c5b1e7cb 135 uint8_t GPIOPWMLevel;
ksnjth 0:8961c5b1e7cb 136 uint8_t GPIOWake;
ksnjth 0:8961c5b1e7cb 137 uint8_t commonChangeKeys;
ksnjth 0:8961c5b1e7cb 138 union readRegsUnion readData;
ksnjth 0:8961c5b1e7cb 139 } ;
ksnjth 0:8961c5b1e7cb 140
ksnjth 0:8961c5b1e7cb 141 void qtWrite( QT &qt, uint8_t reg_addr, uint8_t reg_value)
ksnjth 0:8961c5b1e7cb 142 {
ksnjth 0:8961c5b1e7cb 143 char write_data[5];
ksnjth 0:8961c5b1e7cb 144 write_data[0] = reg_addr;
ksnjth 0:8961c5b1e7cb 145 write_data[1] = reg_value;
ksnjth 0:8961c5b1e7cb 146 qt.i2c.write(qt.ADDR, write_data, 2);
ksnjth 0:8961c5b1e7cb 147 wait_ms(i2cDelay);
ksnjth 0:8961c5b1e7cb 148 }
ksnjth 0:8961c5b1e7cb 149
ksnjth 0:8961c5b1e7cb 150 void QTSetup(QT &qt)
ksnjth 0:8961c5b1e7cb 151 {
ksnjth 0:8961c5b1e7cb 152 qtWrite(qt, reg_reset, 8);
ksnjth 0:8961c5b1e7cb 153 qtWrite(qt, reg_calibrate, 1);
ksnjth 0:8961c5b1e7cb 154 qtWrite(qt, reg_LPMode, qt.LPmode);
ksnjth 0:8961c5b1e7cb 155 qtWrite(qt, reg_burstRepetition, qt.BREP);
ksnjth 0:8961c5b1e7cb 156 qtWrite(qt, reg_NegDC, qt.NDRIFT);
ksnjth 0:8961c5b1e7cb 157 qtWrite(qt, reg_posDC, qt.PDRIFT);
ksnjth 0:8961c5b1e7cb 158 qtWrite(qt, reg_normalDILimit, qt.NDIL);
ksnjth 0:8961c5b1e7cb 159 qtWrite(qt, reg_driftHoldTime, qt.DHT);
ksnjth 0:8961c5b1e7cb 160 qtWrite(qt, reg_sliderControl, qt.SliderControl);
ksnjth 0:8961c5b1e7cb 161 qtWrite(qt, reg_sliderOptions, qt.RESOLUTION);
ksnjth 0:8961c5b1e7cb 162 //***************key control register*************************//
ksnjth 0:8961c5b1e7cb 163 qtWrite(qt, reg_key_0_control, qt.KEY_CONT[0]);
ksnjth 0:8961c5b1e7cb 164 qtWrite(qt, reg_key_1_control, qt.KEY_CONT[1]);
ksnjth 0:8961c5b1e7cb 165 qtWrite(qt, reg_key_2_control, qt.KEY_CONT[2]);
ksnjth 0:8961c5b1e7cb 166 qtWrite(qt, reg_key_3_control, qt.KEY_CONT[3]);
ksnjth 0:8961c5b1e7cb 167 qtWrite(qt, reg_key_4_control, qt.KEY_CONT[4]);
ksnjth 0:8961c5b1e7cb 168 qtWrite(qt, reg_key_5_control, qt.KEY_CONT[5]);
ksnjth 0:8961c5b1e7cb 169 qtWrite(qt, reg_key_6_control, qt.KEY_CONT[6]);
ksnjth 0:8961c5b1e7cb 170 qtWrite(qt, reg_key_7_control, qt.KEY_CONT[7]);
ksnjth 0:8961c5b1e7cb 171 qtWrite(qt, reg_key_8_control, qt.KEY_CONT[8]);
ksnjth 0:8961c5b1e7cb 172 qtWrite(qt, reg_key_9_control, qt.KEY_CONT[9]);
ksnjth 0:8961c5b1e7cb 173 qtWrite(qt, reg_key_10_control, qt.KEY_CONT[10]);
ksnjth 0:8961c5b1e7cb 174 qtWrite(qt, reg_key_11_control, qt.KEY_CONT[11]);
ksnjth 0:8961c5b1e7cb 175 qtWrite(qt, reg_key_12_control, qt.KEY_CONT[12]);
ksnjth 0:8961c5b1e7cb 176 qtWrite(qt, reg_key_13_control, qt.KEY_CONT[13]);
ksnjth 0:8961c5b1e7cb 177 qtWrite(qt, reg_key_14_control, qt.KEY_CONT[14]);
ksnjth 0:8961c5b1e7cb 178 qtWrite(qt, reg_key_15_control, qt.KEY_CONT[15]);
ksnjth 0:8961c5b1e7cb 179 //********************NTHR registers*************************//
ksnjth 0:8961c5b1e7cb 180 qtWrite(qt, reg_key_0_NTHR, qt.NTHR[0]);
ksnjth 0:8961c5b1e7cb 181 qtWrite(qt, reg_key_1_NTHR, qt.NTHR[1]);
ksnjth 0:8961c5b1e7cb 182 qtWrite(qt, reg_key_2_NTHR, qt.NTHR[2]);
ksnjth 0:8961c5b1e7cb 183 qtWrite(qt, reg_key_3_NTHR, qt.NTHR[3]);
ksnjth 0:8961c5b1e7cb 184 qtWrite(qt, reg_key_4_NTHR, qt.NTHR[4]);
ksnjth 0:8961c5b1e7cb 185 qtWrite(qt, reg_key_5_NTHR, qt.NTHR[5]);
ksnjth 0:8961c5b1e7cb 186 qtWrite(qt, reg_key_6_NTHR, qt.NTHR[6]);
ksnjth 0:8961c5b1e7cb 187 qtWrite(qt, reg_key_7_NTHR, qt.NTHR[7]);
ksnjth 0:8961c5b1e7cb 188 qtWrite(qt, reg_key_8_NTHR, qt.NTHR[8]);
ksnjth 0:8961c5b1e7cb 189 qtWrite(qt, reg_key_9_NTHR, qt.NTHR[9]);
ksnjth 0:8961c5b1e7cb 190 qtWrite(qt, reg_key_10_NTHR, qt.NTHR[10]);
ksnjth 0:8961c5b1e7cb 191 qtWrite(qt, reg_key_11_NTHR, qt.NTHR[11]);
ksnjth 0:8961c5b1e7cb 192 qtWrite(qt, reg_key_12_NTHR, qt.NTHR[12]);
ksnjth 0:8961c5b1e7cb 193 qtWrite(qt, reg_key_13_NTHR, qt.NTHR[13]);
ksnjth 0:8961c5b1e7cb 194 qtWrite(qt, reg_key_14_NTHR, qt.NTHR[14]);
ksnjth 0:8961c5b1e7cb 195 qtWrite(qt, reg_key_15_NTHR, qt.NTHR[15]);
ksnjth 0:8961c5b1e7cb 196 //******************BL registers****************************//
ksnjth 0:8961c5b1e7cb 197 qtWrite(qt, reg_key_0_BL, qt.BL[0]);
ksnjth 0:8961c5b1e7cb 198 qtWrite(qt, reg_key_1_BL, qt.BL[1]);
ksnjth 0:8961c5b1e7cb 199 qtWrite(qt, reg_key_2_BL, qt.BL[2]);
ksnjth 0:8961c5b1e7cb 200 qtWrite(qt, reg_key_3_BL, qt.BL[3]);
ksnjth 0:8961c5b1e7cb 201 qtWrite(qt, reg_key_4_BL, qt.BL[4]);
ksnjth 0:8961c5b1e7cb 202 qtWrite(qt, reg_key_5_BL, qt.BL[5]);
ksnjth 0:8961c5b1e7cb 203 qtWrite(qt, reg_key_6_BL, qt.BL[6]);
ksnjth 0:8961c5b1e7cb 204 qtWrite(qt, reg_key_7_BL, qt.BL[7]);
ksnjth 0:8961c5b1e7cb 205 qtWrite(qt, reg_key_8_BL, qt.BL[8]);
ksnjth 0:8961c5b1e7cb 206 qtWrite(qt, reg_key_9_BL, qt.BL[9]);
ksnjth 0:8961c5b1e7cb 207 qtWrite(qt, reg_key_10_BL, qt.BL[10]);
ksnjth 0:8961c5b1e7cb 208 qtWrite(qt, reg_key_11_BL, qt.BL[11]);
ksnjth 0:8961c5b1e7cb 209 qtWrite(qt, reg_key_12_BL, qt.BL[12]);
ksnjth 0:8961c5b1e7cb 210 qtWrite(qt, reg_key_13_BL, qt.BL[13]);
ksnjth 0:8961c5b1e7cb 211 qtWrite(qt, reg_key_14_BL, qt.BL[14]);
ksnjth 0:8961c5b1e7cb 212 qtWrite(qt, reg_key_15_BL, qt.BL[15]);
ksnjth 0:8961c5b1e7cb 213
ksnjth 0:8961c5b1e7cb 214 qtWrite(qt, reg_negRecalDelay, qt.NRD);
ksnjth 0:8961c5b1e7cb 215
ksnjth 0:8961c5b1e7cb 216 qtWrite(qt, reg_calibrate, 0);
ksnjth 0:8961c5b1e7cb 217 }
ksnjth 0:8961c5b1e7cb 218
ksnjth 0:8961c5b1e7cb 219 void QTread(QT &qt)
ksnjth 0:8961c5b1e7cb 220 {
ksnjth 0:8961c5b1e7cb 221 char write_data[5];
ksnjth 0:8961c5b1e7cb 222 write_data[0] = reg_generalStatus;
ksnjth 0:8961c5b1e7cb 223 qt.i2c.write(qt.ADDR, write_data, 1);
ksnjth 0:8961c5b1e7cb 224 wait_ms(1);
ksnjth 0:8961c5b1e7cb 225 qt.i2c.read(qt.ADDR, qt.readData.all, 5);
ksnjth 0:8961c5b1e7cb 226 wait_ms(1);
ksnjth 0:8961c5b1e7cb 227 }
ksnjth 0:8961c5b1e7cb 228
ksnjth 0:8961c5b1e7cb 229 #endif