Program for testing simple spi on FPGA
Fork of SPI_HelloWorld_Mbed by
main.cpp@2:8b87ec0dce1b, 2018-09-20 (annotated)
- Committer:
- korotkiy_eugene
- Date:
- Thu Sep 20 16:32:03 2018 +0000
- Revision:
- 2:8b87ec0dce1b
- Parent:
- 1:cfd8aef8d053
change spi mode from 3 to 0
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 0:466ad3f38b6b | 1 | #include "mbed.h" |
mbed_official | 0:466ad3f38b6b | 2 | |
korotkiy_eugene | 1:cfd8aef8d053 | 3 | SPI spi(D11, D12, D13); // mosi, miso, sclk |
korotkiy_eugene | 1:cfd8aef8d053 | 4 | DigitalOut cs(D10); |
mbed_official | 0:466ad3f38b6b | 5 | |
korotkiy_eugene | 1:cfd8aef8d053 | 6 | int main() |
korotkiy_eugene | 1:cfd8aef8d053 | 7 | { |
mbed_official | 0:466ad3f38b6b | 8 | cs = 1; |
korotkiy_eugene | 1:cfd8aef8d053 | 9 | uint8_t val = 0; |
mbed_official | 0:466ad3f38b6b | 10 | |
korotkiy_eugene | 2:8b87ec0dce1b | 11 | // Setup the spi for 8 bit data, low steady state clock, |
korotkiy_eugene | 2:8b87ec0dce1b | 12 | // first edge capture, with a 1MHz clock rate |
korotkiy_eugene | 2:8b87ec0dce1b | 13 | spi.format(8,0); |
mbed_official | 0:466ad3f38b6b | 14 | spi.frequency(1000000); |
mbed_official | 0:466ad3f38b6b | 15 | |
korotkiy_eugene | 1:cfd8aef8d053 | 16 | while (1) { |
korotkiy_eugene | 1:cfd8aef8d053 | 17 | wait(0.5); |
korotkiy_eugene | 1:cfd8aef8d053 | 18 | cs = 0; |
korotkiy_eugene | 1:cfd8aef8d053 | 19 | spi.write(val++); |
korotkiy_eugene | 1:cfd8aef8d053 | 20 | cs = 1; |
korotkiy_eugene | 1:cfd8aef8d053 | 21 | } |
mbed_official | 0:466ad3f38b6b | 22 | } |