Kevin Kadooka / mbed-dev

Fork of mbed-dev build 137, last build before FAT file system appears to be broken. Also reduced HSE timeout time in STM4XX HAL

Fork of mbed-dev by mbed official

targets/TARGET_NXP/TARGET_LPC13XX/device/LPC13Uxx.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_NXP/TARGET_LPC13XX/LPC13Uxx.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1
<> 144:ef7eb2e8f9f7 2 /****************************************************************************************************//**
<> 144:ef7eb2e8f9f7 3 * @file LPC13Uxx.h
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 *
<> 144:ef7eb2e8f9f7 6 *
<> 144:ef7eb2e8f9f7 7 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 8 * default LPC13Uxx Device Series
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * @version V0.1
<> 144:ef7eb2e8f9f7 11 * @date 18. Jan 2012
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * @note Generated with SFDGen V2.6 Build 4f on Tuesday, 17.01.2012 13:39:52
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * from CMSIS SVD File 'LPC13uxx_svd_v0.1.xml' Version 0.1,
<> 144:ef7eb2e8f9f7 16 * created on Thurs, 01.19.2012 15:13:15, last modified on Thurs, 01.19.2012 15:53:09
<> 144:ef7eb2e8f9f7 17 *
<> 144:ef7eb2e8f9f7 18 *******************************************************************************************************/
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 /** @addtogroup NXP
<> 144:ef7eb2e8f9f7 21 * @{
<> 144:ef7eb2e8f9f7 22 */
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 /** @addtogroup LPC13Uxx
<> 144:ef7eb2e8f9f7 25 * @{
<> 144:ef7eb2e8f9f7 26 */
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 #ifndef __LPC13UXX_H__
<> 144:ef7eb2e8f9f7 29 #define __LPC13UXX_H__
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 32 extern "C" {
<> 144:ef7eb2e8f9f7 33 #endif
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 37 #pragma anon_unions
<> 144:ef7eb2e8f9f7 38 #endif
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 /* Interrupt Number Definition */
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 typedef enum {
<> 144:ef7eb2e8f9f7 43 // ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
<> 144:ef7eb2e8f9f7 44 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
<> 144:ef7eb2e8f9f7 45 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
<> 144:ef7eb2e8f9f7 46 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
<> 144:ef7eb2e8f9f7 47 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
<> 144:ef7eb2e8f9f7 48 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
<> 144:ef7eb2e8f9f7 49 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
<> 144:ef7eb2e8f9f7 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
<> 144:ef7eb2e8f9f7 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
<> 144:ef7eb2e8f9f7 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
<> 144:ef7eb2e8f9f7 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
<> 144:ef7eb2e8f9f7 54 // ---------------------------- LPC13Uxx Specific Interrupt Numbers --------------------------------
<> 144:ef7eb2e8f9f7 55 PIN_INT0_IRQn = 0, /*!< 0 PIN_INT0 */
<> 144:ef7eb2e8f9f7 56 PIN_INT1_IRQn = 1, /*!< 1 PIN_INT1 */
<> 144:ef7eb2e8f9f7 57 PIN_INT2_IRQn = 2, /*!< 2 PIN_INT2 */
<> 144:ef7eb2e8f9f7 58 PIN_INT3_IRQn = 3, /*!< 3 PIN_INT3 */
<> 144:ef7eb2e8f9f7 59 PIN_INT4_IRQn = 4, /*!< 4 PIN_INT4 */
<> 144:ef7eb2e8f9f7 60 PIN_INT5_IRQn = 5, /*!< 5 PIN_INT5 */
<> 144:ef7eb2e8f9f7 61 PIN_INT6_IRQn = 6, /*!< 6 PIN_INT6 */
<> 144:ef7eb2e8f9f7 62 PIN_INT7_IRQn = 7, /*!< 7 PIN_INT7 */
<> 144:ef7eb2e8f9f7 63 GINT0_IRQn = 8, /*!< 8 GINT0 */
<> 144:ef7eb2e8f9f7 64 GINT1_IRQn = 9, /*!< 9 GINT1 */
<> 144:ef7eb2e8f9f7 65 Reserved0_IRQn = 10, /*!< 10 Reserved Interrupt */
<> 144:ef7eb2e8f9f7 66 Reserved1_IRQn = 11, /*!< 11 Reserved Interrupt */
<> 144:ef7eb2e8f9f7 67 RIT_IRQn = 12, /*!< 12 Repetitive Interrupt Timer */
<> 144:ef7eb2e8f9f7 68 Reserved2_IRQn = 13, /*!< 13 Reserved Interrupt */
<> 144:ef7eb2e8f9f7 69 SSP1_IRQn = 14, /*!< 14 SSP1 */
<> 144:ef7eb2e8f9f7 70 I2C_IRQn = 15, /*!< 15 I2C */
<> 144:ef7eb2e8f9f7 71 CT16B0_IRQn = 16, /*!< 16 CT16B0 */
<> 144:ef7eb2e8f9f7 72 CT16B1_IRQn = 17, /*!< 17 CT16B1 */
<> 144:ef7eb2e8f9f7 73 CT32B0_IRQn = 18, /*!< 18 CT32B0 */
<> 144:ef7eb2e8f9f7 74 CT32B1_IRQn = 19, /*!< 19 CT32B1 */
<> 144:ef7eb2e8f9f7 75 SSP0_IRQn = 20, /*!< 20 SSP0 */
<> 144:ef7eb2e8f9f7 76 USART_IRQn = 21, /*!< 21 USART */
<> 144:ef7eb2e8f9f7 77 USB_IRQ_IRQn = 22, /*!< 22 USB_IRQ */
<> 144:ef7eb2e8f9f7 78 USB_FIQ_IRQn = 23, /*!< 23 USB_FIQ */
<> 144:ef7eb2e8f9f7 79 ADC_IRQn = 24, /*!< 24 ADC */
<> 144:ef7eb2e8f9f7 80 WDT_IRQn = 25, /*!< 25 WDT */
<> 144:ef7eb2e8f9f7 81 BOD_IRQn = 26, /*!< 26 BOD */
<> 144:ef7eb2e8f9f7 82 FMC_IRQn = 27, /*!< 27 FMC */
<> 144:ef7eb2e8f9f7 83 Reserved3_IRQn = 28, /*!< 28 Reserved Interrupt */
<> 144:ef7eb2e8f9f7 84 Reserved4_IRQn = 29, /*!< 29 Reserved Interrupt */
<> 144:ef7eb2e8f9f7 85 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
<> 144:ef7eb2e8f9f7 86 Reserved5_IRQn = 31, /*!< 31 Reserved Interrupt */
<> 144:ef7eb2e8f9f7 87 } IRQn_Type;
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /** @addtogroup Configuration_of_CMSIS
<> 144:ef7eb2e8f9f7 91 * @{
<> 144:ef7eb2e8f9f7 92 */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 #define __CM3_REV 0x0000 /*!< Cortex-M3 Core Revision */
<> 144:ef7eb2e8f9f7 97 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 98 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 99 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 100 /** @} */ /* End of group Configuration_of_CMSIS */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 #include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
<> 144:ef7eb2e8f9f7 103 #include "system_LPC13Uxx.h" /*!< LPC13Uxx System */
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 /** @addtogroup Device_Peripheral_Registers
<> 144:ef7eb2e8f9f7 106 * @{
<> 144:ef7eb2e8f9f7 107 */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 111 // ----- I2C -----
<> 144:ef7eb2e8f9f7 112 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 typedef struct { /*!< (@ 0x40000000) I2C Structure */
<> 144:ef7eb2e8f9f7 117 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. */
<> 144:ef7eb2e8f9f7 118 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. */
<> 144:ef7eb2e8f9f7 119 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. */
<> 144:ef7eb2e8f9f7 120 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
<> 144:ef7eb2e8f9f7 121 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. */
<> 144:ef7eb2e8f9f7 122 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. */
<> 144:ef7eb2e8f9f7 123 __O uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. */
<> 144:ef7eb2e8f9f7 124 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register. */
<> 144:ef7eb2e8f9f7 125 union{
<> 144:ef7eb2e8f9f7 126 __IO uint32_t ADR[3]; /*!< (@ 0x40000020) I2C Slave Address Register. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. */
<> 144:ef7eb2e8f9f7 127 struct{
<> 144:ef7eb2e8f9f7 128 __IO uint32_t ADR1;
<> 144:ef7eb2e8f9f7 129 __IO uint32_t ADR2;
<> 144:ef7eb2e8f9f7 130 __IO uint32_t ADR3;
<> 144:ef7eb2e8f9f7 131 };
<> 144:ef7eb2e8f9f7 132 };
<> 144:ef7eb2e8f9f7 133 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. */
<> 144:ef7eb2e8f9f7 134 union{
<> 144:ef7eb2e8f9f7 135 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). */
<> 144:ef7eb2e8f9f7 136 struct{
<> 144:ef7eb2e8f9f7 137 __IO uint32_t MASK0;
<> 144:ef7eb2e8f9f7 138 __IO uint32_t MASK1;
<> 144:ef7eb2e8f9f7 139 __IO uint32_t MASK2;
<> 144:ef7eb2e8f9f7 140 __IO uint32_t MASK3;
<> 144:ef7eb2e8f9f7 141 };
<> 144:ef7eb2e8f9f7 142 };
<> 144:ef7eb2e8f9f7 143 } LPC_I2C_Type;
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 147 // ----- WWDT -----
<> 144:ef7eb2e8f9f7 148 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
<> 144:ef7eb2e8f9f7 152 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
<> 144:ef7eb2e8f9f7 153 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register. This 24-bit register determines the time-out value. */
<> 144:ef7eb2e8f9f7 154 __O uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. */
<> 144:ef7eb2e8f9f7 155 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
<> 144:ef7eb2e8f9f7 156 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
<> 144:ef7eb2e8f9f7 157 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
<> 144:ef7eb2e8f9f7 158 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
<> 144:ef7eb2e8f9f7 159 } LPC_WWDT_Type;
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 163 // ----- USART -----
<> 144:ef7eb2e8f9f7 164 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 typedef struct { /*!< (@ 0x40008000) USART Structure */
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 union {
<> 144:ef7eb2e8f9f7 170 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
<> 144:ef7eb2e8f9f7 171 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
<> 144:ef7eb2e8f9f7 172 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
<> 144:ef7eb2e8f9f7 173 };
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 union {
<> 144:ef7eb2e8f9f7 176 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
<> 144:ef7eb2e8f9f7 177 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
<> 144:ef7eb2e8f9f7 178 };
<> 144:ef7eb2e8f9f7 179
<> 144:ef7eb2e8f9f7 180 union {
<> 144:ef7eb2e8f9f7 181 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
<> 144:ef7eb2e8f9f7 182 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
<> 144:ef7eb2e8f9f7 183 };
<> 144:ef7eb2e8f9f7 184 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
<> 144:ef7eb2e8f9f7 185 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
<> 144:ef7eb2e8f9f7 186 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
<> 144:ef7eb2e8f9f7 187 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
<> 144:ef7eb2e8f9f7 188 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
<> 144:ef7eb2e8f9f7 189 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
<> 144:ef7eb2e8f9f7 190 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
<> 144:ef7eb2e8f9f7 191 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
<> 144:ef7eb2e8f9f7 192 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
<> 144:ef7eb2e8f9f7 193 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
<> 144:ef7eb2e8f9f7 194 __I uint32_t RESERVED0[3];
<> 144:ef7eb2e8f9f7 195 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
<> 144:ef7eb2e8f9f7 196 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 197 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
<> 144:ef7eb2e8f9f7 198 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
<> 144:ef7eb2e8f9f7 199 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
<> 144:ef7eb2e8f9f7 200 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
<> 144:ef7eb2e8f9f7 201 __IO uint32_t SYNCCTRL; /*!< (@ 0x40008058) Synchronous mode control register. */
<> 144:ef7eb2e8f9f7 202 } LPC_USART_Type;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 206 // ----- CT16B0 -----
<> 144:ef7eb2e8f9f7 207 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 typedef struct { /*!< (@ 0x4000C000) LPC_CTxxBx_Type Structure */
<> 144:ef7eb2e8f9f7 210 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
<> 144:ef7eb2e8f9f7 211 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
<> 144:ef7eb2e8f9f7 212 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
<> 144:ef7eb2e8f9f7 213 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
<> 144:ef7eb2e8f9f7 214 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
<> 144:ef7eb2e8f9f7 215 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
<> 144:ef7eb2e8f9f7 216 union {
<> 144:ef7eb2e8f9f7 217 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
<> 144:ef7eb2e8f9f7 218 struct{
<> 144:ef7eb2e8f9f7 219 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
<> 144:ef7eb2e8f9f7 220 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
<> 144:ef7eb2e8f9f7 221 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
<> 144:ef7eb2e8f9f7 222 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
<> 144:ef7eb2e8f9f7 223 };
<> 144:ef7eb2e8f9f7 224 };
<> 144:ef7eb2e8f9f7 225 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
<> 144:ef7eb2e8f9f7 226 union{
<> 144:ef7eb2e8f9f7 227 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
<> 144:ef7eb2e8f9f7 228 struct{
<> 144:ef7eb2e8f9f7 229 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
<> 144:ef7eb2e8f9f7 230 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
<> 144:ef7eb2e8f9f7 231 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
<> 144:ef7eb2e8f9f7 232 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
<> 144:ef7eb2e8f9f7 233 };
<> 144:ef7eb2e8f9f7 234 };
<> 144:ef7eb2e8f9f7 235 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
<> 144:ef7eb2e8f9f7 236 __I uint32_t RESERVED0[12];
<> 144:ef7eb2e8f9f7 237 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
<> 144:ef7eb2e8f9f7 238 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
<> 144:ef7eb2e8f9f7 239 } LPC_CTxxBx_Type;
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 typedef struct { /*!< (@ 0x4000C000) CT16B0 Structure */
<> 144:ef7eb2e8f9f7 242 __IO uint32_t IR; /*!< (@ 0x4000C000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
<> 144:ef7eb2e8f9f7 243 __IO uint32_t TCR; /*!< (@ 0x4000C004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
<> 144:ef7eb2e8f9f7 244 __IO uint32_t TC; /*!< (@ 0x4000C008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
<> 144:ef7eb2e8f9f7 245 __IO uint32_t PR; /*!< (@ 0x4000C00C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
<> 144:ef7eb2e8f9f7 246 __IO uint32_t PC; /*!< (@ 0x4000C010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
<> 144:ef7eb2e8f9f7 247 __IO uint32_t MCR; /*!< (@ 0x4000C014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
<> 144:ef7eb2e8f9f7 248 union {
<> 144:ef7eb2e8f9f7 249 __IO uint32_t MR[4]; /*!< (@ 0x4000C018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
<> 144:ef7eb2e8f9f7 250 struct{
<> 144:ef7eb2e8f9f7 251 __IO uint32_t MR0; /*!< (@ 0x4000C018) Match Register. MR0 */
<> 144:ef7eb2e8f9f7 252 __IO uint32_t MR1; /*!< (@ 0x4000C01C) Match Register. MR1 */
<> 144:ef7eb2e8f9f7 253 __IO uint32_t MR2; /*!< (@ 0x4000C020) Match Register. MR2 */
<> 144:ef7eb2e8f9f7 254 __IO uint32_t MR3; /*!< (@ 0x4000C024) Match Register. MR3 */
<> 144:ef7eb2e8f9f7 255 };
<> 144:ef7eb2e8f9f7 256 };
<> 144:ef7eb2e8f9f7 257 __IO uint32_t CCR; /*!< (@ 0x4000C028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
<> 144:ef7eb2e8f9f7 258 union{
<> 144:ef7eb2e8f9f7 259 __I uint32_t CR[4]; /*!< (@ 0x4000C02C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
<> 144:ef7eb2e8f9f7 260 struct{
<> 144:ef7eb2e8f9f7 261 __I uint32_t CR0; /*!< (@ 0x4000C02C) Capture Register. CR 0 */
<> 144:ef7eb2e8f9f7 262 __I uint32_t CR1; /*!< (@ 0x4000C030) Capture Register. CR 1 */
<> 144:ef7eb2e8f9f7 263 __I uint32_t CR2; /*!< (@ 0x4000C034) Capture Register. CR 2 */
<> 144:ef7eb2e8f9f7 264 __I uint32_t CR3; /*!< (@ 0x4000C038) Capture Register. CR 3 */
<> 144:ef7eb2e8f9f7 265 };
<> 144:ef7eb2e8f9f7 266 };
<> 144:ef7eb2e8f9f7 267 __IO uint32_t EMR; /*!< (@ 0x4000C03C) External Match Register. The EMR controls the match function and the external match pins */
<> 144:ef7eb2e8f9f7 268 __I uint32_t RESERVED0[12];
<> 144:ef7eb2e8f9f7 269 __IO uint32_t CTCR; /*!< (@ 0x4000C070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
<> 144:ef7eb2e8f9f7 270 __IO uint32_t PWMC; /*!< (@ 0x4000C074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
<> 144:ef7eb2e8f9f7 271 } LPC_CT16B0_Type;
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273
<> 144:ef7eb2e8f9f7 274 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 275 // ----- CT16B1 -----
<> 144:ef7eb2e8f9f7 276 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 typedef struct { /*!< (@ 0x40010000) CT16B1 Structure */
<> 144:ef7eb2e8f9f7 279 __IO uint32_t IR; /*!< (@ 0x40010000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
<> 144:ef7eb2e8f9f7 280 __IO uint32_t TCR; /*!< (@ 0x40010004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
<> 144:ef7eb2e8f9f7 281 __IO uint32_t TC; /*!< (@ 0x40010008) Timer Counter. The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
<> 144:ef7eb2e8f9f7 282 __IO uint32_t PR; /*!< (@ 0x4001000C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
<> 144:ef7eb2e8f9f7 283 __IO uint32_t PC; /*!< (@ 0x40010010) Prescale Counter. The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
<> 144:ef7eb2e8f9f7 284 __IO uint32_t MCR; /*!< (@ 0x40010014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
<> 144:ef7eb2e8f9f7 285 union {
<> 144:ef7eb2e8f9f7 286 __IO uint32_t MR[4]; /*!< (@ 0x40010018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
<> 144:ef7eb2e8f9f7 287 struct{
<> 144:ef7eb2e8f9f7 288 __IO uint32_t MR0; /*!< (@ 0x40010018) Match Register. MR0 */
<> 144:ef7eb2e8f9f7 289 __IO uint32_t MR1; /*!< (@ 0x4001001C) Match Register. MR1 */
<> 144:ef7eb2e8f9f7 290 __IO uint32_t MR2; /*!< (@ 0x40010020) Match Register. MR2 */
<> 144:ef7eb2e8f9f7 291 __IO uint32_t MR3; /*!< (@ 0x40010024) Match Register. MR3 */
<> 144:ef7eb2e8f9f7 292 };
<> 144:ef7eb2e8f9f7 293 };
<> 144:ef7eb2e8f9f7 294 __IO uint32_t CCR; /*!< (@ 0x40010028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
<> 144:ef7eb2e8f9f7 295 union{
<> 144:ef7eb2e8f9f7 296 __I uint32_t CR[4]; /*!< (@ 0x4001002C) Capture Register. CR is loaded with the value of TC when there is an event on the CT16B0_CAP input. */
<> 144:ef7eb2e8f9f7 297 struct{
<> 144:ef7eb2e8f9f7 298 __I uint32_t CR0; /*!< (@ 0x4001002C) Capture Register. CR 0 */
<> 144:ef7eb2e8f9f7 299 __I uint32_t CR1; /*!< (@ 0x40010030) Capture Register. CR 1 */
<> 144:ef7eb2e8f9f7 300 __I uint32_t CR2; /*!< (@ 0x40010034) Capture Register. CR 2 */
<> 144:ef7eb2e8f9f7 301 __I uint32_t CR3; /*!< (@ 0x40010038) Capture Register. CR 3 */
<> 144:ef7eb2e8f9f7 302 };
<> 144:ef7eb2e8f9f7 303 };
<> 144:ef7eb2e8f9f7 304 __IO uint32_t EMR; /*!< (@ 0x4001003C) External Match Register. The EMR controls the match function and the external match pins */
<> 144:ef7eb2e8f9f7 305 __I uint32_t RESERVED0[12];
<> 144:ef7eb2e8f9f7 306 __IO uint32_t CTCR; /*!< (@ 0x40010070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
<> 144:ef7eb2e8f9f7 307 __IO uint32_t PWMC; /*!< (@ 0x40010074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT16B0_MAT[1:0] and CT16B1_MAT[1:0]. */
<> 144:ef7eb2e8f9f7 308 } LPC_CT16B1_Type;
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 312 // ----- CT32B0 -----
<> 144:ef7eb2e8f9f7 313 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 314 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
<> 144:ef7eb2e8f9f7 315 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
<> 144:ef7eb2e8f9f7 316 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
<> 144:ef7eb2e8f9f7 317 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
<> 144:ef7eb2e8f9f7 318 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
<> 144:ef7eb2e8f9f7 319 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
<> 144:ef7eb2e8f9f7 320 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
<> 144:ef7eb2e8f9f7 321 union {
<> 144:ef7eb2e8f9f7 322 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
<> 144:ef7eb2e8f9f7 323 struct{
<> 144:ef7eb2e8f9f7 324 __IO uint32_t MR0; /*!< (@ 0x40014018) Match Register. MR0 */
<> 144:ef7eb2e8f9f7 325 __IO uint32_t MR1; /*!< (@ 0x4001401C) Match Register. MR1 */
<> 144:ef7eb2e8f9f7 326 __IO uint32_t MR2; /*!< (@ 0x40014020) Match Register. MR2 */
<> 144:ef7eb2e8f9f7 327 __IO uint32_t MR3; /*!< (@ 0x40014024) Match Register. MR3 */
<> 144:ef7eb2e8f9f7 328 };
<> 144:ef7eb2e8f9f7 329 };
<> 144:ef7eb2e8f9f7 330 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
<> 144:ef7eb2e8f9f7 331 union{
<> 144:ef7eb2e8f9f7 332 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
<> 144:ef7eb2e8f9f7 333 struct{
<> 144:ef7eb2e8f9f7 334 __I uint32_t CR0; /*!< (@ 0x4001402C) Capture Register. CR 0 */
<> 144:ef7eb2e8f9f7 335 __I uint32_t CR1; /*!< (@ 0x40014030) Capture Register. CR 1 */
<> 144:ef7eb2e8f9f7 336 __I uint32_t CR2; /*!< (@ 0x40014034) Capture Register. CR 2 */
<> 144:ef7eb2e8f9f7 337 __I uint32_t CR3; /*!< (@ 0x40014038) Capture Register. CR 3 */
<> 144:ef7eb2e8f9f7 338 };
<> 144:ef7eb2e8f9f7 339 };
<> 144:ef7eb2e8f9f7 340 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
<> 144:ef7eb2e8f9f7 341 __I uint32_t RESERVED0[12];
<> 144:ef7eb2e8f9f7 342 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
<> 144:ef7eb2e8f9f7 343 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
<> 144:ef7eb2e8f9f7 344 } LPC_CT32B0_Type;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 348 // ----- CT32B1 -----
<> 144:ef7eb2e8f9f7 349 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 350 typedef struct { /*!< (@ 0x40018000) CT32B1 Structure */
<> 144:ef7eb2e8f9f7 351 __IO uint32_t IR; /*!< (@ 0x40018000) Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
<> 144:ef7eb2e8f9f7 352 __IO uint32_t TCR; /*!< (@ 0x40018004) Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
<> 144:ef7eb2e8f9f7 353 __IO uint32_t TC; /*!< (@ 0x40018008) Timer Counter. The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. */
<> 144:ef7eb2e8f9f7 354 __IO uint32_t PR; /*!< (@ 0x4001800C) Prescale Register. When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. */
<> 144:ef7eb2e8f9f7 355 __IO uint32_t PC; /*!< (@ 0x40018010) Prescale Counter. The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */
<> 144:ef7eb2e8f9f7 356 __IO uint32_t MCR; /*!< (@ 0x40018014) Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */
<> 144:ef7eb2e8f9f7 357 union {
<> 144:ef7eb2e8f9f7 358 __IO uint32_t MR[4]; /*!< (@ 0x40018018) Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
<> 144:ef7eb2e8f9f7 359 struct{
<> 144:ef7eb2e8f9f7 360 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
<> 144:ef7eb2e8f9f7 362 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
<> 144:ef7eb2e8f9f7 363 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
<> 144:ef7eb2e8f9f7 364 };
<> 144:ef7eb2e8f9f7 365 };
<> 144:ef7eb2e8f9f7 366 __IO uint32_t CCR; /*!< (@ 0x40018028) Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
<> 144:ef7eb2e8f9f7 367 union{
<> 144:ef7eb2e8f9f7 368 __I uint32_t CR[4]; /*!< (@ 0x4001802C) Capture Register. CR is loaded with the value of TC when there is an event on the CT32B_CAP0 input. */
<> 144:ef7eb2e8f9f7 369 struct{
<> 144:ef7eb2e8f9f7 370 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
<> 144:ef7eb2e8f9f7 371 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
<> 144:ef7eb2e8f9f7 372 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
<> 144:ef7eb2e8f9f7 373 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
<> 144:ef7eb2e8f9f7 374 };
<> 144:ef7eb2e8f9f7 375 };
<> 144:ef7eb2e8f9f7 376 __IO uint32_t EMR; /*!< (@ 0x4001803C) External Match Register. The EMR controls the match function and the external match pins CT32Bn_MAT[3:0]. */
<> 144:ef7eb2e8f9f7 377 __I uint32_t RESERVED0[12];
<> 144:ef7eb2e8f9f7 378 __IO uint32_t CTCR; /*!< (@ 0x40018070) Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
<> 144:ef7eb2e8f9f7 379 __IO uint32_t PWMC; /*!< (@ 0x40018074) PWM Control Register. The PWMCON enables PWM mode for the external match pins CT32Bn_MAT[3:0]. */
<> 144:ef7eb2e8f9f7 380 } LPC_CT32B1_Type;
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 384 // ----- ADC -----
<> 144:ef7eb2e8f9f7 385 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 386 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
<> 144:ef7eb2e8f9f7 387 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur. */
<> 144:ef7eb2e8f9f7 388 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register. Contains the result of the most recent A/D conversion. */
<> 144:ef7eb2e8f9f7 389 __I uint32_t RESERVED0[1];
<> 144:ef7eb2e8f9f7 390 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. */
<> 144:ef7eb2e8f9f7 391 union{
<> 144:ef7eb2e8f9f7 392 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
<> 144:ef7eb2e8f9f7 393 struct{
<> 144:ef7eb2e8f9f7 394 __I uint32_t DR0; /*!< (@ 0x4001C010) A/D Channel Data Register 0*/
<> 144:ef7eb2e8f9f7 395 __I uint32_t DR1; /*!< (@ 0x4001C014) A/D Channel Data Register 1*/
<> 144:ef7eb2e8f9f7 396 __I uint32_t DR2; /*!< (@ 0x4001C018) A/D Channel Data Register 2*/
<> 144:ef7eb2e8f9f7 397 __I uint32_t DR3; /*!< (@ 0x4001C01C) A/D Channel Data Register 3*/
<> 144:ef7eb2e8f9f7 398 __I uint32_t DR4; /*!< (@ 0x4001C020) A/D Channel Data Register 4*/
<> 144:ef7eb2e8f9f7 399 __I uint32_t DR5; /*!< (@ 0x4001C024) A/D Channel Data Register 5*/
<> 144:ef7eb2e8f9f7 400 __I uint32_t DR6; /*!< (@ 0x4001C028) A/D Channel Data Register 6*/
<> 144:ef7eb2e8f9f7 401 __I uint32_t DR7; /*!< (@ 0x4001C02C) A/D Channel Data Register 7*/
<> 144:ef7eb2e8f9f7 402 };
<> 144:ef7eb2e8f9f7 403 };
<> 144:ef7eb2e8f9f7 404 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. */
<> 144:ef7eb2e8f9f7 405 } LPC_ADC_Type;
<> 144:ef7eb2e8f9f7 406
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 409 // ----- PMU -----
<> 144:ef7eb2e8f9f7 410 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 411
<> 144:ef7eb2e8f9f7 412 typedef struct { /*!< (@ 0x40038000) PMU Structure */
<> 144:ef7eb2e8f9f7 413 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
<> 144:ef7eb2e8f9f7 414 union{
<> 144:ef7eb2e8f9f7 415 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
<> 144:ef7eb2e8f9f7 416 struct{
<> 144:ef7eb2e8f9f7 417 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
<> 144:ef7eb2e8f9f7 418 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
<> 144:ef7eb2e8f9f7 419 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
<> 144:ef7eb2e8f9f7 420 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
<> 144:ef7eb2e8f9f7 421 };
<> 144:ef7eb2e8f9f7 422 };
<> 144:ef7eb2e8f9f7 423 __IO uint32_t GPREG4; /*!< (@ 0x40038014) General purpose register 4 */
<> 144:ef7eb2e8f9f7 424 } LPC_PMU_Type;
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 428 // ----- FLASHCTRL -----
<> 144:ef7eb2e8f9f7 429 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
<> 144:ef7eb2e8f9f7 432 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 433 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
<> 144:ef7eb2e8f9f7 434 __I uint32_t RESERVED1[3];
<> 144:ef7eb2e8f9f7 435 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
<> 144:ef7eb2e8f9f7 436 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
<> 144:ef7eb2e8f9f7 437 __I uint32_t RESERVED2[1];
<> 144:ef7eb2e8f9f7 438 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
<> 144:ef7eb2e8f9f7 439 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
<> 144:ef7eb2e8f9f7 440 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
<> 144:ef7eb2e8f9f7 441 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
<> 144:ef7eb2e8f9f7 442 __I uint32_t RESERVED3[1001];
<> 144:ef7eb2e8f9f7 443 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
<> 144:ef7eb2e8f9f7 444 __I uint32_t RESERVED4[1];
<> 144:ef7eb2e8f9f7 445 __O uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
<> 144:ef7eb2e8f9f7 446 } LPC_FLASHCTRL_Type;
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 450 // ----- SSP -----
<> 144:ef7eb2e8f9f7 451 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 452 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
<> 144:ef7eb2e8f9f7 453 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
<> 144:ef7eb2e8f9f7 454 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
<> 144:ef7eb2e8f9f7 455 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
<> 144:ef7eb2e8f9f7 456 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
<> 144:ef7eb2e8f9f7 457 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
<> 144:ef7eb2e8f9f7 458 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
<> 144:ef7eb2e8f9f7 459 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
<> 144:ef7eb2e8f9f7 460 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
<> 144:ef7eb2e8f9f7 461 __O uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
<> 144:ef7eb2e8f9f7 462 } LPC_SSPx_Type;
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 466 // ----- IOCON -----
<> 144:ef7eb2e8f9f7 467 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 468 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
<> 144:ef7eb2e8f9f7 469 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
<> 144:ef7eb2e8f9f7 470 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
<> 144:ef7eb2e8f9f7 471 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
<> 144:ef7eb2e8f9f7 472 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
<> 144:ef7eb2e8f9f7 473 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
<> 144:ef7eb2e8f9f7 474 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
<> 144:ef7eb2e8f9f7 475 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
<> 144:ef7eb2e8f9f7 476 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
<> 144:ef7eb2e8f9f7 477 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0/SWO */
<> 144:ef7eb2e8f9f7 478 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1/TRACECLK */
<> 144:ef7eb2e8f9f7 479 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
<> 144:ef7eb2e8f9f7 480 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
<> 144:ef7eb2e8f9f7 481 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
<> 144:ef7eb2e8f9f7 482 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
<> 144:ef7eb2e8f9f7 483 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
<> 144:ef7eb2e8f9f7 484 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
<> 144:ef7eb2e8f9f7 485 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
<> 144:ef7eb2e8f9f7 486 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
<> 144:ef7eb2e8f9f7 487 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
<> 144:ef7eb2e8f9f7 488 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
<> 144:ef7eb2e8f9f7 489 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
<> 144:ef7eb2e8f9f7 490 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
<> 144:ef7eb2e8f9f7 491 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
<> 144:ef7eb2e8f9f7 492 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
<> 144:ef7eb2e8f9f7 493 __IO uint32_t PIO1_0; /*!< (@ 0x40044060) I/O configuration for pin PIO1_0/CT32B1_MAT0 */
<> 144:ef7eb2e8f9f7 494 __IO uint32_t PIO1_1; /*!< (@ 0x40044064) I/O configuration for pin PIO1_1/CT32B1_MAT1 */
<> 144:ef7eb2e8f9f7 495 __IO uint32_t PIO1_2; /*!< (@ 0x40044068) I/O configuration for pin PIO1_2/CT32B1_MAT2 */
<> 144:ef7eb2e8f9f7 496 __IO uint32_t PIO1_3; /*!< (@ 0x4004406C) I/O configuration for pin PIO1_3/CT32B1_MAT3 */
<> 144:ef7eb2e8f9f7 497 __IO uint32_t PIO1_4; /*!< (@ 0x40044070) I/O configuration for pin PIO1_4/CT32B1_CAP0 */
<> 144:ef7eb2e8f9f7 498 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
<> 144:ef7eb2e8f9f7 499 __IO uint32_t PIO1_6; /*!< (@ 0x40044078) I/O configuration for pin PIO1_6 */
<> 144:ef7eb2e8f9f7 500 __IO uint32_t PIO1_7; /*!< (@ 0x4004407C) I/O configuration for pin PIO1_7 */
<> 144:ef7eb2e8f9f7 501 __IO uint32_t PIO1_8; /*!< (@ 0x40044080) I/O configuration for pin PIO1_8 */
<> 144:ef7eb2e8f9f7 502 __IO uint32_t PIO1_9; /*!< (@ 0x40044084) I/O configuration for pin PIO1_9 */
<> 144:ef7eb2e8f9f7 503 __IO uint32_t PIO1_10; /*!< (@ 0x40044088) I/O configuration for pin PIO1_10 */
<> 144:ef7eb2e8f9f7 504 __IO uint32_t PIO1_11; /*!< (@ 0x4004408C) I/O configuration for pin PIO1_11 */
<> 144:ef7eb2e8f9f7 505 __IO uint32_t PIO1_12; /*!< (@ 0x40044090) I/O configuration for pin PIO1_12 */
<> 144:ef7eb2e8f9f7 506 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for PIO1_13/DTR/CT16B0_MAT0/TXD */
<> 144:ef7eb2e8f9f7 507 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for PIO1_14/DSR/CT16B0_MAT1/RXD */
<> 144:ef7eb2e8f9f7 508 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
<> 144:ef7eb2e8f9f7 509 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
<> 144:ef7eb2e8f9f7 510 __IO uint32_t PIO1_17; /*!< (@ 0x400440A4) I/O configuration for PIO1_17/CT16B0_CAP1/RXD */
<> 144:ef7eb2e8f9f7 511 __IO uint32_t PIO1_18; /*!< (@ 0x400440A8) I/O configuration for PIO1_18/CT16B1_CAP1/TXD */
<> 144:ef7eb2e8f9f7 512 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
<> 144:ef7eb2e8f9f7 513 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
<> 144:ef7eb2e8f9f7 514 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
<> 144:ef7eb2e8f9f7 515 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
<> 144:ef7eb2e8f9f7 516 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
<> 144:ef7eb2e8f9f7 517 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
<> 144:ef7eb2e8f9f7 518 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
<> 144:ef7eb2e8f9f7 519 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
<> 144:ef7eb2e8f9f7 520 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
<> 144:ef7eb2e8f9f7 521 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
<> 144:ef7eb2e8f9f7 522 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
<> 144:ef7eb2e8f9f7 523 __IO uint32_t PIO1_30; /*!< (@ 0x400440D8) I/O configuration for pin PIO1_30 */
<> 144:ef7eb2e8f9f7 524 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
<> 144:ef7eb2e8f9f7 525 } LPC_IOCON_Type;
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 529 // ----- SYSCON -----
<> 144:ef7eb2e8f9f7 530 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
<> 144:ef7eb2e8f9f7 533 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
<> 144:ef7eb2e8f9f7 534 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
<> 144:ef7eb2e8f9f7 535 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
<> 144:ef7eb2e8f9f7 536 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
<> 144:ef7eb2e8f9f7 537 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
<> 144:ef7eb2e8f9f7 538 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
<> 144:ef7eb2e8f9f7 539 __I uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 540 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
<> 144:ef7eb2e8f9f7 541 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
<> 144:ef7eb2e8f9f7 542 __I uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 543 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
<> 144:ef7eb2e8f9f7 544 __I uint32_t RESERVED2[3];
<> 144:ef7eb2e8f9f7 545 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
<> 144:ef7eb2e8f9f7 546 __I uint32_t RESERVED3;
<> 144:ef7eb2e8f9f7 547 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
<> 144:ef7eb2e8f9f7 548 __I uint32_t RESERVED4[9];
<> 144:ef7eb2e8f9f7 549 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
<> 144:ef7eb2e8f9f7 550 __I uint32_t RESERVED5;
<> 144:ef7eb2e8f9f7 551 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
<> 144:ef7eb2e8f9f7 552 __I uint32_t RESERVED6;
<> 144:ef7eb2e8f9f7 553 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
<> 144:ef7eb2e8f9f7 554 __I uint32_t RESERVED7[4];
<> 144:ef7eb2e8f9f7 555 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
<> 144:ef7eb2e8f9f7 556 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
<> 144:ef7eb2e8f9f7 557 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
<> 144:ef7eb2e8f9f7 558 __I uint32_t RESERVED8[3];
<> 144:ef7eb2e8f9f7 559 __IO uint32_t TRACECLKDIV; /*!< (@ 0x400480AC) ARM trace clock divider */
<> 144:ef7eb2e8f9f7 560 __IO uint32_t SYSTICKCLKDIV; /*!< (@ 0x400480B0) SYSTICK clock divder */
<> 144:ef7eb2e8f9f7 561 __I uint32_t RESERVED9[3];
<> 144:ef7eb2e8f9f7 562 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
<> 144:ef7eb2e8f9f7 563 __I uint32_t RESERVED10;
<> 144:ef7eb2e8f9f7 564 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
<> 144:ef7eb2e8f9f7 565 __I uint32_t RESERVED11[5];
<> 144:ef7eb2e8f9f7 566 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
<> 144:ef7eb2e8f9f7 567 __I uint32_t RESERVED12;
<> 144:ef7eb2e8f9f7 568 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
<> 144:ef7eb2e8f9f7 569 __I uint32_t RESERVED13[5];
<> 144:ef7eb2e8f9f7 570 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
<> 144:ef7eb2e8f9f7 571 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
<> 144:ef7eb2e8f9f7 572 __I uint32_t RESERVED14[18];
<> 144:ef7eb2e8f9f7 573 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
<> 144:ef7eb2e8f9f7 574 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
<> 144:ef7eb2e8f9f7 575 __I uint32_t RESERVED15[6];
<> 144:ef7eb2e8f9f7 576 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt latency and determinism. */
<> 144:ef7eb2e8f9f7 577 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
<> 144:ef7eb2e8f9f7 578 __IO uint32_t PINSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register */
<> 144:ef7eb2e8f9f7 579 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
<> 144:ef7eb2e8f9f7 580 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
<> 144:ef7eb2e8f9f7 581 __I uint32_t RESERVED16[25];
<> 144:ef7eb2e8f9f7 582 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
<> 144:ef7eb2e8f9f7 583 __I uint32_t RESERVED17[3];
<> 144:ef7eb2e8f9f7 584 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
<> 144:ef7eb2e8f9f7 585 __I uint32_t RESERVED18[6];
<> 144:ef7eb2e8f9f7 586 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
<> 144:ef7eb2e8f9f7 587 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
<> 144:ef7eb2e8f9f7 588 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
<> 144:ef7eb2e8f9f7 589 __I uint32_t RESERVED19[111];
<> 144:ef7eb2e8f9f7 590 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
<> 144:ef7eb2e8f9f7 591 } LPC_SYSCON_Type;
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 595 // ----- GPIO_PIN_INT -----
<> 144:ef7eb2e8f9f7 596 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 597 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
<> 144:ef7eb2e8f9f7 598 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
<> 144:ef7eb2e8f9f7 599 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 600 __O uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 601 __O uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
<> 144:ef7eb2e8f9f7 602 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
<> 144:ef7eb2e8f9f7 603 __O uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
<> 144:ef7eb2e8f9f7 604 __O uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
<> 144:ef7eb2e8f9f7 605 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
<> 144:ef7eb2e8f9f7 606 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
<> 144:ef7eb2e8f9f7 607 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
<> 144:ef7eb2e8f9f7 608 } LPC_GPIO_PIN_INT_Type;
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 612 // ----- GPIO_GROUP_INT0 -----
<> 144:ef7eb2e8f9f7 613 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 614 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
<> 144:ef7eb2e8f9f7 615 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
<> 144:ef7eb2e8f9f7 616 __I uint32_t RESERVED0[7];
<> 144:ef7eb2e8f9f7 617 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
<> 144:ef7eb2e8f9f7 618 __I uint32_t RESERVED1[6];
<> 144:ef7eb2e8f9f7 619 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
<> 144:ef7eb2e8f9f7 620 } LPC_GPIO_GROUP_INT0_Type;
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 624 // ----- GPIO_GROUP_INT1 -----
<> 144:ef7eb2e8f9f7 625 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 typedef struct { /*!< (@ 0x40060000) GPIO_GROUP_INT1 Structure */
<> 144:ef7eb2e8f9f7 628 __IO uint32_t CTRL; /*!< (@ 0x40060000) GPIO grouped interrupt control register */
<> 144:ef7eb2e8f9f7 629 __I uint32_t RESERVED0[7];
<> 144:ef7eb2e8f9f7 630 __IO uint32_t PORT_POL[2]; /*!< (@ 0x40060020) GPIO grouped interrupt port 0 polarity register */
<> 144:ef7eb2e8f9f7 631 __I uint32_t RESERVED1[6];
<> 144:ef7eb2e8f9f7 632 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x40060040) GPIO grouped interrupt port 0/1 enable register */
<> 144:ef7eb2e8f9f7 633 } LPC_GPIO_GROUP_INT1_Type;
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 637 // ----- Repetitive Interrupt Timer (RIT) -----
<> 144:ef7eb2e8f9f7 638 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 typedef struct { /*!< (@ 0x40064000) RITIMER Structure */
<> 144:ef7eb2e8f9f7 641 __IO uint32_t COMPVAL; /*!< (@ 0x40064000) RITIMER compare register */
<> 144:ef7eb2e8f9f7 642 __IO uint32_t MASK; /*!< (@ 0x40064004) RITIMER mask register */
<> 144:ef7eb2e8f9f7 643 __IO uint32_t CTRL; /*!< (@ 0x40064008) RITIMER control register */
<> 144:ef7eb2e8f9f7 644 __IO uint32_t COUNTER; /*!< (@ 0x4006400C) RITIMER counter register */
<> 144:ef7eb2e8f9f7 645 __IO uint32_t COMPVAL_H; /*!< (@ 0x40064010) RITIMER compare upper register */
<> 144:ef7eb2e8f9f7 646 __IO uint32_t MASK_H; /*!< (@ 0x40064014) RITIMER mask upper register */
<> 144:ef7eb2e8f9f7 647 __I uint32_t RESERVED0[1];
<> 144:ef7eb2e8f9f7 648 __IO uint32_t COUNTER_H; /*!< (@ 0x4006401C) RITIMER counter upper register */
<> 144:ef7eb2e8f9f7 649 } LPC_RITIMER_Type;
<> 144:ef7eb2e8f9f7 650
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 653 // ----- USB -----
<> 144:ef7eb2e8f9f7 654 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 655 typedef struct { /*!< (@ 0x40020000) USB Structure */
<> 144:ef7eb2e8f9f7 656 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40020000) USB Device Command/Status register */
<> 144:ef7eb2e8f9f7 657 __IO uint32_t INFO; /*!< (@ 0x40020004) USB Info register */
<> 144:ef7eb2e8f9f7 658 __IO uint32_t EPLISTSTART; /*!< (@ 0x40020008) USB EP Command/Status List start address */
<> 144:ef7eb2e8f9f7 659 __IO uint32_t DATABUFSTART; /*!< (@ 0x4002000C) USB Data buffer start address */
<> 144:ef7eb2e8f9f7 660 __IO uint32_t LPM; /*!< (@ 0x40020010) Link Power Management register */
<> 144:ef7eb2e8f9f7 661 __IO uint32_t EPSKIP; /*!< (@ 0x40020014) USB Endpoint skip */
<> 144:ef7eb2e8f9f7 662 __IO uint32_t EPINUSE; /*!< (@ 0x40020018) USB Endpoint Buffer in use */
<> 144:ef7eb2e8f9f7 663 __IO uint32_t EPBUFCFG; /*!< (@ 0x4002001C) USB Endpoint Buffer Configuration register */
<> 144:ef7eb2e8f9f7 664 __IO uint32_t INTSTAT; /*!< (@ 0x40020020) USB interrupt status register */
<> 144:ef7eb2e8f9f7 665 __IO uint32_t INTEN; /*!< (@ 0x40020024) USB interrupt enable register */
<> 144:ef7eb2e8f9f7 666 __IO uint32_t INTSETSTAT; /*!< (@ 0x40020028) USB set interrupt status register */
<> 144:ef7eb2e8f9f7 667 __IO uint32_t INTROUTING; /*!< (@ 0x4002002C) USB interrupt routing register */
<> 144:ef7eb2e8f9f7 668 __I uint32_t RESERVED0[1];
<> 144:ef7eb2e8f9f7 669 __I uint32_t EPTOGGLE; /*!< (@ 0x40020034) USB Endpoint toggle register */
<> 144:ef7eb2e8f9f7 670 } LPC_USB_Type;
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672
<> 144:ef7eb2e8f9f7 673 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 674 // ----- GPIO_PORT -----
<> 144:ef7eb2e8f9f7 675 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 typedef struct { /*!< (@ 0x50000000) GPIO_PORT Structure */
<> 144:ef7eb2e8f9f7 678 union {
<> 144:ef7eb2e8f9f7 679 struct {
<> 144:ef7eb2e8f9f7 680 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
<> 144:ef7eb2e8f9f7 681 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
<> 144:ef7eb2e8f9f7 682 };
<> 144:ef7eb2e8f9f7 683 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
<> 144:ef7eb2e8f9f7 684 };
<> 144:ef7eb2e8f9f7 685 __I uint32_t RESERVED0[1008];
<> 144:ef7eb2e8f9f7 686 union {
<> 144:ef7eb2e8f9f7 687 struct {
<> 144:ef7eb2e8f9f7 688 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 689 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
<> 144:ef7eb2e8f9f7 690 };
<> 144:ef7eb2e8f9f7 691 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
<> 144:ef7eb2e8f9f7 692 };
<> 144:ef7eb2e8f9f7 693 __I uint32_t RESERVED1[960];
<> 144:ef7eb2e8f9f7 694 __IO uint32_t DIR[2]; /*!< (@ 0x50002000) Direction registers port 0/1 */
<> 144:ef7eb2e8f9f7 695 __I uint32_t RESERVED2[30];
<> 144:ef7eb2e8f9f7 696 __IO uint32_t MASK[2]; /*!< (@ 0x50002080) Mask register port 0/1 */
<> 144:ef7eb2e8f9f7 697 __I uint32_t RESERVED3[30];
<> 144:ef7eb2e8f9f7 698 __IO uint32_t PIN[2]; /*!< (@ 0x50002100) Portpin register port 0 */
<> 144:ef7eb2e8f9f7 699 __I uint32_t RESERVED4[30];
<> 144:ef7eb2e8f9f7 700 __IO uint32_t MPIN[2]; /*!< (@ 0x50002180) Masked port register port 0/1 */
<> 144:ef7eb2e8f9f7 701 __I uint32_t RESERVED5[30];
<> 144:ef7eb2e8f9f7 702 __IO uint32_t SET[2]; /*!< (@ 0x50002200) Write: Set register for port 0/1 Read: output bits for port 0/1 */
<> 144:ef7eb2e8f9f7 703 __I uint32_t RESERVED6[30];
<> 144:ef7eb2e8f9f7 704 __O uint32_t CLR[2]; /*!< (@ 0x50002280) Clear port 0/1 */
<> 144:ef7eb2e8f9f7 705 __I uint32_t RESERVED7[30];
<> 144:ef7eb2e8f9f7 706 __O uint32_t NOT[2]; /*!< (@ 0x50002300) Toggle port 0/1 */
<> 144:ef7eb2e8f9f7 707 } LPC_GPIO_Type;
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 711 #pragma no_anon_unions
<> 144:ef7eb2e8f9f7 712 #endif
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714
<> 144:ef7eb2e8f9f7 715 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 716 // ----- Peripheral memory map -----
<> 144:ef7eb2e8f9f7 717 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 #define LPC_I2C_BASE (0x40000000)
<> 144:ef7eb2e8f9f7 720 #define LPC_WWDT_BASE (0x40004000)
<> 144:ef7eb2e8f9f7 721 #define LPC_USART_BASE (0x40008000)
<> 144:ef7eb2e8f9f7 722 #define LPC_CT16B0_BASE (0x4000C000)
<> 144:ef7eb2e8f9f7 723 #define LPC_CT16B1_BASE (0x40010000)
<> 144:ef7eb2e8f9f7 724 #define LPC_CT32B0_BASE (0x40014000)
<> 144:ef7eb2e8f9f7 725 #define LPC_CT32B1_BASE (0x40018000)
<> 144:ef7eb2e8f9f7 726 #define LPC_ADC_BASE (0x4001C000)
<> 144:ef7eb2e8f9f7 727 #define LPC_PMU_BASE (0x40038000)
<> 144:ef7eb2e8f9f7 728 #define LPC_FLASHCTRL_BASE (0x4003C000)
<> 144:ef7eb2e8f9f7 729 #define LPC_SSP0_BASE (0x40040000)
<> 144:ef7eb2e8f9f7 730 #define LPC_IOCON_BASE (0x40044000)
<> 144:ef7eb2e8f9f7 731 #define LPC_SYSCON_BASE (0x40048000)
<> 144:ef7eb2e8f9f7 732 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
<> 144:ef7eb2e8f9f7 733 #define LPC_SSP1_BASE (0x40058000)
<> 144:ef7eb2e8f9f7 734 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
<> 144:ef7eb2e8f9f7 735 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
<> 144:ef7eb2e8f9f7 736 #define LPC_RITIMER_BASE (0x40064000)
<> 144:ef7eb2e8f9f7 737 #define LPC_USB_BASE (0x40080000)
<> 144:ef7eb2e8f9f7 738 #define LPC_GPIO_BASE (0x50000000)
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 742 // ----- Peripheral declaration -----
<> 144:ef7eb2e8f9f7 743 // ------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 744
<> 144:ef7eb2e8f9f7 745 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
<> 144:ef7eb2e8f9f7 746 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
<> 144:ef7eb2e8f9f7 747 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
<> 144:ef7eb2e8f9f7 748 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
<> 144:ef7eb2e8f9f7 749 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
<> 144:ef7eb2e8f9f7 750 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
<> 144:ef7eb2e8f9f7 751 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
<> 144:ef7eb2e8f9f7 752 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
<> 144:ef7eb2e8f9f7 753 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
<> 144:ef7eb2e8f9f7 754 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
<> 144:ef7eb2e8f9f7 755 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
<> 144:ef7eb2e8f9f7 756 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
<> 144:ef7eb2e8f9f7 757 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
<> 144:ef7eb2e8f9f7 758 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
<> 144:ef7eb2e8f9f7 759 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
<> 144:ef7eb2e8f9f7 760 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INT0_Type*) LPC_GPIO_GROUP_INT0_BASE)
<> 144:ef7eb2e8f9f7 761 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INT1_Type*) LPC_GPIO_GROUP_INT1_BASE)
<> 144:ef7eb2e8f9f7 762 #define LPC_RITIMER ((LPC_RITIMER_Type *) LPC_RITIMER_BASE)
<> 144:ef7eb2e8f9f7 763 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
<> 144:ef7eb2e8f9f7 764 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /** @} */ /* End of group Device_Peripheral_Registers */
<> 144:ef7eb2e8f9f7 768 /** @} */ /* End of group (null) */
<> 144:ef7eb2e8f9f7 769 /** @} */ /* End of group h1usf */
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 772 }
<> 144:ef7eb2e8f9f7 773 #endif
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 #endif // __LPC13UXX_H__