Kevin Kadooka / mbed-dev

Fork of mbed-dev build 137, last build before FAT file system appears to be broken. Also reduced HSE timeout time in STM4XX HAL

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32625/mxc/pmu.c@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 * $Date: 2016-06-21 16:19:28 -0500 (Tue, 21 Jun 2016) $
<> 150:02e0a0aed4ec 33 * $Revision: 23450 $
<> 150:02e0a0aed4ec 34 *
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 #include <stdio.h>
<> 150:02e0a0aed4ec 38 #include <stddef.h>
<> 150:02e0a0aed4ec 39 #include "mxc_config.h"
<> 150:02e0a0aed4ec 40 #include "mxc_assert.h"
<> 150:02e0a0aed4ec 41 #include "pmu.h"
<> 150:02e0a0aed4ec 42
<> 150:02e0a0aed4ec 43 #if (MXC_PMU_REV == 0)
<> 150:02e0a0aed4ec 44 /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 -- workaround */
<> 150:02e0a0aed4ec 45 #include "clkman_regs.h"
<> 150:02e0a0aed4ec 46 /* Channel 5 infinite loop program */
<> 150:02e0a0aed4ec 47 static const uint32_t pmu_0[] = {
<> 150:02e0a0aed4ec 48 PMU_JUMP(0, 0, (uint32_t)pmu_0)
<> 150:02e0a0aed4ec 49 };
<> 150:02e0a0aed4ec 50 #endif
<> 150:02e0a0aed4ec 51
<> 150:02e0a0aed4ec 52 static void (*callbacks[MXC_CFG_PMU_CHANNELS])(int);
<> 150:02e0a0aed4ec 53
<> 150:02e0a0aed4ec 54
<> 150:02e0a0aed4ec 55 /******************************************************************************/
<> 150:02e0a0aed4ec 56 void PMU_Handler(void)
<> 150:02e0a0aed4ec 57 {
<> 150:02e0a0aed4ec 58 int channel;
<> 150:02e0a0aed4ec 59 uint32_t cfg1, cfg2;
<> 150:02e0a0aed4ec 60 mxc_pmu_regs_t *MXC_PMUn;
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 for (channel = 0; channel < MXC_CFG_PMU_CHANNELS; channel++) {
<> 150:02e0a0aed4ec 63 MXC_PMUn = &MXC_PMU0[channel];
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 if (MXC_PMUn->cfg & MXC_F_PMU_CFG_INTERRUPT) {
<> 150:02e0a0aed4ec 66 cfg1 = MXC_PMUn->cfg;
<> 150:02e0a0aed4ec 67 /* Since any set flags will be cleared by the write-back below, mask them off */
<> 150:02e0a0aed4ec 68 cfg2 = cfg1 & ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT);
<> 150:02e0a0aed4ec 69
<> 150:02e0a0aed4ec 70 /* Clear the interrupt flag */
<> 150:02e0a0aed4ec 71 MXC_PMUn->cfg = cfg2 | MXC_F_PMU_CFG_INTERRUPT;
<> 150:02e0a0aed4ec 72
<> 150:02e0a0aed4ec 73 if (callbacks[channel]) {
<> 150:02e0a0aed4ec 74 callbacks[channel](cfg1);
<> 150:02e0a0aed4ec 75 }
<> 150:02e0a0aed4ec 76 }
<> 150:02e0a0aed4ec 77 }
<> 150:02e0a0aed4ec 78 }
<> 150:02e0a0aed4ec 79
<> 150:02e0a0aed4ec 80 /******************************************************************************/
<> 150:02e0a0aed4ec 81 int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback)
<> 150:02e0a0aed4ec 82 {
<> 150:02e0a0aed4ec 83 if(channel >= MXC_CFG_PMU_CHANNELS)
<> 150:02e0a0aed4ec 84 return E_BAD_PARAM;
<> 150:02e0a0aed4ec 85
<> 150:02e0a0aed4ec 86 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
<> 150:02e0a0aed4ec 87 uint32_t cfg = MXC_PMUn->cfg;
<> 150:02e0a0aed4ec 88
<> 150:02e0a0aed4ec 89 /* is this channel already running? */
<> 150:02e0a0aed4ec 90 if (cfg & MXC_F_PMU_CFG_ENABLE) {
<> 150:02e0a0aed4ec 91 return E_BUSY;
<> 150:02e0a0aed4ec 92 }
<> 150:02e0a0aed4ec 93
<> 150:02e0a0aed4ec 94 #if (MXC_PMU_REV == 0)
<> 150:02e0a0aed4ec 95 /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */
<> 150:02e0a0aed4ec 96 if (channel == 5) {
<> 150:02e0a0aed4ec 97 /* Channel 5 is used for the work-around */
<> 150:02e0a0aed4ec 98 return E_BUSY;
<> 150:02e0a0aed4ec 99 }
<> 150:02e0a0aed4ec 100 /* Select always-ON clock for PMU */
<> 150:02e0a0aed4ec 101 MXC_CLKMAN->clk_gate_ctrl0 |= MXC_F_CLKMAN_CLK_GATE_CTRL0_PMU_CLK_GATER;
<> 150:02e0a0aed4ec 102 /* Start channel 5 with infinite-loop program */
<> 150:02e0a0aed4ec 103 MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE; /* Clear enable and wipe W1C flags */
<> 150:02e0a0aed4ec 104 MXC_PMU5->dscadr = (uint32_t)pmu_0;
<> 150:02e0a0aed4ec 105 MXC_PMU5->cfg = MXC_F_PMU_CFG_ENABLE | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS);
<> 150:02e0a0aed4ec 106 #endif
<> 150:02e0a0aed4ec 107 /* Set callback */
<> 150:02e0a0aed4ec 108 callbacks[channel] = callback;
<> 150:02e0a0aed4ec 109
<> 150:02e0a0aed4ec 110 /* Set start op-code */
<> 150:02e0a0aed4ec 111 MXC_PMUn->dscadr = (uint32_t)program_address;
<> 150:02e0a0aed4ec 112
<> 150:02e0a0aed4ec 113 /* Configure the channel */
<> 150:02e0a0aed4ec 114 cfg = (cfg & ~(MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_BURST_SIZE)) | (0x1c << MXC_F_PMU_CFG_BURST_SIZE_POS);
<> 150:02e0a0aed4ec 115
<> 150:02e0a0aed4ec 116 /* Enable if necessary */
<> 150:02e0a0aed4ec 117 if (callback) {
<> 150:02e0a0aed4ec 118 cfg |= MXC_F_PMU_CFG_INT_EN;
<> 150:02e0a0aed4ec 119 } else {
<> 150:02e0a0aed4ec 120 cfg &= ~MXC_F_PMU_CFG_INT_EN;
<> 150:02e0a0aed4ec 121 }
<> 150:02e0a0aed4ec 122
<> 150:02e0a0aed4ec 123 /* Start the channel */
<> 150:02e0a0aed4ec 124 cfg |= MXC_F_PMU_CFG_ENABLE;
<> 150:02e0a0aed4ec 125
<> 150:02e0a0aed4ec 126 /*If any W1C flags are set, this write will clear them */
<> 150:02e0a0aed4ec 127 MXC_PMUn->cfg = cfg;
<> 150:02e0a0aed4ec 128
<> 150:02e0a0aed4ec 129 return E_NO_ERROR;
<> 150:02e0a0aed4ec 130 }
<> 150:02e0a0aed4ec 131
<> 150:02e0a0aed4ec 132 /******************************************************************************/
<> 150:02e0a0aed4ec 133 void PMU_Stop(unsigned int channel)
<> 150:02e0a0aed4ec 134 {
<> 150:02e0a0aed4ec 135 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
<> 150:02e0a0aed4ec 136 uint32_t cfg = MXC_PMUn->cfg;
<> 150:02e0a0aed4ec 137
<> 150:02e0a0aed4ec 138 /* Since any set flags will be cleared by the write-back below, mask them off */
<> 150:02e0a0aed4ec 139 cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
<> 150:02e0a0aed4ec 140
<> 150:02e0a0aed4ec 141 /* Clear the enable bit to stop the channel */
<> 150:02e0a0aed4ec 142 cfg &= ~MXC_F_PMU_CFG_ENABLE;
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144 MXC_PMUn->cfg = cfg;
<> 150:02e0a0aed4ec 145
<> 150:02e0a0aed4ec 146 /* Remove callback */
<> 150:02e0a0aed4ec 147 callbacks[channel] = NULL;
<> 150:02e0a0aed4ec 148
<> 150:02e0a0aed4ec 149 #if (MXC_PMU_REV == 0)
<> 150:02e0a0aed4ec 150 /* MAX32630 A1 & A2 Erratum #6: PMU only supports channels 0-4 */
<> 150:02e0a0aed4ec 151 /* Check channels 0-4 for any running channels. If none found, stop channel 5 */
<> 150:02e0a0aed4ec 152 if ((MXC_PMU0->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
<> 150:02e0a0aed4ec 153 (MXC_PMU1->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
<> 150:02e0a0aed4ec 154 (MXC_PMU2->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
<> 150:02e0a0aed4ec 155 (MXC_PMU3->cfg & MXC_F_PMU_CFG_ENABLE) == 0 &&
<> 150:02e0a0aed4ec 156 (MXC_PMU4->cfg & MXC_F_PMU_CFG_ENABLE) == 0) {
<> 150:02e0a0aed4ec 157
<> 150:02e0a0aed4ec 158 MXC_PMU5->cfg &= ~MXC_F_PMU_CFG_ENABLE;
<> 150:02e0a0aed4ec 159 }
<> 150:02e0a0aed4ec 160 #endif
<> 150:02e0a0aed4ec 161
<> 150:02e0a0aed4ec 162 }
<> 150:02e0a0aed4ec 163
<> 150:02e0a0aed4ec 164 /******************************************************************************/
<> 150:02e0a0aed4ec 165 int PMU_SetCounter(unsigned int channel, unsigned int counter, uint16_t value)
<> 150:02e0a0aed4ec 166 {
<> 150:02e0a0aed4ec 167 if((channel >= MXC_CFG_PMU_CHANNELS) || counter > 1)
<> 150:02e0a0aed4ec 168 return E_BAD_PARAM;
<> 150:02e0a0aed4ec 169
<> 150:02e0a0aed4ec 170 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
<> 150:02e0a0aed4ec 171
<> 150:02e0a0aed4ec 172 if (counter == 0) {
<> 150:02e0a0aed4ec 173 MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_0) | (value << MXC_F_PMU_LOOP_COUNTER_0_POS);
<> 150:02e0a0aed4ec 174 } else {
<> 150:02e0a0aed4ec 175 MXC_PMUn->loop = (MXC_PMUn->loop & ~MXC_F_PMU_LOOP_COUNTER_1) | (value << MXC_F_PMU_LOOP_COUNTER_1_POS);
<> 150:02e0a0aed4ec 176 }
<> 150:02e0a0aed4ec 177
<> 150:02e0a0aed4ec 178 return E_NO_ERROR;
<> 150:02e0a0aed4ec 179 }
<> 150:02e0a0aed4ec 180
<> 150:02e0a0aed4ec 181 /******************************************************************************/
<> 150:02e0a0aed4ec 182 int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks)
<> 150:02e0a0aed4ec 183 {
<> 150:02e0a0aed4ec 184 if(channel >= MXC_CFG_PMU_CHANNELS)
<> 150:02e0a0aed4ec 185 return E_BAD_PARAM;
<> 150:02e0a0aed4ec 186
<> 150:02e0a0aed4ec 187 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
<> 150:02e0a0aed4ec 188 uint32_t cfg = MXC_PMUn->cfg;
<> 150:02e0a0aed4ec 189
<> 150:02e0a0aed4ec 190 /* Since any set flags will be cleared by the write-back below, mask them off */
<> 150:02e0a0aed4ec 191 cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
<> 150:02e0a0aed4ec 192
<> 150:02e0a0aed4ec 193 /* Adjust timeout settings */
<> 150:02e0a0aed4ec 194 cfg &= ~(MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL);
<> 150:02e0a0aed4ec 195 cfg |= ((timeoutClkScale << MXC_F_PMU_CFG_PS_SEL_POS) & MXC_F_PMU_CFG_PS_SEL) |
<> 150:02e0a0aed4ec 196 ((timeoutTicks << MXC_F_PMU_CFG_TO_SEL_POS) & MXC_F_PMU_CFG_TO_SEL);
<> 150:02e0a0aed4ec 197
<> 150:02e0a0aed4ec 198 MXC_PMUn->cfg = cfg;
<> 150:02e0a0aed4ec 199
<> 150:02e0a0aed4ec 200 return E_NO_ERROR;
<> 150:02e0a0aed4ec 201 }
<> 150:02e0a0aed4ec 202
<> 150:02e0a0aed4ec 203 /******************************************************************************/
<> 150:02e0a0aed4ec 204 uint32_t PMU_GetFlags(unsigned int channel)
<> 150:02e0a0aed4ec 205 {
<> 150:02e0a0aed4ec 206 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
<> 150:02e0a0aed4ec 207 uint32_t cfg = MXC_PMUn->cfg;
<> 150:02e0a0aed4ec 208
<> 150:02e0a0aed4ec 209 /* Mask off configuration bits leaving only flag bits */
<> 150:02e0a0aed4ec 210 cfg &= ~(MXC_F_PMU_CFG_ENABLE | MXC_F_PMU_CFG_MANUAL | MXC_F_PMU_CFG_TO_SEL | MXC_F_PMU_CFG_PS_SEL |
<> 150:02e0a0aed4ec 211 MXC_F_PMU_CFG_INT_EN | MXC_F_PMU_CFG_BURST_SIZE);
<> 150:02e0a0aed4ec 212
<> 150:02e0a0aed4ec 213 return cfg;
<> 150:02e0a0aed4ec 214 }
<> 150:02e0a0aed4ec 215
<> 150:02e0a0aed4ec 216 /******************************************************************************/
<> 150:02e0a0aed4ec 217 void PMU_ClearFlags(unsigned int channel, unsigned int mask)
<> 150:02e0a0aed4ec 218 {
<> 150:02e0a0aed4ec 219 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
<> 150:02e0a0aed4ec 220 uint32_t cfg = MXC_PMUn->cfg;
<> 150:02e0a0aed4ec 221
<> 150:02e0a0aed4ec 222 /* Since any set flags will be cleared by the write-back below, mask them off */
<> 150:02e0a0aed4ec 223 cfg &= ~(MXC_F_PMU_CFG_LL_STOPPED | MXC_F_PMU_CFG_BUS_ERROR | MXC_F_PMU_CFG_TO_STAT | MXC_F_PMU_CFG_INTERRUPT);
<> 150:02e0a0aed4ec 224
<> 150:02e0a0aed4ec 225 /* Now, apply the caller-supplied bits to clear */
<> 150:02e0a0aed4ec 226 cfg |= mask;
<> 150:02e0a0aed4ec 227
<> 150:02e0a0aed4ec 228 MXC_PMUn->cfg = cfg;
<> 150:02e0a0aed4ec 229 }
<> 150:02e0a0aed4ec 230
<> 150:02e0a0aed4ec 231 /******************************************************************************/
<> 150:02e0a0aed4ec 232 uint32_t PMU_IsActive(unsigned int channel)
<> 150:02e0a0aed4ec 233 {
<> 150:02e0a0aed4ec 234 mxc_pmu_regs_t *MXC_PMUn = &MXC_PMU0[channel];
<> 150:02e0a0aed4ec 235 return (MXC_PMUn->cfg & MXC_F_PMU_CFG_ENABLE);
<> 150:02e0a0aed4ec 236 }