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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_cortex.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_cortex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief CORTEX HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the CORTEX:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 *** How to configure Interrupts using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 20 ===========================================================
<> 144:ef7eb2e8f9f7 21 [..]
<> 144:ef7eb2e8f9f7 22 This section provides functions allowing to configure the NVIC interrupts (IRQ).
<> 144:ef7eb2e8f9f7 23 The Cortex-M4 exceptions are managed by CMSIS functions.
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function
<> 144:ef7eb2e8f9f7 26
<> 144:ef7eb2e8f9f7 27 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority()
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ()
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
<> 144:ef7eb2e8f9f7 33 The pending IRQ priority will be managed only by the sub priority.
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 -@- IRQ priority order (sorted by highest to lowest priority):
<> 144:ef7eb2e8f9f7 36 (+@) Lowest pre-emption priority
<> 144:ef7eb2e8f9f7 37 (+@) Lowest sub priority
<> 144:ef7eb2e8f9f7 38 (+@) Lowest hardware priority (IRQ number)
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 [..]
<> 144:ef7eb2e8f9f7 41 *** How to configure Systick using CORTEX HAL driver ***
<> 144:ef7eb2e8f9f7 42 ========================================================
<> 144:ef7eb2e8f9f7 43 [..]
<> 144:ef7eb2e8f9f7 44 Setup SysTick Timer for time base
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
<> 144:ef7eb2e8f9f7 47 is a CMSIS function that:
<> 144:ef7eb2e8f9f7 48 (++) Configures the SysTick Reload register with value passed as function parameter.
<> 144:ef7eb2e8f9f7 49 (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
<> 144:ef7eb2e8f9f7 50 (++) Resets the SysTick Counter register.
<> 144:ef7eb2e8f9f7 51 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
<> 144:ef7eb2e8f9f7 52 (++) Enables the SysTick Interrupt.
<> 144:ef7eb2e8f9f7 53 (++) Starts the SysTick Counter.
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
<> 144:ef7eb2e8f9f7 56 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
<> 144:ef7eb2e8f9f7 57 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
<> 144:ef7eb2e8f9f7 58 inside the stm32f3xx_hal_cortex.h file.
<> 144:ef7eb2e8f9f7 59
<> 144:ef7eb2e8f9f7 60 (+) You can change the SysTick IRQ priority by calling the
<> 144:ef7eb2e8f9f7 61 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 62 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 (+) To adjust the SysTick time base, use the following formula:
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s)
<> 144:ef7eb2e8f9f7 67 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
<> 144:ef7eb2e8f9f7 68 (++) Reload Value should not exceed 0xFFFFFF
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 @endverbatim
<> 144:ef7eb2e8f9f7 71 ******************************************************************************
<> 144:ef7eb2e8f9f7 72 * @attention
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 75 *
<> 144:ef7eb2e8f9f7 76 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 77 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 78 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 79 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 81 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 82 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 84 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 85 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 86 *
<> 144:ef7eb2e8f9f7 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 97 *
<> 144:ef7eb2e8f9f7 98 ******************************************************************************
<> 144:ef7eb2e8f9f7 99 */
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /*
<> 144:ef7eb2e8f9f7 102 Additional Tables: CORTEX_NVIC_Priority_Table
<> 144:ef7eb2e8f9f7 103 The table below gives the allowed values of the pre-emption priority and subpriority according
<> 144:ef7eb2e8f9f7 104 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function
<> 144:ef7eb2e8f9f7 105 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 106 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
<> 144:ef7eb2e8f9f7 107 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 108 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 109 | | | 4 bits for subpriority
<> 144:ef7eb2e8f9f7 110 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 111 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 112 | | | 3 bits for subpriority
<> 144:ef7eb2e8f9f7 113 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 114 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 115 | | | 2 bits for subpriority
<> 144:ef7eb2e8f9f7 116 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 117 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 118 | | | 1 bits for subpriority
<> 144:ef7eb2e8f9f7 119 --------------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 120 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 121 | | | 0 bits for subpriority
<> 144:ef7eb2e8f9f7 122 ==========================================================================================================================
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup CORTEX CORTEX
<> 144:ef7eb2e8f9f7 134 * @brief CORTEX CORTEX HAL module driver
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 #ifdef HAL_CORTEX_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 141 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 142 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 143 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 144 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 145 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 146
<> 144:ef7eb2e8f9f7 147 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
<> 144:ef7eb2e8f9f7 148 * @{
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 153 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 154 *
<> 144:ef7eb2e8f9f7 155 @verbatim
<> 144:ef7eb2e8f9f7 156 ==============================================================================
<> 144:ef7eb2e8f9f7 157 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 158 ==============================================================================
<> 144:ef7eb2e8f9f7 159 [..]
<> 144:ef7eb2e8f9f7 160 This section provides the CORTEX HAL driver functions allowing to configure Interrupts
<> 144:ef7eb2e8f9f7 161 Systick functionalities
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 @endverbatim
<> 144:ef7eb2e8f9f7 164 * @{
<> 144:ef7eb2e8f9f7 165 */
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /**
<> 144:ef7eb2e8f9f7 169 * @brief Sets the priority grouping field (pre-emption priority and subpriority)
<> 144:ef7eb2e8f9f7 170 * using the required unlock sequence.
<> 144:ef7eb2e8f9f7 171 * @param PriorityGroup: The priority grouping bits length.
<> 144:ef7eb2e8f9f7 172 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 173 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 174 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 175 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 176 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 177 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 178 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 179 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 180 * 1 bits for subpriority
<> 144:ef7eb2e8f9f7 181 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 182 * 0 bits for subpriority
<> 144:ef7eb2e8f9f7 183 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
<> 144:ef7eb2e8f9f7 184 * The pending IRQ priority will be managed only by the subpriority.
<> 144:ef7eb2e8f9f7 185 * @retval None
<> 144:ef7eb2e8f9f7 186 */
<> 144:ef7eb2e8f9f7 187 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
<> 144:ef7eb2e8f9f7 188 {
<> 144:ef7eb2e8f9f7 189 /* Check the parameters */
<> 144:ef7eb2e8f9f7 190 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
<> 144:ef7eb2e8f9f7 193 NVIC_SetPriorityGrouping(PriorityGroup);
<> 144:ef7eb2e8f9f7 194 }
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /**
<> 144:ef7eb2e8f9f7 197 * @brief Sets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 198 * @param IRQn: External interrupt number
<> 144:ef7eb2e8f9f7 199 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 200 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
<> 144:ef7eb2e8f9f7 201 * @param PreemptPriority: The pre-emption priority for the IRQn channel.
<> 144:ef7eb2e8f9f7 202 * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
<> 144:ef7eb2e8f9f7 203 * A lower priority value indicates a higher priority
<> 144:ef7eb2e8f9f7 204 * @param SubPriority: the subpriority level for the IRQ channel.
<> 144:ef7eb2e8f9f7 205 * This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
<> 144:ef7eb2e8f9f7 206 * A lower priority value indicates a higher priority.
<> 144:ef7eb2e8f9f7 207 * @retval None
<> 144:ef7eb2e8f9f7 208 */
<> 144:ef7eb2e8f9f7 209 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
<> 144:ef7eb2e8f9f7 210 {
<> 144:ef7eb2e8f9f7 211 uint32_t prioritygroup = 0x00;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /* Check the parameters */
<> 144:ef7eb2e8f9f7 214 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
<> 144:ef7eb2e8f9f7 215 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 prioritygroup = NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
<> 144:ef7eb2e8f9f7 220 }
<> 144:ef7eb2e8f9f7 221
<> 144:ef7eb2e8f9f7 222 /**
<> 144:ef7eb2e8f9f7 223 * @brief Enables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 224 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
<> 144:ef7eb2e8f9f7 225 * function should be called before.
<> 144:ef7eb2e8f9f7 226 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 227 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 228 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
<> 144:ef7eb2e8f9f7 229 * @retval None
<> 144:ef7eb2e8f9f7 230 */
<> 144:ef7eb2e8f9f7 231 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 232 {
<> 144:ef7eb2e8f9f7 233 /* Check the parameters */
<> 144:ef7eb2e8f9f7 234 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 235
<> 144:ef7eb2e8f9f7 236 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 237 NVIC_EnableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 238 }
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /**
<> 144:ef7eb2e8f9f7 241 * @brief Disables a device specific interrupt in the NVIC interrupt controller.
<> 144:ef7eb2e8f9f7 242 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 243 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 244 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
<> 144:ef7eb2e8f9f7 245 * @retval None
<> 144:ef7eb2e8f9f7 246 */
<> 144:ef7eb2e8f9f7 247 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 /* Check the parameters */
<> 144:ef7eb2e8f9f7 250 assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
<> 144:ef7eb2e8f9f7 251
<> 144:ef7eb2e8f9f7 252 /* Disable interrupt */
<> 144:ef7eb2e8f9f7 253 NVIC_DisableIRQ(IRQn);
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @brief Initiates a system reset request to reset the MCU.
<> 144:ef7eb2e8f9f7 258 * @retval None
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 void HAL_NVIC_SystemReset(void)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 /* System Reset */
<> 144:ef7eb2e8f9f7 263 NVIC_SystemReset();
<> 144:ef7eb2e8f9f7 264 }
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 /**
<> 144:ef7eb2e8f9f7 267 * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
<> 144:ef7eb2e8f9f7 268 * Counter is in free running mode to generate periodic interrupts.
<> 144:ef7eb2e8f9f7 269 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
<> 144:ef7eb2e8f9f7 270 * @retval status: - 0 Function succeeded.
<> 144:ef7eb2e8f9f7 271 * - 1 Function failed.
<> 144:ef7eb2e8f9f7 272 */
<> 144:ef7eb2e8f9f7 273 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
<> 144:ef7eb2e8f9f7 274 {
<> 144:ef7eb2e8f9f7 275 return SysTick_Config(TicksNumb);
<> 144:ef7eb2e8f9f7 276 }
<> 144:ef7eb2e8f9f7 277 /**
<> 144:ef7eb2e8f9f7 278 * @}
<> 144:ef7eb2e8f9f7 279 */
<> 144:ef7eb2e8f9f7 280
<> 144:ef7eb2e8f9f7 281 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 282 * @brief Cortex control functions
<> 144:ef7eb2e8f9f7 283 *
<> 144:ef7eb2e8f9f7 284 @verbatim
<> 144:ef7eb2e8f9f7 285 ==============================================================================
<> 144:ef7eb2e8f9f7 286 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 287 ==============================================================================
<> 144:ef7eb2e8f9f7 288 [..]
<> 144:ef7eb2e8f9f7 289 This subsection provides a set of functions allowing to control the CORTEX
<> 144:ef7eb2e8f9f7 290 (NVIC, SYSTICK, MPU) functionalities.
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 @endverbatim
<> 144:ef7eb2e8f9f7 294 * @{
<> 144:ef7eb2e8f9f7 295 */
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 #if (__MPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 298 /**
<> 144:ef7eb2e8f9f7 299 * @brief Initializes and configures the Region and the memory to be protected.
<> 144:ef7eb2e8f9f7 300 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
<> 144:ef7eb2e8f9f7 301 * the initialization and configuration information.
<> 144:ef7eb2e8f9f7 302 * @retval None
<> 144:ef7eb2e8f9f7 303 */
<> 144:ef7eb2e8f9f7 304 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
<> 144:ef7eb2e8f9f7 305 {
<> 144:ef7eb2e8f9f7 306 /* Check the parameters */
<> 144:ef7eb2e8f9f7 307 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
<> 144:ef7eb2e8f9f7 308 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
<> 144:ef7eb2e8f9f7 309
<> 144:ef7eb2e8f9f7 310 /* Set the Region number */
<> 144:ef7eb2e8f9f7 311 MPU->RNR = MPU_Init->Number;
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 if ((MPU_Init->Enable) != RESET)
<> 144:ef7eb2e8f9f7 314 {
<> 144:ef7eb2e8f9f7 315 /* Check the parameters */
<> 144:ef7eb2e8f9f7 316 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
<> 144:ef7eb2e8f9f7 317 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
<> 144:ef7eb2e8f9f7 318 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
<> 144:ef7eb2e8f9f7 319 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
<> 144:ef7eb2e8f9f7 320 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
<> 144:ef7eb2e8f9f7 321 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
<> 144:ef7eb2e8f9f7 322 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
<> 144:ef7eb2e8f9f7 323 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 MPU->RBAR = MPU_Init->BaseAddress;
<> 144:ef7eb2e8f9f7 326 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
<> 144:ef7eb2e8f9f7 327 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
<> 144:ef7eb2e8f9f7 328 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
<> 144:ef7eb2e8f9f7 329 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
<> 144:ef7eb2e8f9f7 330 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
<> 144:ef7eb2e8f9f7 331 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
<> 144:ef7eb2e8f9f7 332 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
<> 144:ef7eb2e8f9f7 333 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
<> 144:ef7eb2e8f9f7 334 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
<> 144:ef7eb2e8f9f7 335 }
<> 144:ef7eb2e8f9f7 336 else
<> 144:ef7eb2e8f9f7 337 {
<> 144:ef7eb2e8f9f7 338 MPU->RBAR = 0x00;
<> 144:ef7eb2e8f9f7 339 MPU->RASR = 0x00;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342 #endif /* __MPU_PRESENT */
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief Gets the priority grouping field from the NVIC Interrupt Controller.
<> 144:ef7eb2e8f9f7 346 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
<> 144:ef7eb2e8f9f7 347 */
<> 144:ef7eb2e8f9f7 348 uint32_t HAL_NVIC_GetPriorityGrouping(void)
<> 144:ef7eb2e8f9f7 349 {
<> 144:ef7eb2e8f9f7 350 /* Get the PRIGROUP[10:8] field value */
<> 144:ef7eb2e8f9f7 351 return NVIC_GetPriorityGrouping();
<> 144:ef7eb2e8f9f7 352 }
<> 144:ef7eb2e8f9f7 353
<> 144:ef7eb2e8f9f7 354 /**
<> 144:ef7eb2e8f9f7 355 * @brief Gets the priority of an interrupt.
<> 144:ef7eb2e8f9f7 356 * @param IRQn: External interrupt number
<> 144:ef7eb2e8f9f7 357 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 358 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
<> 144:ef7eb2e8f9f7 359 * @param PriorityGroup: the priority grouping bits length.
<> 144:ef7eb2e8f9f7 360 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 361 * @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 362 * 4 bits for subpriority
<> 144:ef7eb2e8f9f7 363 * @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 364 * 3 bits for subpriority
<> 144:ef7eb2e8f9f7 365 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 366 * 2 bits for subpriority
<> 144:ef7eb2e8f9f7 367 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 368 * 1 bits for subpriority
<> 144:ef7eb2e8f9f7 369 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
<> 144:ef7eb2e8f9f7 370 * 0 bits for subpriority
<> 144:ef7eb2e8f9f7 371 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
<> 144:ef7eb2e8f9f7 372 * @param pSubPriority: Pointer on the Subpriority value (starting from 0).
<> 144:ef7eb2e8f9f7 373 * @retval None
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
<> 144:ef7eb2e8f9f7 376 {
<> 144:ef7eb2e8f9f7 377 /* Check the parameters */
<> 144:ef7eb2e8f9f7 378 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
<> 144:ef7eb2e8f9f7 379 /* Get priority for Cortex-M system or device specific interrupts */
<> 144:ef7eb2e8f9f7 380 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
<> 144:ef7eb2e8f9f7 381 }
<> 144:ef7eb2e8f9f7 382
<> 144:ef7eb2e8f9f7 383 /**
<> 144:ef7eb2e8f9f7 384 * @brief Sets Pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 385 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 386 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 387 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
<> 144:ef7eb2e8f9f7 388 * @retval None
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 391 {
<> 144:ef7eb2e8f9f7 392 /* Set interrupt pending */
<> 144:ef7eb2e8f9f7 393 NVIC_SetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /**
<> 144:ef7eb2e8f9f7 397 * @brief Gets Pending Interrupt (reads the pending register in the NVIC
<> 144:ef7eb2e8f9f7 398 * and returns the pending bit for the specified interrupt).
<> 144:ef7eb2e8f9f7 399 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 400 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 401 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
<> 144:ef7eb2e8f9f7 402 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 403 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 404 */
<> 144:ef7eb2e8f9f7 405 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 406 {
<> 144:ef7eb2e8f9f7 407 /* Return 1 if pending else 0 */
<> 144:ef7eb2e8f9f7 408 return NVIC_GetPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 409 }
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @brief Clears the pending bit of an external interrupt.
<> 144:ef7eb2e8f9f7 413 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 414 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 415 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
<> 144:ef7eb2e8f9f7 416 * @retval None
<> 144:ef7eb2e8f9f7 417 */
<> 144:ef7eb2e8f9f7 418 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 /* Clear pending interrupt */
<> 144:ef7eb2e8f9f7 421 NVIC_ClearPendingIRQ(IRQn);
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /**
<> 144:ef7eb2e8f9f7 425 * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
<> 144:ef7eb2e8f9f7 426 * @param IRQn External interrupt number
<> 144:ef7eb2e8f9f7 427 * This parameter can be an enumerator of IRQn_Type enumeration
<> 144:ef7eb2e8f9f7 428 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
<> 144:ef7eb2e8f9f7 429 * @retval status: - 0 Interrupt status is not pending.
<> 144:ef7eb2e8f9f7 430 * - 1 Interrupt status is pending.
<> 144:ef7eb2e8f9f7 431 */
<> 144:ef7eb2e8f9f7 432 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
<> 144:ef7eb2e8f9f7 433 {
<> 144:ef7eb2e8f9f7 434 /* Return 1 if active else 0 */
<> 144:ef7eb2e8f9f7 435 return NVIC_GetActive(IRQn);
<> 144:ef7eb2e8f9f7 436 }
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438 /**
<> 144:ef7eb2e8f9f7 439 * @brief Configures the SysTick clock source.
<> 144:ef7eb2e8f9f7 440 * @param CLKSource: specifies the SysTick clock source.
<> 144:ef7eb2e8f9f7 441 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 442 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 443 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
<> 144:ef7eb2e8f9f7 444 * @retval None
<> 144:ef7eb2e8f9f7 445 */
<> 144:ef7eb2e8f9f7 446 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
<> 144:ef7eb2e8f9f7 447 {
<> 144:ef7eb2e8f9f7 448 /* Check the parameters */
<> 144:ef7eb2e8f9f7 449 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
<> 144:ef7eb2e8f9f7 450 if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 453 }
<> 144:ef7eb2e8f9f7 454 else
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458 }
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 /**
<> 144:ef7eb2e8f9f7 461 * @brief This function handles SYSTICK interrupt request.
<> 144:ef7eb2e8f9f7 462 * @retval None
<> 144:ef7eb2e8f9f7 463 */
<> 144:ef7eb2e8f9f7 464 void HAL_SYSTICK_IRQHandler(void)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 HAL_SYSTICK_Callback();
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 /**
<> 144:ef7eb2e8f9f7 470 * @brief SYSTICK callback.
<> 144:ef7eb2e8f9f7 471 * @retval None
<> 144:ef7eb2e8f9f7 472 */
<> 144:ef7eb2e8f9f7 473 __weak void HAL_SYSTICK_Callback(void)
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 476 the HAL_SYSTICK_Callback could be implemented in the user file
<> 144:ef7eb2e8f9f7 477 */
<> 144:ef7eb2e8f9f7 478 }
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /**
<> 144:ef7eb2e8f9f7 481 * @}
<> 144:ef7eb2e8f9f7 482 */
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 /**
<> 144:ef7eb2e8f9f7 485 * @}
<> 144:ef7eb2e8f9f7 486 */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 #endif /* HAL_CORTEX_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 489 /**
<> 144:ef7eb2e8f9f7 490 * @}
<> 144:ef7eb2e8f9f7 491 */
<> 144:ef7eb2e8f9f7 492
<> 144:ef7eb2e8f9f7 493 /**
<> 144:ef7eb2e8f9f7 494 * @}
<> 144:ef7eb2e8f9f7 495 */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/