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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
124:6a4a5b7d7324
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_rcc_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 15-December-2014
bogdanm 0:9b334a45a8ff 7 * @brief Extended RCC HAL module driver.
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 10 * functionalities RCC extension peripheral:
bogdanm 0:9b334a45a8ff 11 * + Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 ******************************************************************************
bogdanm 0:9b334a45a8ff 14 * @attention
bogdanm 0:9b334a45a8ff 15 *
bogdanm 0:9b334a45a8ff 16 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 17 *
bogdanm 0:9b334a45a8ff 18 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 19 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 20 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 21 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 23 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 24 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 26 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 27 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 28 *
bogdanm 0:9b334a45a8ff 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 39 *
bogdanm 0:9b334a45a8ff 40 ******************************************************************************
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 44 #include "stm32f1xx_hal.h"
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 47 * @{
bogdanm 0:9b334a45a8ff 48 */
bogdanm 0:9b334a45a8ff 49
bogdanm 0:9b334a45a8ff 50 #ifdef HAL_RCC_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 /** @defgroup RCCEx RCCEx
bogdanm 0:9b334a45a8ff 53 * @brief RCC Extension HAL module driver
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 59 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62 #define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 63
bogdanm 0:9b334a45a8ff 64 /* Alias word address of PLL2ON bit */
bogdanm 0:9b334a45a8ff 65 #define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
bogdanm 0:9b334a45a8ff 66 #define CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68
bogdanm 0:9b334a45a8ff 69 /**
bogdanm 0:9b334a45a8ff 70 * @}
bogdanm 0:9b334a45a8ff 71 */
bogdanm 0:9b334a45a8ff 72 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 73 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
bogdanm 0:9b334a45a8ff 74 * @{
bogdanm 0:9b334a45a8ff 75 */
bogdanm 0:9b334a45a8ff 76 /**
bogdanm 0:9b334a45a8ff 77 * @}
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
bogdanm 0:9b334a45a8ff 81 * @{
bogdanm 0:9b334a45a8ff 82 */
bogdanm 0:9b334a45a8ff 83
bogdanm 0:9b334a45a8ff 84 /**
bogdanm 0:9b334a45a8ff 85 * @}
bogdanm 0:9b334a45a8ff 86 */
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 90 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 91 /* Private functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93 /**
bogdanm 0:9b334a45a8ff 94 * @}
bogdanm 0:9b334a45a8ff 95 */
bogdanm 0:9b334a45a8ff 96
bogdanm 0:9b334a45a8ff 97 /** @addtogroup RCC
bogdanm 0:9b334a45a8ff 98 * @{
bogdanm 0:9b334a45a8ff 99 */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 /** @addtogroup RCC_Exported_Functions
bogdanm 0:9b334a45a8ff 102 * @{
bogdanm 0:9b334a45a8ff 103 */
bogdanm 0:9b334a45a8ff 104
bogdanm 0:9b334a45a8ff 105 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
bogdanm 0:9b334a45a8ff 106 /** @addtogroup RCC_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /**
bogdanm 0:9b334a45a8ff 111 * @brief Resets the RCC clock configuration to the default reset state.
bogdanm 0:9b334a45a8ff 112 * @note The default reset state of the clock configuration is given below:
bogdanm 0:9b334a45a8ff 113 * - HSI ON and used as system clock source
bogdanm 0:9b334a45a8ff 114 * - HSE and PLL OFF
bogdanm 0:9b334a45a8ff 115 * - AHB, APB1 and APB2 prescaler set to 1.
bogdanm 0:9b334a45a8ff 116 * - CSS and MCO1 OFF
bogdanm 0:9b334a45a8ff 117 * - All interrupts disabled
bogdanm 0:9b334a45a8ff 118 * @note This function doesn't modify the configuration of the
bogdanm 0:9b334a45a8ff 119 * - Peripheral clocks
bogdanm 0:9b334a45a8ff 120 * - LSI, LSE and RTC clocks
bogdanm 0:9b334a45a8ff 121 * @retval None
bogdanm 0:9b334a45a8ff 122 */
bogdanm 0:9b334a45a8ff 123 void HAL_RCC_DeInit(void)
bogdanm 0:9b334a45a8ff 124 {
bogdanm 0:9b334a45a8ff 125 /* Switch SYSCLK to HSI */
bogdanm 0:9b334a45a8ff 126 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
bogdanm 0:9b334a45a8ff 127
bogdanm 0:9b334a45a8ff 128 /* Reset HSEON, CSSON, & PLLON bits */
bogdanm 0:9b334a45a8ff 129 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131 /* Reset HSEBYP bit */
bogdanm 0:9b334a45a8ff 132 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
bogdanm 0:9b334a45a8ff 133
bogdanm 0:9b334a45a8ff 134 /* Reset CFGR register */
bogdanm 0:9b334a45a8ff 135 CLEAR_REG(RCC->CFGR);
bogdanm 0:9b334a45a8ff 136
bogdanm 0:9b334a45a8ff 137 /* Set HSITRIM bits to the reset value */
bogdanm 0:9b334a45a8ff 138 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 /* Reset CFGR2 register */
bogdanm 0:9b334a45a8ff 141 CLEAR_REG(RCC->CFGR2);
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 /* Disable all interrupts */
bogdanm 0:9b334a45a8ff 144 CLEAR_REG(RCC->CIR);
bogdanm 0:9b334a45a8ff 145 }
bogdanm 0:9b334a45a8ff 146 /**
bogdanm 0:9b334a45a8ff 147 * @}
bogdanm 0:9b334a45a8ff 148 */
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 153 /** @addtogroup RCC_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 154 * @{
bogdanm 0:9b334a45a8ff 155 */
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 /**
bogdanm 0:9b334a45a8ff 158 * @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm 0:9b334a45a8ff 159 * RCC_OscInitTypeDef.
bogdanm 0:9b334a45a8ff 160 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 161 * contains the configuration information for the RCC Oscillators.
bogdanm 0:9b334a45a8ff 162 * @note The PLL is not disabled when used as system clock.
bogdanm 0:9b334a45a8ff 163 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
bogdanm 0:9b334a45a8ff 164 * @retval HAL status
bogdanm 0:9b334a45a8ff 165 */
bogdanm 0:9b334a45a8ff 166 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /* Check the parameters */
bogdanm 0:9b334a45a8ff 171 assert_param(RCC_OscInitStruct != NULL);
bogdanm 0:9b334a45a8ff 172 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 /*------------------------------- HSE Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 175 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm 0:9b334a45a8ff 176 {
bogdanm 0:9b334a45a8ff 177 /* Check the parameters */
bogdanm 0:9b334a45a8ff 178 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
bogdanm 0:9b334a45a8ff 181 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 182 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
bogdanm 0:9b334a45a8ff 183 {
bogdanm 0:9b334a45a8ff 184 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON) && (RCC_OscInitStruct->HSEState != RCC_HSE_BYPASS))
bogdanm 0:9b334a45a8ff 185 {
bogdanm 0:9b334a45a8ff 186 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 187 }
bogdanm 0:9b334a45a8ff 188 }
bogdanm 0:9b334a45a8ff 189 else
bogdanm 0:9b334a45a8ff 190 {
bogdanm 0:9b334a45a8ff 191 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
bogdanm 0:9b334a45a8ff 192 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
bogdanm 0:9b334a45a8ff 193
bogdanm 0:9b334a45a8ff 194 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 195 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 196
bogdanm 0:9b334a45a8ff 197 /* Wait till HSE is disabled */
bogdanm 0:9b334a45a8ff 198 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 199 {
bogdanm 0:9b334a45a8ff 200 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 201 {
bogdanm 0:9b334a45a8ff 202 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 203 }
bogdanm 0:9b334a45a8ff 204 }
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 /* Set the new HSE configuration ---------------------------------------*/
bogdanm 0:9b334a45a8ff 207 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Check the HSE State */
bogdanm 0:9b334a45a8ff 210 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
bogdanm 0:9b334a45a8ff 211 {
bogdanm 0:9b334a45a8ff 212 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 213 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /* Wait till HSE is ready */
bogdanm 0:9b334a45a8ff 216 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 217 {
bogdanm 0:9b334a45a8ff 218 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 219 {
bogdanm 0:9b334a45a8ff 220 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 221 }
bogdanm 0:9b334a45a8ff 222 }
bogdanm 0:9b334a45a8ff 223 }
bogdanm 0:9b334a45a8ff 224 else
bogdanm 0:9b334a45a8ff 225 {
bogdanm 0:9b334a45a8ff 226 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 227 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 228
bogdanm 0:9b334a45a8ff 229 /* Wait till HSE is disabled */
bogdanm 0:9b334a45a8ff 230 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 231 {
bogdanm 0:9b334a45a8ff 232 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 233 {
bogdanm 0:9b334a45a8ff 234 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 235 }
bogdanm 0:9b334a45a8ff 236 }
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238 }
bogdanm 0:9b334a45a8ff 239 }
bogdanm 0:9b334a45a8ff 240 /*----------------------------- HSI Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 241 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm 0:9b334a45a8ff 242 {
bogdanm 0:9b334a45a8ff 243 /* Check the parameters */
bogdanm 0:9b334a45a8ff 244 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm 0:9b334a45a8ff 245 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
bogdanm 0:9b334a45a8ff 248 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 249 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
bogdanm 0:9b334a45a8ff 250 {
bogdanm 0:9b334a45a8ff 251 /* When HSI is used as system clock it will not disabled */
bogdanm 0:9b334a45a8ff 252 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm 0:9b334a45a8ff 253 {
bogdanm 0:9b334a45a8ff 254 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 255 }
bogdanm 0:9b334a45a8ff 256 /* Otherwise, just the calibration is allowed */
bogdanm 0:9b334a45a8ff 257 else
bogdanm 0:9b334a45a8ff 258 {
bogdanm 0:9b334a45a8ff 259 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 260 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 261 }
bogdanm 0:9b334a45a8ff 262 }
bogdanm 0:9b334a45a8ff 263 else
bogdanm 0:9b334a45a8ff 264 {
bogdanm 0:9b334a45a8ff 265 /* Check the HSI State */
bogdanm 0:9b334a45a8ff 266 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
bogdanm 0:9b334a45a8ff 267 {
bogdanm 0:9b334a45a8ff 268 /* Enable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 269 __HAL_RCC_HSI_ENABLE();
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 272 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 275 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 276 {
bogdanm 0:9b334a45a8ff 277 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 278 {
bogdanm 0:9b334a45a8ff 279 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 280 }
bogdanm 0:9b334a45a8ff 281 }
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 284 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 285 }
bogdanm 0:9b334a45a8ff 286 else
bogdanm 0:9b334a45a8ff 287 {
bogdanm 0:9b334a45a8ff 288 /* Disable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 289 __HAL_RCC_HSI_DISABLE();
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 292 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 293
bogdanm 0:9b334a45a8ff 294 /* Wait till HSI is disabled */
bogdanm 0:9b334a45a8ff 295 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 296 {
bogdanm 0:9b334a45a8ff 297 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 298 {
bogdanm 0:9b334a45a8ff 299 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 300 }
bogdanm 0:9b334a45a8ff 301 }
bogdanm 0:9b334a45a8ff 302 }
bogdanm 0:9b334a45a8ff 303 }
bogdanm 0:9b334a45a8ff 304 }
bogdanm 0:9b334a45a8ff 305 /*------------------------------ LSI Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 306 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm 0:9b334a45a8ff 307 {
bogdanm 0:9b334a45a8ff 308 /* Check the parameters */
bogdanm 0:9b334a45a8ff 309 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311 /* Check the LSI State */
bogdanm 0:9b334a45a8ff 312 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
bogdanm 0:9b334a45a8ff 313 {
bogdanm 0:9b334a45a8ff 314 /* Enable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 315 __HAL_RCC_LSI_ENABLE();
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 318 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 /* Wait till LSI is ready */
bogdanm 0:9b334a45a8ff 321 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 322 {
bogdanm 0:9b334a45a8ff 323 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 324 {
bogdanm 0:9b334a45a8ff 325 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 326 }
bogdanm 0:9b334a45a8ff 327 }
bogdanm 0:9b334a45a8ff 328 /* To have a fully stabilized clock in the specified range, a software temporization of 1ms
bogdanm 0:9b334a45a8ff 329 should be added.*/
bogdanm 0:9b334a45a8ff 330 HAL_Delay(1);
bogdanm 0:9b334a45a8ff 331 }
bogdanm 0:9b334a45a8ff 332 else
bogdanm 0:9b334a45a8ff 333 {
bogdanm 0:9b334a45a8ff 334 /* Disable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 335 __HAL_RCC_LSI_DISABLE();
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 338 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 /* Wait till LSI is disabled */
bogdanm 0:9b334a45a8ff 341 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 342 {
bogdanm 0:9b334a45a8ff 343 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 344 {
bogdanm 0:9b334a45a8ff 345 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 346 }
bogdanm 0:9b334a45a8ff 347 }
bogdanm 0:9b334a45a8ff 348 }
bogdanm 0:9b334a45a8ff 349 }
bogdanm 0:9b334a45a8ff 350 /*------------------------------ LSE Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 351 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm 0:9b334a45a8ff 352 {
bogdanm 0:9b334a45a8ff 353 /* Check the parameters */
bogdanm 0:9b334a45a8ff 354 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356 /* Enable Power Clock*/
bogdanm 0:9b334a45a8ff 357 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 360 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 363 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm 0:9b334a45a8ff 366 {
bogdanm 0:9b334a45a8ff 367 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 368 {
bogdanm 0:9b334a45a8ff 369 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 370 }
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
bogdanm 0:9b334a45a8ff 374 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 377 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379 /* Wait till LSE is disabled */
bogdanm 0:9b334a45a8ff 380 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 381 {
bogdanm 0:9b334a45a8ff 382 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 383 {
bogdanm 0:9b334a45a8ff 384 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 /* Set the new LSE configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 389 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm 0:9b334a45a8ff 390 /* Check the LSE State */
bogdanm 0:9b334a45a8ff 391 if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
bogdanm 0:9b334a45a8ff 392 {
bogdanm 0:9b334a45a8ff 393 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 394 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 395
bogdanm 0:9b334a45a8ff 396 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 397 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 398 {
bogdanm 0:9b334a45a8ff 399 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 400 {
bogdanm 0:9b334a45a8ff 401 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 402 }
bogdanm 0:9b334a45a8ff 403 }
bogdanm 0:9b334a45a8ff 404 }
bogdanm 0:9b334a45a8ff 405 else
bogdanm 0:9b334a45a8ff 406 {
bogdanm 0:9b334a45a8ff 407 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 408 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 409
bogdanm 0:9b334a45a8ff 410 /* Wait till LSE is disabled */
bogdanm 0:9b334a45a8ff 411 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 412 {
bogdanm 0:9b334a45a8ff 413 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 414 {
bogdanm 0:9b334a45a8ff 415 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 416 }
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418 }
bogdanm 0:9b334a45a8ff 419 }
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 /*-------------------------------- PLL2 Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 422 /* Check the parameters */
bogdanm 0:9b334a45a8ff 423 assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
bogdanm 0:9b334a45a8ff 424 if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
bogdanm 0:9b334a45a8ff 425 {
bogdanm 0:9b334a45a8ff 426 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
bogdanm 0:9b334a45a8ff 427 clock (i.e. it is used as PLL clock entry that is used as system clock). */
bogdanm 0:9b334a45a8ff 428 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
bogdanm 0:9b334a45a8ff 429 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
bogdanm 0:9b334a45a8ff 430 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
bogdanm 0:9b334a45a8ff 431 {
bogdanm 0:9b334a45a8ff 432 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 433 }
bogdanm 0:9b334a45a8ff 434 else
bogdanm 0:9b334a45a8ff 435 {
bogdanm 0:9b334a45a8ff 436 if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
bogdanm 0:9b334a45a8ff 437 {
bogdanm 0:9b334a45a8ff 438 /* Check the parameters */
bogdanm 0:9b334a45a8ff 439 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
bogdanm 0:9b334a45a8ff 440 assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
bogdanm 0:9b334a45a8ff 441
bogdanm 0:9b334a45a8ff 442 /* Prediv2 can be written only when the PLLI2S is disabled. */
bogdanm 0:9b334a45a8ff 443 /* Return an error only if new value is different from the programmed value */
bogdanm 0:9b334a45a8ff 444 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
bogdanm 0:9b334a45a8ff 445 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
bogdanm 0:9b334a45a8ff 446 {
bogdanm 0:9b334a45a8ff 447 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 /* Disable the main PLL2. */
bogdanm 0:9b334a45a8ff 451 __HAL_RCC_PLL2_DISABLE();
bogdanm 0:9b334a45a8ff 452
bogdanm 0:9b334a45a8ff 453 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 454 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /* Wait till PLL2 is disabled */
bogdanm 0:9b334a45a8ff 457 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
bogdanm 0:9b334a45a8ff 458 {
bogdanm 0:9b334a45a8ff 459 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 460 {
bogdanm 0:9b334a45a8ff 461 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 462 }
bogdanm 0:9b334a45a8ff 463 }
bogdanm 0:9b334a45a8ff 464
bogdanm 0:9b334a45a8ff 465 /* Configure the HSE prediv2 factor --------------------------------*/
bogdanm 0:9b334a45a8ff 466 __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /* Configure the main PLL2 multiplication factors. */
bogdanm 0:9b334a45a8ff 469 __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 /* Enable the main PLL2. */
bogdanm 0:9b334a45a8ff 472 __HAL_RCC_PLL2_ENABLE();
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 475 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 /* Wait till PLL2 is ready */
bogdanm 0:9b334a45a8ff 478 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
bogdanm 0:9b334a45a8ff 479 {
bogdanm 0:9b334a45a8ff 480 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 481 {
bogdanm 0:9b334a45a8ff 482 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484 }
bogdanm 0:9b334a45a8ff 485 }
bogdanm 0:9b334a45a8ff 486 else
bogdanm 0:9b334a45a8ff 487 {
bogdanm 0:9b334a45a8ff 488 /* Set PREDIV1 source to HSE */
bogdanm 0:9b334a45a8ff 489 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 /* Disable the main PLL2. */
bogdanm 0:9b334a45a8ff 492 __HAL_RCC_PLL2_DISABLE();
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 495 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 496
bogdanm 0:9b334a45a8ff 497 /* Wait till PLL2 is disabled */
bogdanm 0:9b334a45a8ff 498 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
bogdanm 0:9b334a45a8ff 499 {
bogdanm 0:9b334a45a8ff 500 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 501 {
bogdanm 0:9b334a45a8ff 502 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 503 }
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505 }
bogdanm 0:9b334a45a8ff 506 }
bogdanm 0:9b334a45a8ff 507 }
bogdanm 0:9b334a45a8ff 508
bogdanm 0:9b334a45a8ff 509 /*-------------------------------- PLL Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 510 /* Check the parameters */
bogdanm 0:9b334a45a8ff 511 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm 0:9b334a45a8ff 512 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm 0:9b334a45a8ff 513 {
bogdanm 0:9b334a45a8ff 514 /* Check if the PLL is used as system clock or not */
bogdanm 0:9b334a45a8ff 515 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 516 {
bogdanm 0:9b334a45a8ff 517 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm 0:9b334a45a8ff 518 {
bogdanm 0:9b334a45a8ff 519 /* Check the parameters */
bogdanm 0:9b334a45a8ff 520 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm 0:9b334a45a8ff 521 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 524 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 525
bogdanm 0:9b334a45a8ff 526 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 527 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 528
bogdanm 0:9b334a45a8ff 529 /* Wait till PLL is disabled */
bogdanm 0:9b334a45a8ff 530 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 531 {
bogdanm 0:9b334a45a8ff 532 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 533 {
bogdanm 0:9b334a45a8ff 534 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 535 }
bogdanm 0:9b334a45a8ff 536 }
bogdanm 0:9b334a45a8ff 537
bogdanm 0:9b334a45a8ff 538 /* Configure the HSE prediv1 factor and source --------------------------------*/
bogdanm 0:9b334a45a8ff 539 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
bogdanm 0:9b334a45a8ff 540 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
bogdanm 0:9b334a45a8ff 541 {
bogdanm 0:9b334a45a8ff 542 /* Check the parameter */
bogdanm 0:9b334a45a8ff 543 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
bogdanm 0:9b334a45a8ff 544 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 /* Set PREDIV1 source */
bogdanm 0:9b334a45a8ff 547 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
bogdanm 0:9b334a45a8ff 548
bogdanm 0:9b334a45a8ff 549 /* Set PREDIV1 Value */
bogdanm 0:9b334a45a8ff 550 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
bogdanm 0:9b334a45a8ff 551 }
bogdanm 0:9b334a45a8ff 552
bogdanm 0:9b334a45a8ff 553 /* Configure the main PLL clock source and multiplication factors. */
bogdanm 0:9b334a45a8ff 554 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm 0:9b334a45a8ff 555 RCC_OscInitStruct->PLL.PLLMUL);
bogdanm 0:9b334a45a8ff 556 /* Enable the main PLL. */
bogdanm 0:9b334a45a8ff 557 __HAL_RCC_PLL_ENABLE();
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 560 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 561
bogdanm 0:9b334a45a8ff 562 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 563 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 564 {
bogdanm 0:9b334a45a8ff 565 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 566 {
bogdanm 0:9b334a45a8ff 567 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 568 }
bogdanm 0:9b334a45a8ff 569 }
bogdanm 0:9b334a45a8ff 570 }
bogdanm 0:9b334a45a8ff 571 else
bogdanm 0:9b334a45a8ff 572 {
bogdanm 0:9b334a45a8ff 573 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 574 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 575
bogdanm 0:9b334a45a8ff 576 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 577 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 578
bogdanm 0:9b334a45a8ff 579 /* Wait till PLL is disabled */
bogdanm 0:9b334a45a8ff 580 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 581 {
bogdanm 0:9b334a45a8ff 582 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 583 {
bogdanm 0:9b334a45a8ff 584 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 585 }
bogdanm 0:9b334a45a8ff 586 }
bogdanm 0:9b334a45a8ff 587 }
bogdanm 0:9b334a45a8ff 588 }
bogdanm 0:9b334a45a8ff 589 else
bogdanm 0:9b334a45a8ff 590 {
bogdanm 0:9b334a45a8ff 591 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 592 }
bogdanm 0:9b334a45a8ff 593 }
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 return HAL_OK;
bogdanm 0:9b334a45a8ff 596 }
bogdanm 0:9b334a45a8ff 597 /**
bogdanm 0:9b334a45a8ff 598 * @}
bogdanm 0:9b334a45a8ff 599 */
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 #endif /* STM32F105xC STM32F107xC */
bogdanm 0:9b334a45a8ff 602
bogdanm 0:9b334a45a8ff 603 #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
bogdanm 0:9b334a45a8ff 604 defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \
bogdanm 0:9b334a45a8ff 605 defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 606 /** @addtogroup RCC_Exported_Functions_Group1
bogdanm 0:9b334a45a8ff 607 * @{
bogdanm 0:9b334a45a8ff 608 */
bogdanm 0:9b334a45a8ff 609
bogdanm 0:9b334a45a8ff 610 /**
bogdanm 0:9b334a45a8ff 611 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
bogdanm 0:9b334a45a8ff 612 * parameters in the RCC_ClkInitStruct.
bogdanm 0:9b334a45a8ff 613 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 614 * contains the configuration information for the RCC peripheral.
bogdanm 0:9b334a45a8ff 615 * @param FLatency: FLASH Latency
bogdanm 0:9b334a45a8ff 616 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 617 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
bogdanm 0:9b334a45a8ff 618 *
bogdanm 0:9b334a45a8ff 619 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
bogdanm 0:9b334a45a8ff 620 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
bogdanm 0:9b334a45a8ff 621 *
bogdanm 0:9b334a45a8ff 622 * @note The HSI is used (enabled by hardware) as system clock source after
bogdanm 0:9b334a45a8ff 623 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
bogdanm 0:9b334a45a8ff 624 * of failure of the HSE used directly or indirectly as system clock
bogdanm 0:9b334a45a8ff 625 * (if the Clock Security System CSS is enabled).
bogdanm 0:9b334a45a8ff 626 *
bogdanm 0:9b334a45a8ff 627 * @note A switch from one clock source to another occurs only if the target
bogdanm 0:9b334a45a8ff 628 * clock source is ready (clock stable after startup delay or PLL locked).
bogdanm 0:9b334a45a8ff 629 * If a clock source which is not yet ready is selected, the switch will
bogdanm 0:9b334a45a8ff 630 * occur when the clock source will be ready.
bogdanm 0:9b334a45a8ff 631 * You can use HAL_RCC_GetClockConfig() function to know which clock is
bogdanm 0:9b334a45a8ff 632 * currently used as system clock source.
bogdanm 0:9b334a45a8ff 633 * @retval None
bogdanm 0:9b334a45a8ff 634 */
bogdanm 0:9b334a45a8ff 635 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
bogdanm 0:9b334a45a8ff 636 {
bogdanm 0:9b334a45a8ff 637 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 /* Check the parameters */
bogdanm 0:9b334a45a8ff 640 assert_param(RCC_ClkInitStruct != NULL);
bogdanm 0:9b334a45a8ff 641 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
bogdanm 0:9b334a45a8ff 642 assert_param(IS_FLASH_LATENCY(FLatency));
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
bogdanm 0:9b334a45a8ff 645 must be correctly programmed according to the frequency of the CPU clock
bogdanm 0:9b334a45a8ff 646 (HCLK) of the device. */
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 /* Increasing the CPU frequency */
bogdanm 0:9b334a45a8ff 649 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
bogdanm 0:9b334a45a8ff 650 {
bogdanm 0:9b334a45a8ff 651 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 652 __HAL_FLASH_SET_LATENCY(FLatency);
bogdanm 0:9b334a45a8ff 653
bogdanm 0:9b334a45a8ff 654 /* Check that the new number of wait states is taken into account to access the Flash
bogdanm 0:9b334a45a8ff 655 memory by reading the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 656 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
bogdanm 0:9b334a45a8ff 657 {
bogdanm 0:9b334a45a8ff 658 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 659 }
bogdanm 0:9b334a45a8ff 660 /*-------------------------- HCLK Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 661 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm 0:9b334a45a8ff 662 {
bogdanm 0:9b334a45a8ff 663 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm 0:9b334a45a8ff 664 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm 0:9b334a45a8ff 665 }
bogdanm 0:9b334a45a8ff 666
bogdanm 0:9b334a45a8ff 667 /*------------------------- SYSCLK Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 668 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm 0:9b334a45a8ff 669 {
bogdanm 0:9b334a45a8ff 670 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm 0:9b334a45a8ff 671
bogdanm 0:9b334a45a8ff 672 /* HSE is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 673 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 674 {
bogdanm 0:9b334a45a8ff 675 /* Check the HSE ready flag */
bogdanm 0:9b334a45a8ff 676 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 677 {
bogdanm 0:9b334a45a8ff 678 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 679 }
bogdanm 0:9b334a45a8ff 680 }
bogdanm 0:9b334a45a8ff 681 /* PLL is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 682 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 683 {
bogdanm 0:9b334a45a8ff 684 /* Check the PLL ready flag */
bogdanm 0:9b334a45a8ff 685 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 686 {
bogdanm 0:9b334a45a8ff 687 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 688 }
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690 /* HSI is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 691 else
bogdanm 0:9b334a45a8ff 692 {
bogdanm 0:9b334a45a8ff 693 /* Check the HSI ready flag */
bogdanm 0:9b334a45a8ff 694 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 695 {
bogdanm 0:9b334a45a8ff 696 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 697 }
bogdanm 0:9b334a45a8ff 698 }
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 703 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 704
bogdanm 0:9b334a45a8ff 705 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 706 {
bogdanm 0:9b334a45a8ff 707 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 708 {
bogdanm 0:9b334a45a8ff 709 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 710 {
bogdanm 0:9b334a45a8ff 711 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 712 }
bogdanm 0:9b334a45a8ff 713 }
bogdanm 0:9b334a45a8ff 714 }
bogdanm 0:9b334a45a8ff 715 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 716 {
bogdanm 0:9b334a45a8ff 717 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 718 {
bogdanm 0:9b334a45a8ff 719 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 720 {
bogdanm 0:9b334a45a8ff 721 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 722 }
bogdanm 0:9b334a45a8ff 723 }
bogdanm 0:9b334a45a8ff 724 }
bogdanm 0:9b334a45a8ff 725 else
bogdanm 0:9b334a45a8ff 726 {
bogdanm 0:9b334a45a8ff 727 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 728 {
bogdanm 0:9b334a45a8ff 729 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 730 {
bogdanm 0:9b334a45a8ff 731 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 732 }
bogdanm 0:9b334a45a8ff 733 }
bogdanm 0:9b334a45a8ff 734 }
bogdanm 0:9b334a45a8ff 735 }
bogdanm 0:9b334a45a8ff 736 }
bogdanm 0:9b334a45a8ff 737 /* Decreasing the CPU frequency */
bogdanm 0:9b334a45a8ff 738 else
bogdanm 0:9b334a45a8ff 739 {
bogdanm 0:9b334a45a8ff 740 /*-------------------------- HCLK Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 741 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
bogdanm 0:9b334a45a8ff 742 {
bogdanm 0:9b334a45a8ff 743 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
bogdanm 0:9b334a45a8ff 744 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
bogdanm 0:9b334a45a8ff 745 }
bogdanm 0:9b334a45a8ff 746
bogdanm 0:9b334a45a8ff 747 /*------------------------- SYSCLK Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 748 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
bogdanm 0:9b334a45a8ff 749 {
bogdanm 0:9b334a45a8ff 750 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
bogdanm 0:9b334a45a8ff 751
bogdanm 0:9b334a45a8ff 752 /* HSE is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 753 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 754 {
bogdanm 0:9b334a45a8ff 755 /* Check the HSE ready flag */
bogdanm 0:9b334a45a8ff 756 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 757 {
bogdanm 0:9b334a45a8ff 758 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 759 }
bogdanm 0:9b334a45a8ff 760 }
bogdanm 0:9b334a45a8ff 761 /* PLL is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 762 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 763 {
bogdanm 0:9b334a45a8ff 764 /* Check the PLL ready flag */
bogdanm 0:9b334a45a8ff 765 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 766 {
bogdanm 0:9b334a45a8ff 767 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 768 }
bogdanm 0:9b334a45a8ff 769 }
bogdanm 0:9b334a45a8ff 770 /* HSI is selected as System Clock Source */
bogdanm 0:9b334a45a8ff 771 else
bogdanm 0:9b334a45a8ff 772 {
bogdanm 0:9b334a45a8ff 773 /* Check the HSI ready flag */
bogdanm 0:9b334a45a8ff 774 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 775 {
bogdanm 0:9b334a45a8ff 776 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 777 }
bogdanm 0:9b334a45a8ff 778 }
bogdanm 0:9b334a45a8ff 779
bogdanm 0:9b334a45a8ff 780 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
bogdanm 0:9b334a45a8ff 781
bogdanm 0:9b334a45a8ff 782 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 783 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 784
bogdanm 0:9b334a45a8ff 785 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
bogdanm 0:9b334a45a8ff 786 {
bogdanm 0:9b334a45a8ff 787 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
bogdanm 0:9b334a45a8ff 788 {
bogdanm 0:9b334a45a8ff 789 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 790 {
bogdanm 0:9b334a45a8ff 791 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 792 }
bogdanm 0:9b334a45a8ff 793 }
bogdanm 0:9b334a45a8ff 794 }
bogdanm 0:9b334a45a8ff 795 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
bogdanm 0:9b334a45a8ff 796 {
bogdanm 0:9b334a45a8ff 797 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 798 {
bogdanm 0:9b334a45a8ff 799 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 800 {
bogdanm 0:9b334a45a8ff 801 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 802 }
bogdanm 0:9b334a45a8ff 803 }
bogdanm 0:9b334a45a8ff 804 }
bogdanm 0:9b334a45a8ff 805 else
bogdanm 0:9b334a45a8ff 806 {
bogdanm 0:9b334a45a8ff 807 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
bogdanm 0:9b334a45a8ff 808 {
bogdanm 0:9b334a45a8ff 809 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 810 {
bogdanm 0:9b334a45a8ff 811 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 812 }
bogdanm 0:9b334a45a8ff 813 }
bogdanm 0:9b334a45a8ff 814 }
bogdanm 0:9b334a45a8ff 815 }
bogdanm 0:9b334a45a8ff 816
bogdanm 0:9b334a45a8ff 817 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 818 __HAL_FLASH_SET_LATENCY(FLatency);
bogdanm 0:9b334a45a8ff 819
bogdanm 0:9b334a45a8ff 820 /* Check that the new number of wait states is taken into account to access the Flash
bogdanm 0:9b334a45a8ff 821 memory by reading the FLASH_ACR register */
bogdanm 0:9b334a45a8ff 822 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
bogdanm 0:9b334a45a8ff 823 {
bogdanm 0:9b334a45a8ff 824 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 825 }
bogdanm 0:9b334a45a8ff 826 }
bogdanm 0:9b334a45a8ff 827
bogdanm 0:9b334a45a8ff 828 /*-------------------------- PCLK1 Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 829 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
bogdanm 0:9b334a45a8ff 830 {
bogdanm 0:9b334a45a8ff 831 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
bogdanm 0:9b334a45a8ff 832 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
bogdanm 0:9b334a45a8ff 833 }
bogdanm 0:9b334a45a8ff 834
bogdanm 0:9b334a45a8ff 835 /*-------------------------- PCLK2 Configuration ---------------------------*/
bogdanm 0:9b334a45a8ff 836 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
bogdanm 0:9b334a45a8ff 837 {
bogdanm 0:9b334a45a8ff 838 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
bogdanm 0:9b334a45a8ff 839 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
bogdanm 0:9b334a45a8ff 840 }
bogdanm 0:9b334a45a8ff 841
bogdanm 0:9b334a45a8ff 842 /* Configure the source of time base considering new system clocks settings*/
bogdanm 0:9b334a45a8ff 843 HAL_InitTick (TICK_INT_PRIORITY);
bogdanm 0:9b334a45a8ff 844
bogdanm 0:9b334a45a8ff 845 return HAL_OK;
bogdanm 0:9b334a45a8ff 846 }
bogdanm 0:9b334a45a8ff 847 /**
bogdanm 0:9b334a45a8ff 848 * @}
bogdanm 0:9b334a45a8ff 849 */
bogdanm 0:9b334a45a8ff 850
bogdanm 0:9b334a45a8ff 851 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 852
bogdanm 0:9b334a45a8ff 853 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 854 /** @addtogroup RCC_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 855 * @{
bogdanm 0:9b334a45a8ff 856 */
bogdanm 0:9b334a45a8ff 857
bogdanm 0:9b334a45a8ff 858 /**
bogdanm 0:9b334a45a8ff 859 * @brief Returns the SYSCLK frequency
bogdanm 0:9b334a45a8ff 860 *
bogdanm 0:9b334a45a8ff 861 * @note The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 862 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 863 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 864 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 865 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
bogdanm 0:9b334a45a8ff 866 * divided by PREDIV factor(**)
bogdanm 0:9b334a45a8ff 867 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
bogdanm 0:9b334a45a8ff 868 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
bogdanm 0:9b334a45a8ff 869 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 870 * 8 MHz).
bogdanm 0:9b334a45a8ff 871 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 872 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 873 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 874 * have wrong result.
bogdanm 0:9b334a45a8ff 875 *
bogdanm 0:9b334a45a8ff 876 * @note The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 877 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 878 *
bogdanm 0:9b334a45a8ff 879 * @note This function can be used by the user application to compute the
bogdanm 0:9b334a45a8ff 880 * baudrate for the communication peripherals or configure other parameters.
bogdanm 0:9b334a45a8ff 881 *
bogdanm 0:9b334a45a8ff 882 * @note Each time SYSCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 883 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 884 *
bogdanm 0:9b334a45a8ff 885 *
bogdanm 0:9b334a45a8ff 886 * @retval SYSCLK frequency
bogdanm 0:9b334a45a8ff 887 */
bogdanm 0:9b334a45a8ff 888 uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm 0:9b334a45a8ff 889 {
bogdanm 0:9b334a45a8ff 890 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
bogdanm 0:9b334a45a8ff 891 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
bogdanm 0:9b334a45a8ff 892
bogdanm 0:9b334a45a8ff 893 uint32_t tmp_reg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
bogdanm 0:9b334a45a8ff 894 uint32_t sysclockfreq = 0;
bogdanm 0:9b334a45a8ff 895 uint32_t prediv2 = 0, pll2mul = 0;
bogdanm 0:9b334a45a8ff 896
bogdanm 0:9b334a45a8ff 897 tmp_reg = RCC->CFGR;
bogdanm 0:9b334a45a8ff 898
bogdanm 0:9b334a45a8ff 899 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 900 switch (tmp_reg & RCC_CFGR_SWS)
bogdanm 0:9b334a45a8ff 901 {
bogdanm 0:9b334a45a8ff 902 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
bogdanm 0:9b334a45a8ff 903 {
bogdanm 0:9b334a45a8ff 904 sysclockfreq = HSE_VALUE;
bogdanm 0:9b334a45a8ff 905 break;
bogdanm 0:9b334a45a8ff 906 }
bogdanm 0:9b334a45a8ff 907 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
bogdanm 0:9b334a45a8ff 908 {
bogdanm 0:9b334a45a8ff 909 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
bogdanm 0:9b334a45a8ff 910
bogdanm 0:9b334a45a8ff 911 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
bogdanm 0:9b334a45a8ff 912 {
bogdanm 0:9b334a45a8ff 913 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
bogdanm 0:9b334a45a8ff 914 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
bogdanm 0:9b334a45a8ff 915 {
bogdanm 0:9b334a45a8ff 916 /* PLL2 selected as Prediv1 source */
bogdanm 0:9b334a45a8ff 917 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
bogdanm 0:9b334a45a8ff 918 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
bogdanm 0:9b334a45a8ff 919 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
bogdanm 0:9b334a45a8ff 920 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922 else
bogdanm 0:9b334a45a8ff 923 {
bogdanm 0:9b334a45a8ff 924 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
bogdanm 0:9b334a45a8ff 925 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
bogdanm 0:9b334a45a8ff 926 }
bogdanm 0:9b334a45a8ff 927
bogdanm 0:9b334a45a8ff 928 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
bogdanm 0:9b334a45a8ff 929 /* In this case need to divide pllclk by 2 */
bogdanm 0:9b334a45a8ff 930 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
bogdanm 0:9b334a45a8ff 931 {
bogdanm 0:9b334a45a8ff 932 pllclk = pllclk / 2;
bogdanm 0:9b334a45a8ff 933 }
bogdanm 0:9b334a45a8ff 934 }
bogdanm 0:9b334a45a8ff 935 else
bogdanm 0:9b334a45a8ff 936 {
bogdanm 0:9b334a45a8ff 937 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
bogdanm 0:9b334a45a8ff 938 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
bogdanm 0:9b334a45a8ff 939 }
bogdanm 0:9b334a45a8ff 940 sysclockfreq = pllclk;
bogdanm 0:9b334a45a8ff 941 break;
bogdanm 0:9b334a45a8ff 942 }
bogdanm 0:9b334a45a8ff 943 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 944 default: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 945 {
bogdanm 0:9b334a45a8ff 946 sysclockfreq = HSI_VALUE;
bogdanm 0:9b334a45a8ff 947 break;
bogdanm 0:9b334a45a8ff 948 }
bogdanm 0:9b334a45a8ff 949 }
bogdanm 0:9b334a45a8ff 950 return sysclockfreq;
bogdanm 0:9b334a45a8ff 951 }
bogdanm 0:9b334a45a8ff 952
bogdanm 0:9b334a45a8ff 953
bogdanm 0:9b334a45a8ff 954 /**
bogdanm 0:9b334a45a8ff 955 * @brief Configures the RCC_OscInitStruct according to the internal
bogdanm 0:9b334a45a8ff 956 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 957 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 958 * will be configured.
bogdanm 0:9b334a45a8ff 959 * @retval None
bogdanm 0:9b334a45a8ff 960 */
bogdanm 0:9b334a45a8ff 961 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 962 {
bogdanm 0:9b334a45a8ff 963 /* Check the parameters */
bogdanm 0:9b334a45a8ff 964 assert_param(RCC_OscInitStruct != NULL);
bogdanm 0:9b334a45a8ff 965
bogdanm 0:9b334a45a8ff 966 /* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm 0:9b334a45a8ff 967 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
bogdanm 0:9b334a45a8ff 968 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
bogdanm 0:9b334a45a8ff 969
bogdanm 0:9b334a45a8ff 970 /* Get the Prediv1 source --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 971 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
bogdanm 0:9b334a45a8ff 972
bogdanm 0:9b334a45a8ff 973 /* Get the HSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 974 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm 0:9b334a45a8ff 975 {
bogdanm 0:9b334a45a8ff 976 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm 0:9b334a45a8ff 977 }
bogdanm 0:9b334a45a8ff 978 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm 0:9b334a45a8ff 979 {
bogdanm 0:9b334a45a8ff 980 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm 0:9b334a45a8ff 981 }
bogdanm 0:9b334a45a8ff 982 else
bogdanm 0:9b334a45a8ff 983 {
bogdanm 0:9b334a45a8ff 984 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 985 }
bogdanm 0:9b334a45a8ff 986
bogdanm 0:9b334a45a8ff 987 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
bogdanm 0:9b334a45a8ff 988
bogdanm 0:9b334a45a8ff 989 /* Get the HSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 990 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
bogdanm 0:9b334a45a8ff 991 {
bogdanm 0:9b334a45a8ff 992 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 993 }
bogdanm 0:9b334a45a8ff 994 else
bogdanm 0:9b334a45a8ff 995 {
bogdanm 0:9b334a45a8ff 996 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 997 }
bogdanm 0:9b334a45a8ff 998
bogdanm 0:9b334a45a8ff 999 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
bogdanm 0:9b334a45a8ff 1000
bogdanm 0:9b334a45a8ff 1001 /* Get the LSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1002 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
bogdanm 0:9b334a45a8ff 1003 {
bogdanm 0:9b334a45a8ff 1004 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm 0:9b334a45a8ff 1005 }
bogdanm 0:9b334a45a8ff 1006 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
bogdanm 0:9b334a45a8ff 1007 {
bogdanm 0:9b334a45a8ff 1008 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm 0:9b334a45a8ff 1009 }
bogdanm 0:9b334a45a8ff 1010 else
bogdanm 0:9b334a45a8ff 1011 {
bogdanm 0:9b334a45a8ff 1012 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm 0:9b334a45a8ff 1013 }
bogdanm 0:9b334a45a8ff 1014
bogdanm 0:9b334a45a8ff 1015 /* Get the LSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1016 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm 0:9b334a45a8ff 1017 {
bogdanm 0:9b334a45a8ff 1018 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm 0:9b334a45a8ff 1019 }
bogdanm 0:9b334a45a8ff 1020 else
bogdanm 0:9b334a45a8ff 1021 {
bogdanm 0:9b334a45a8ff 1022 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm 0:9b334a45a8ff 1023 }
bogdanm 0:9b334a45a8ff 1024
bogdanm 0:9b334a45a8ff 1025 /* Get the PLL configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1026 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm 0:9b334a45a8ff 1027 {
bogdanm 0:9b334a45a8ff 1028 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 1029 }
bogdanm 0:9b334a45a8ff 1030 else
bogdanm 0:9b334a45a8ff 1031 {
bogdanm 0:9b334a45a8ff 1032 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm 0:9b334a45a8ff 1033 }
bogdanm 0:9b334a45a8ff 1034 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
bogdanm 0:9b334a45a8ff 1035 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
bogdanm 0:9b334a45a8ff 1036
bogdanm 0:9b334a45a8ff 1037 /* Get the PLL2 configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1038 if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
bogdanm 0:9b334a45a8ff 1039 {
bogdanm 0:9b334a45a8ff 1040 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
bogdanm 0:9b334a45a8ff 1041 }
bogdanm 0:9b334a45a8ff 1042 else
bogdanm 0:9b334a45a8ff 1043 {
bogdanm 0:9b334a45a8ff 1044 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
bogdanm 0:9b334a45a8ff 1045 }
bogdanm 0:9b334a45a8ff 1046 RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
bogdanm 0:9b334a45a8ff 1047 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
bogdanm 0:9b334a45a8ff 1048 }
bogdanm 0:9b334a45a8ff 1049
bogdanm 0:9b334a45a8ff 1050 /**
bogdanm 0:9b334a45a8ff 1051 * @}
bogdanm 0:9b334a45a8ff 1052 */
bogdanm 0:9b334a45a8ff 1053
bogdanm 0:9b334a45a8ff 1054 #endif /* STM32F105xC || STM32F107xC*/
bogdanm 0:9b334a45a8ff 1055
bogdanm 0:9b334a45a8ff 1056 #if defined (STM32F100xB) || defined (STM32F100xE)
bogdanm 0:9b334a45a8ff 1057 /** @addtogroup RCC_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 1058 * @{
bogdanm 0:9b334a45a8ff 1059 */
bogdanm 0:9b334a45a8ff 1060
bogdanm 0:9b334a45a8ff 1061 /**
bogdanm 0:9b334a45a8ff 1062 * @brief Returns the SYSCLK frequency
bogdanm 0:9b334a45a8ff 1063 *
bogdanm 0:9b334a45a8ff 1064 * @note The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 1065 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 1066 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 1067 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 1068 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
bogdanm 0:9b334a45a8ff 1069 * divided by PREDIV factor(**)
bogdanm 0:9b334a45a8ff 1070 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
bogdanm 0:9b334a45a8ff 1071 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
bogdanm 0:9b334a45a8ff 1072 * @note (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
bogdanm 0:9b334a45a8ff 1073 * 8 MHz).
bogdanm 0:9b334a45a8ff 1074 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
bogdanm 0:9b334a45a8ff 1075 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 1076 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 1077 * have wrong result.
bogdanm 0:9b334a45a8ff 1078 *
bogdanm 0:9b334a45a8ff 1079 * @note The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 1080 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 1081 *
bogdanm 0:9b334a45a8ff 1082 * @note This function can be used by the user application to compute the
bogdanm 0:9b334a45a8ff 1083 * baudrate for the communication peripherals or configure other parameters.
bogdanm 0:9b334a45a8ff 1084 *
bogdanm 0:9b334a45a8ff 1085 * @note Each time SYSCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 1086 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 1087 *
bogdanm 0:9b334a45a8ff 1088 *
bogdanm 0:9b334a45a8ff 1089 * @retval SYSCLK frequency
bogdanm 0:9b334a45a8ff 1090 */
bogdanm 0:9b334a45a8ff 1091 uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm 0:9b334a45a8ff 1092 {
bogdanm 0:9b334a45a8ff 1093 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
bogdanm 0:9b334a45a8ff 1094 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
bogdanm 0:9b334a45a8ff 1095 uint32_t tmp_reg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
bogdanm 0:9b334a45a8ff 1096 uint32_t sysclockfreq = 0;
bogdanm 0:9b334a45a8ff 1097
bogdanm 0:9b334a45a8ff 1098 tmp_reg = RCC->CFGR;
bogdanm 0:9b334a45a8ff 1099
bogdanm 0:9b334a45a8ff 1100 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1101 switch (tmp_reg & RCC_CFGR_SWS)
bogdanm 0:9b334a45a8ff 1102 {
bogdanm 0:9b334a45a8ff 1103 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
bogdanm 0:9b334a45a8ff 1104 {
bogdanm 0:9b334a45a8ff 1105 sysclockfreq = HSE_VALUE;
bogdanm 0:9b334a45a8ff 1106 break;
bogdanm 0:9b334a45a8ff 1107 }
bogdanm 0:9b334a45a8ff 1108 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
bogdanm 0:9b334a45a8ff 1109 {
bogdanm 0:9b334a45a8ff 1110 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
bogdanm 0:9b334a45a8ff 1111 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
bogdanm 0:9b334a45a8ff 1112 {
bogdanm 0:9b334a45a8ff 1113 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
bogdanm 0:9b334a45a8ff 1114 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
bogdanm 0:9b334a45a8ff 1115 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
bogdanm 0:9b334a45a8ff 1116 }
bogdanm 0:9b334a45a8ff 1117 else
bogdanm 0:9b334a45a8ff 1118 {
bogdanm 0:9b334a45a8ff 1119 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
bogdanm 0:9b334a45a8ff 1120 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
bogdanm 0:9b334a45a8ff 1121 }
bogdanm 0:9b334a45a8ff 1122 sysclockfreq = pllclk;
bogdanm 0:9b334a45a8ff 1123 break;
bogdanm 0:9b334a45a8ff 1124 }
bogdanm 0:9b334a45a8ff 1125 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 1126 default: /* HSI used as system clock */
bogdanm 0:9b334a45a8ff 1127 {
bogdanm 0:9b334a45a8ff 1128 sysclockfreq = HSI_VALUE;
bogdanm 0:9b334a45a8ff 1129 break;
bogdanm 0:9b334a45a8ff 1130 }
bogdanm 0:9b334a45a8ff 1131 }
bogdanm 0:9b334a45a8ff 1132 return sysclockfreq;
bogdanm 0:9b334a45a8ff 1133 }
bogdanm 0:9b334a45a8ff 1134 /**
bogdanm 0:9b334a45a8ff 1135 * @}
bogdanm 0:9b334a45a8ff 1136 */
bogdanm 0:9b334a45a8ff 1137
bogdanm 0:9b334a45a8ff 1138 #endif /* STM32F100xB || STM32F100xE*/
bogdanm 0:9b334a45a8ff 1139
bogdanm 0:9b334a45a8ff 1140 #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
bogdanm 0:9b334a45a8ff 1141 defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \
bogdanm 0:9b334a45a8ff 1142 defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1143 /** @addtogroup RCC_Exported_Functions_Group2
bogdanm 0:9b334a45a8ff 1144 * @{
bogdanm 0:9b334a45a8ff 1145 */
bogdanm 0:9b334a45a8ff 1146
bogdanm 0:9b334a45a8ff 1147 /**
bogdanm 0:9b334a45a8ff 1148 * @brief Configures the RCC_ClkInitStruct according to the internal
bogdanm 0:9b334a45a8ff 1149 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 1150 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1151 * will be configured.
bogdanm 0:9b334a45a8ff 1152 * @param pFLatency: Pointer on the Flash Latency.
bogdanm 0:9b334a45a8ff 1153 * @retval None
bogdanm 0:9b334a45a8ff 1154 */
bogdanm 0:9b334a45a8ff 1155 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
bogdanm 0:9b334a45a8ff 1156 {
bogdanm 0:9b334a45a8ff 1157 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1158 assert_param(RCC_ClkInitStruct != NULL);
bogdanm 0:9b334a45a8ff 1159 assert_param(pFLatency != NULL);
bogdanm 0:9b334a45a8ff 1160
bogdanm 0:9b334a45a8ff 1161 /* Set all possible values for the Clock type parameter --------------------*/
bogdanm 0:9b334a45a8ff 1162 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
bogdanm 0:9b334a45a8ff 1163
bogdanm 0:9b334a45a8ff 1164 /* Get the SYSCLK configuration --------------------------------------------*/
bogdanm 0:9b334a45a8ff 1165 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
bogdanm 0:9b334a45a8ff 1166
bogdanm 0:9b334a45a8ff 1167 /* Get the HCLK configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1168 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
bogdanm 0:9b334a45a8ff 1169
bogdanm 0:9b334a45a8ff 1170 /* Get the APB1 configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1171 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
bogdanm 0:9b334a45a8ff 1172
bogdanm 0:9b334a45a8ff 1173 /* Get the APB2 configuration ----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1174 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
bogdanm 0:9b334a45a8ff 1175
bogdanm 0:9b334a45a8ff 1176 /* Get the Flash Wait State (Latency) configuration ------------------------*/
bogdanm 0:9b334a45a8ff 1177 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
bogdanm 0:9b334a45a8ff 1178 }
bogdanm 0:9b334a45a8ff 1179 /**
bogdanm 0:9b334a45a8ff 1180 * @}
bogdanm 0:9b334a45a8ff 1181 */
bogdanm 0:9b334a45a8ff 1182
bogdanm 0:9b334a45a8ff 1183 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1184
bogdanm 0:9b334a45a8ff 1185 /**
bogdanm 0:9b334a45a8ff 1186 * @}
bogdanm 0:9b334a45a8ff 1187 */
bogdanm 0:9b334a45a8ff 1188
bogdanm 0:9b334a45a8ff 1189 /**
bogdanm 0:9b334a45a8ff 1190 * @}
bogdanm 0:9b334a45a8ff 1191 */
bogdanm 0:9b334a45a8ff 1192
bogdanm 0:9b334a45a8ff 1193 /** @addtogroup RCCEx
bogdanm 0:9b334a45a8ff 1194 * @{
bogdanm 0:9b334a45a8ff 1195 */
bogdanm 0:9b334a45a8ff 1196
bogdanm 0:9b334a45a8ff 1197 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
bogdanm 0:9b334a45a8ff 1198 * @{
bogdanm 0:9b334a45a8ff 1199 */
bogdanm 0:9b334a45a8ff 1200
bogdanm 0:9b334a45a8ff 1201 /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
bogdanm 0:9b334a45a8ff 1202 * @brief Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 1203 *
bogdanm 0:9b334a45a8ff 1204 @verbatim
bogdanm 0:9b334a45a8ff 1205 ===============================================================================
bogdanm 0:9b334a45a8ff 1206 ##### Extended Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 1207 ===============================================================================
bogdanm 0:9b334a45a8ff 1208 [..]
bogdanm 0:9b334a45a8ff 1209 This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm 0:9b334a45a8ff 1210 frequencies.
bogdanm 0:9b334a45a8ff 1211 [..]
bogdanm 0:9b334a45a8ff 1212 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
bogdanm 0:9b334a45a8ff 1213 select the RTC clock source; in this case the Backup domain will be reset in
bogdanm 0:9b334a45a8ff 1214 order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm 0:9b334a45a8ff 1215 the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm 0:9b334a45a8ff 1216
bogdanm 0:9b334a45a8ff 1217 @endverbatim
bogdanm 0:9b334a45a8ff 1218 * @{
bogdanm 0:9b334a45a8ff 1219 */
bogdanm 0:9b334a45a8ff 1220
bogdanm 0:9b334a45a8ff 1221 /**
bogdanm 0:9b334a45a8ff 1222 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
bogdanm 0:9b334a45a8ff 1223 * RCC_PeriphCLKInitTypeDef.
bogdanm 0:9b334a45a8ff 1224 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1225 * contains the configuration information for the Extended Peripherals clocks(RTC clock).
bogdanm 0:9b334a45a8ff 1226 *
bogdanm 0:9b334a45a8ff 1227 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
bogdanm 0:9b334a45a8ff 1228 * the RTC clock source; in this case the Backup domain will be reset in
bogdanm 0:9b334a45a8ff 1229 * order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm 0:9b334a45a8ff 1230 * the backup registers) are set to their reset values.
bogdanm 0:9b334a45a8ff 1231 *
bogdanm 0:9b334a45a8ff 1232 * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
bogdanm 0:9b334a45a8ff 1233 * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
bogdanm 0:9b334a45a8ff 1234 * manually disable it.
bogdanm 0:9b334a45a8ff 1235 *
bogdanm 0:9b334a45a8ff 1236 * @retval HAL status
bogdanm 0:9b334a45a8ff 1237 */
bogdanm 0:9b334a45a8ff 1238 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm 0:9b334a45a8ff 1239 {
bogdanm 0:9b334a45a8ff 1240 uint32_t tickstart = 0, tmp_reg = 0;
bogdanm 0:9b334a45a8ff 1241 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1242 uint32_t pllactive = 0;
bogdanm 0:9b334a45a8ff 1243 #endif /* STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1244
bogdanm 0:9b334a45a8ff 1245 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1246 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
bogdanm 0:9b334a45a8ff 1247
bogdanm 0:9b334a45a8ff 1248 /*------------------------------- RTC/LCD Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 1249 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
bogdanm 0:9b334a45a8ff 1250 {
bogdanm 0:9b334a45a8ff 1251 /* Enable Power Controller clock */
bogdanm 0:9b334a45a8ff 1252 __HAL_RCC_PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 1253
bogdanm 0:9b334a45a8ff 1254 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 1255 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 1256
bogdanm 0:9b334a45a8ff 1257 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 1258 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1259
bogdanm 0:9b334a45a8ff 1260 while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm 0:9b334a45a8ff 1261 {
bogdanm 0:9b334a45a8ff 1262 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1263 {
bogdanm 0:9b334a45a8ff 1264 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1265 }
bogdanm 0:9b334a45a8ff 1266 }
bogdanm 0:9b334a45a8ff 1267
bogdanm 0:9b334a45a8ff 1268 tmp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
bogdanm 0:9b334a45a8ff 1269 /* Reset the Backup domain only if the RTC Clock source selection is modified */
bogdanm 0:9b334a45a8ff 1270 if((tmp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
bogdanm 0:9b334a45a8ff 1271 {
bogdanm 0:9b334a45a8ff 1272 /* Store the content of BDCR register before the reset of Backup Domain */
bogdanm 0:9b334a45a8ff 1273 tmp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm 0:9b334a45a8ff 1274 /* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm 0:9b334a45a8ff 1275 __HAL_RCC_BACKUPRESET_FORCE();
bogdanm 0:9b334a45a8ff 1276 __HAL_RCC_BACKUPRESET_RELEASE();
bogdanm 0:9b334a45a8ff 1277 /* Restore the Content of BDCR register */
bogdanm 0:9b334a45a8ff 1278 RCC->BDCR = tmp_reg;
bogdanm 0:9b334a45a8ff 1279 }
bogdanm 0:9b334a45a8ff 1280
bogdanm 0:9b334a45a8ff 1281 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
bogdanm 0:9b334a45a8ff 1282 if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE))
bogdanm 0:9b334a45a8ff 1283 {
bogdanm 0:9b334a45a8ff 1284 /* Get timeout */
bogdanm 0:9b334a45a8ff 1285 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1286
bogdanm 0:9b334a45a8ff 1287 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 1288 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 1289 {
bogdanm 0:9b334a45a8ff 1290 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1291 {
bogdanm 0:9b334a45a8ff 1292 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1293 }
bogdanm 0:9b334a45a8ff 1294 }
bogdanm 0:9b334a45a8ff 1295 }
bogdanm 0:9b334a45a8ff 1296
bogdanm 0:9b334a45a8ff 1297 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm 0:9b334a45a8ff 1298 }
bogdanm 0:9b334a45a8ff 1299
bogdanm 0:9b334a45a8ff 1300 /*------------------------------ ADC clock Configuration ------------------*/
bogdanm 0:9b334a45a8ff 1301 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
bogdanm 0:9b334a45a8ff 1302 {
bogdanm 0:9b334a45a8ff 1303 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1304 assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
bogdanm 0:9b334a45a8ff 1305
bogdanm 0:9b334a45a8ff 1306 /* Configure the ADC clock source */
bogdanm 0:9b334a45a8ff 1307 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
bogdanm 0:9b334a45a8ff 1308 }
bogdanm 0:9b334a45a8ff 1309
bogdanm 0:9b334a45a8ff 1310 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1311 /*------------------------------ I2S2 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 1312 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
bogdanm 0:9b334a45a8ff 1313 {
bogdanm 0:9b334a45a8ff 1314 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1315 assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
bogdanm 0:9b334a45a8ff 1316
bogdanm 0:9b334a45a8ff 1317 /* Configure the I2S2 clock source */
bogdanm 0:9b334a45a8ff 1318 __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
bogdanm 0:9b334a45a8ff 1319 }
bogdanm 0:9b334a45a8ff 1320
bogdanm 0:9b334a45a8ff 1321 /*------------------------------ I2S3 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 1322 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
bogdanm 0:9b334a45a8ff 1323 {
bogdanm 0:9b334a45a8ff 1324 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1325 assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
bogdanm 0:9b334a45a8ff 1326
bogdanm 0:9b334a45a8ff 1327 /* Configure the I2S3 clock source */
bogdanm 0:9b334a45a8ff 1328 __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
bogdanm 0:9b334a45a8ff 1329 }
bogdanm 0:9b334a45a8ff 1330
bogdanm 0:9b334a45a8ff 1331 /*------------------------------ PLL I2S Configuration ----------------------*/
bogdanm 0:9b334a45a8ff 1332 /* Check that PLLI2S need to be enabled */
bogdanm 0:9b334a45a8ff 1333 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
bogdanm 0:9b334a45a8ff 1334 {
bogdanm 0:9b334a45a8ff 1335 /* Update flag to indicate that PLL I2S should be active */
bogdanm 0:9b334a45a8ff 1336 pllactive = 1;
bogdanm 0:9b334a45a8ff 1337 }
bogdanm 0:9b334a45a8ff 1338
bogdanm 0:9b334a45a8ff 1339 /* Check if PLL I2S need to be enabled */
bogdanm 0:9b334a45a8ff 1340 if (pllactive == 1)
bogdanm 0:9b334a45a8ff 1341 {
bogdanm 0:9b334a45a8ff 1342 /* Enable PLL I2S only if not active */
bogdanm 0:9b334a45a8ff 1343 if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
bogdanm 0:9b334a45a8ff 1344 {
bogdanm 0:9b334a45a8ff 1345 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1346 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
bogdanm 0:9b334a45a8ff 1347 assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
bogdanm 0:9b334a45a8ff 1348
bogdanm 0:9b334a45a8ff 1349 /* Prediv2 can be written only when the PLL2 is disabled. */
bogdanm 0:9b334a45a8ff 1350 /* Return an error only if new value is different from the programmed value */
bogdanm 0:9b334a45a8ff 1351 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
bogdanm 0:9b334a45a8ff 1352 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
bogdanm 0:9b334a45a8ff 1353 {
bogdanm 0:9b334a45a8ff 1354 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1355 }
bogdanm 0:9b334a45a8ff 1356
bogdanm 0:9b334a45a8ff 1357 /* Configure the HSE prediv2 factor --------------------------------*/
bogdanm 0:9b334a45a8ff 1358 __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
bogdanm 0:9b334a45a8ff 1359
bogdanm 0:9b334a45a8ff 1360 /* Configure the main PLLI2S multiplication factors. */
bogdanm 0:9b334a45a8ff 1361 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
bogdanm 0:9b334a45a8ff 1362
bogdanm 0:9b334a45a8ff 1363 /* Enable the main PLLI2S. */
bogdanm 0:9b334a45a8ff 1364 __HAL_RCC_PLLI2S_ENABLE();
bogdanm 0:9b334a45a8ff 1365
bogdanm 0:9b334a45a8ff 1366 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 1367 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1368
bogdanm 0:9b334a45a8ff 1369 /* Wait till PLLI2S is ready */
bogdanm 0:9b334a45a8ff 1370 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
bogdanm 0:9b334a45a8ff 1371 {
bogdanm 0:9b334a45a8ff 1372 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1373 {
bogdanm 0:9b334a45a8ff 1374 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1375 }
bogdanm 0:9b334a45a8ff 1376 }
bogdanm 0:9b334a45a8ff 1377 }
bogdanm 0:9b334a45a8ff 1378 else
bogdanm 0:9b334a45a8ff 1379 {
bogdanm 0:9b334a45a8ff 1380 /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
bogdanm 0:9b334a45a8ff 1381 if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
bogdanm 0:9b334a45a8ff 1382 {
bogdanm 0:9b334a45a8ff 1383 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1384 }
bogdanm 0:9b334a45a8ff 1385 }
bogdanm 0:9b334a45a8ff 1386 }
bogdanm 0:9b334a45a8ff 1387 #endif /* STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1388
bogdanm 0:9b334a45a8ff 1389 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
bogdanm 0:9b334a45a8ff 1390 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1391 /*------------------------------ USB clock Configuration ------------------*/
bogdanm 0:9b334a45a8ff 1392 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
bogdanm 0:9b334a45a8ff 1393 {
bogdanm 0:9b334a45a8ff 1394 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1395 assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
bogdanm 0:9b334a45a8ff 1396
bogdanm 0:9b334a45a8ff 1397 /* Configure the USB clock source */
bogdanm 0:9b334a45a8ff 1398 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
bogdanm 0:9b334a45a8ff 1399 }
bogdanm 0:9b334a45a8ff 1400 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1401
bogdanm 0:9b334a45a8ff 1402 return HAL_OK;
bogdanm 0:9b334a45a8ff 1403 }
bogdanm 0:9b334a45a8ff 1404
bogdanm 0:9b334a45a8ff 1405 /**
bogdanm 0:9b334a45a8ff 1406 * @brief Get the PeriphClkInit according to the internal
bogdanm 0:9b334a45a8ff 1407 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 1408 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1409 * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
bogdanm 0:9b334a45a8ff 1410 * @retval None
bogdanm 0:9b334a45a8ff 1411 */
bogdanm 0:9b334a45a8ff 1412 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm 0:9b334a45a8ff 1413 {
bogdanm 0:9b334a45a8ff 1414 uint32_t srcclk = 0;
bogdanm 0:9b334a45a8ff 1415
bogdanm 0:9b334a45a8ff 1416 /* Set all possible values for the extended clock type parameter------------*/
bogdanm 0:9b334a45a8ff 1417 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
bogdanm 0:9b334a45a8ff 1418
bogdanm 0:9b334a45a8ff 1419 /* Get the RTC configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1420 srcclk = __HAL_RCC_GET_RTC_SOURCE();
bogdanm 0:9b334a45a8ff 1421 /* Source clock is LSE or LSI*/
bogdanm 0:9b334a45a8ff 1422 PeriphClkInit->RTCClockSelection = srcclk;
bogdanm 0:9b334a45a8ff 1423
bogdanm 0:9b334a45a8ff 1424 /* Get the ADC clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 1425 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
bogdanm 0:9b334a45a8ff 1426 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
bogdanm 0:9b334a45a8ff 1427
bogdanm 0:9b334a45a8ff 1428 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1429 /* Get the I2S2 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 1430 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
bogdanm 0:9b334a45a8ff 1431 PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
bogdanm 0:9b334a45a8ff 1432
bogdanm 0:9b334a45a8ff 1433 /* Get the I2S3 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 1434 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
bogdanm 0:9b334a45a8ff 1435 PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
bogdanm 0:9b334a45a8ff 1436
bogdanm 0:9b334a45a8ff 1437 #endif /* STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1438
bogdanm 0:9b334a45a8ff 1439 #if defined(STM32F103xE) || defined(STM32F103xG)
bogdanm 0:9b334a45a8ff 1440 /* Get the I2S2 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 1441 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
bogdanm 0:9b334a45a8ff 1442 PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
bogdanm 0:9b334a45a8ff 1443
bogdanm 0:9b334a45a8ff 1444 /* Get the I2S3 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 1445 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
bogdanm 0:9b334a45a8ff 1446 PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
bogdanm 0:9b334a45a8ff 1447
bogdanm 0:9b334a45a8ff 1448 #endif /* STM32F103xE || STM32F103xG */
bogdanm 0:9b334a45a8ff 1449
bogdanm 0:9b334a45a8ff 1450 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
bogdanm 0:9b334a45a8ff 1451 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1452 /* Get the USB clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 1453 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
bogdanm 0:9b334a45a8ff 1454 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
bogdanm 0:9b334a45a8ff 1455 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1456 }
bogdanm 0:9b334a45a8ff 1457
bogdanm 0:9b334a45a8ff 1458 /**
bogdanm 0:9b334a45a8ff 1459 * @brief Returns the peripheral clock frequency
bogdanm 0:9b334a45a8ff 1460 * @note Returns 0 if peripheral clock is unknown
bogdanm 0:9b334a45a8ff 1461 * @param PeriphClk: Peripheral clock identifier
bogdanm 0:9b334a45a8ff 1462 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 1463 * @arg RCC_PERIPHCLK_RTC: RTC peripheral clock
bogdanm 0:9b334a45a8ff 1464 * @arg RCC_PERIPHCLK_ADC: ADC peripheral clock
bogdanm 0:9b334a45a8ff 1465 * @arg RCC_PERIPHCLK_I2S2: I2S2 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC)
bogdanm 0:9b334a45a8ff 1466 * @arg RCC_PERIPHCLK_I2S3: I2S3 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC)
bogdanm 0:9b334a45a8ff 1467 * @arg RCC_PERIPHCLK_USB: USB peripheral clock (STM32F102xx, STM32F103xx, STM32F105xC & STM32F107xC)
bogdanm 0:9b334a45a8ff 1468 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
bogdanm 0:9b334a45a8ff 1469 */
bogdanm 0:9b334a45a8ff 1470 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
bogdanm 0:9b334a45a8ff 1471 {
bogdanm 0:9b334a45a8ff 1472 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
bogdanm 0:9b334a45a8ff 1473 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1474 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1475 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
bogdanm 0:9b334a45a8ff 1476 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
bogdanm 0:9b334a45a8ff 1477 #else
bogdanm 0:9b334a45a8ff 1478 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
bogdanm 0:9b334a45a8ff 1479 const uint8_t aPredivFactorTable[2] = { 1, 2};
bogdanm 0:9b334a45a8ff 1480 #endif
bogdanm 0:9b334a45a8ff 1481 #endif
bogdanm 0:9b334a45a8ff 1482 uint32_t tmp_reg = 0, frequency = 0;
bogdanm 0:9b334a45a8ff 1483 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
bogdanm 0:9b334a45a8ff 1484 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1485 uint32_t prediv1 = 0, pllclk = 0, pllmul = 0;
bogdanm 0:9b334a45a8ff 1486 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1487 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1488 uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0;
bogdanm 0:9b334a45a8ff 1489 #endif /* STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1490
bogdanm 0:9b334a45a8ff 1491 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1492 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
bogdanm 0:9b334a45a8ff 1493
bogdanm 0:9b334a45a8ff 1494 switch (PeriphClk)
bogdanm 0:9b334a45a8ff 1495 {
bogdanm 0:9b334a45a8ff 1496 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
bogdanm 0:9b334a45a8ff 1497 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1498 case RCC_PERIPHCLK_USB:
bogdanm 0:9b334a45a8ff 1499 {
bogdanm 0:9b334a45a8ff 1500 /* Get RCC configuration ------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1501 tmp_reg = RCC->CFGR;
bogdanm 0:9b334a45a8ff 1502
bogdanm 0:9b334a45a8ff 1503 /* Check if PLL is enabled */
bogdanm 0:9b334a45a8ff 1504 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
bogdanm 0:9b334a45a8ff 1505 {
bogdanm 0:9b334a45a8ff 1506 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
bogdanm 0:9b334a45a8ff 1507 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
bogdanm 0:9b334a45a8ff 1508 {
bogdanm 0:9b334a45a8ff 1509 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
bogdanm 0:9b334a45a8ff 1510 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
bogdanm 0:9b334a45a8ff 1511 #else
bogdanm 0:9b334a45a8ff 1512 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
bogdanm 0:9b334a45a8ff 1513 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
bogdanm 0:9b334a45a8ff 1514
bogdanm 0:9b334a45a8ff 1515 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1516 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
bogdanm 0:9b334a45a8ff 1517 {
bogdanm 0:9b334a45a8ff 1518 /* PLL2 selected as Prediv1 source */
bogdanm 0:9b334a45a8ff 1519 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
bogdanm 0:9b334a45a8ff 1520 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
bogdanm 0:9b334a45a8ff 1521 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
bogdanm 0:9b334a45a8ff 1522 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
bogdanm 0:9b334a45a8ff 1523 }
bogdanm 0:9b334a45a8ff 1524 else
bogdanm 0:9b334a45a8ff 1525 {
bogdanm 0:9b334a45a8ff 1526 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
bogdanm 0:9b334a45a8ff 1527 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
bogdanm 0:9b334a45a8ff 1528 }
bogdanm 0:9b334a45a8ff 1529
bogdanm 0:9b334a45a8ff 1530 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
bogdanm 0:9b334a45a8ff 1531 /* In this case need to divide pllclk by 2 */
bogdanm 0:9b334a45a8ff 1532 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
bogdanm 0:9b334a45a8ff 1533 {
bogdanm 0:9b334a45a8ff 1534 pllclk = pllclk / 2;
bogdanm 0:9b334a45a8ff 1535 }
bogdanm 0:9b334a45a8ff 1536 #else
bogdanm 0:9b334a45a8ff 1537 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
bogdanm 0:9b334a45a8ff 1538 {
bogdanm 0:9b334a45a8ff 1539 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
bogdanm 0:9b334a45a8ff 1540 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
bogdanm 0:9b334a45a8ff 1541 }
bogdanm 0:9b334a45a8ff 1542 #endif /* STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1543 }
bogdanm 0:9b334a45a8ff 1544 else
bogdanm 0:9b334a45a8ff 1545 {
bogdanm 0:9b334a45a8ff 1546 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
bogdanm 0:9b334a45a8ff 1547 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
bogdanm 0:9b334a45a8ff 1548 }
bogdanm 0:9b334a45a8ff 1549
bogdanm 0:9b334a45a8ff 1550 /* Calcul of the USB frequency*/
bogdanm 0:9b334a45a8ff 1551 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1552 /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
bogdanm 0:9b334a45a8ff 1553 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBPLLCLK_DIV2)
bogdanm 0:9b334a45a8ff 1554 {
bogdanm 0:9b334a45a8ff 1555 /* Prescaler of 2 selected for USB */
bogdanm 0:9b334a45a8ff 1556 frequency = pllclk;
bogdanm 0:9b334a45a8ff 1557 }
bogdanm 0:9b334a45a8ff 1558 else
bogdanm 0:9b334a45a8ff 1559 {
bogdanm 0:9b334a45a8ff 1560 /* Prescaler of 3 selected for USB */
bogdanm 0:9b334a45a8ff 1561 frequency = (2 * pllclk) / 3;
bogdanm 0:9b334a45a8ff 1562 }
bogdanm 0:9b334a45a8ff 1563 #else
bogdanm 0:9b334a45a8ff 1564 /* USBCLK = PLLCLK / USB prescaler */
bogdanm 0:9b334a45a8ff 1565 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBPLLCLK_DIV1)
bogdanm 0:9b334a45a8ff 1566 {
bogdanm 0:9b334a45a8ff 1567 /* No prescaler selected for USB */
bogdanm 0:9b334a45a8ff 1568 frequency = pllclk;
bogdanm 0:9b334a45a8ff 1569 }
bogdanm 0:9b334a45a8ff 1570 else
bogdanm 0:9b334a45a8ff 1571 {
bogdanm 0:9b334a45a8ff 1572 /* Prescaler of 1.5 selected for USB */
bogdanm 0:9b334a45a8ff 1573 frequency = (pllclk * 2) / 3;
bogdanm 0:9b334a45a8ff 1574 }
bogdanm 0:9b334a45a8ff 1575 #endif
bogdanm 0:9b334a45a8ff 1576 }
bogdanm 0:9b334a45a8ff 1577 break;
bogdanm 0:9b334a45a8ff 1578 }
bogdanm 0:9b334a45a8ff 1579 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1580 #if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
bogdanm 0:9b334a45a8ff 1581 case RCC_PERIPHCLK_I2S2:
bogdanm 0:9b334a45a8ff 1582 {
bogdanm 0:9b334a45a8ff 1583 #if defined (STM32F103xE) || defined (STM32F103xG)
bogdanm 0:9b334a45a8ff 1584 /* SYSCLK used as source clock for I2S2 */
bogdanm 0:9b334a45a8ff 1585 frequency = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 1586 #else
bogdanm 0:9b334a45a8ff 1587 if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
bogdanm 0:9b334a45a8ff 1588 {
bogdanm 0:9b334a45a8ff 1589 /* SYSCLK used as source clock for I2S2 */
bogdanm 0:9b334a45a8ff 1590 frequency = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 1591 }
bogdanm 0:9b334a45a8ff 1592 else
bogdanm 0:9b334a45a8ff 1593 {
bogdanm 0:9b334a45a8ff 1594 /* Check if PLLI2S is enabled */
bogdanm 0:9b334a45a8ff 1595 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
bogdanm 0:9b334a45a8ff 1596 {
bogdanm 0:9b334a45a8ff 1597 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
bogdanm 0:9b334a45a8ff 1598 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
bogdanm 0:9b334a45a8ff 1599 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
bogdanm 0:9b334a45a8ff 1600 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
bogdanm 0:9b334a45a8ff 1601 }
bogdanm 0:9b334a45a8ff 1602 }
bogdanm 0:9b334a45a8ff 1603 #endif /* STM32F103xE || STM32F103xG */
bogdanm 0:9b334a45a8ff 1604 break;
bogdanm 0:9b334a45a8ff 1605 }
bogdanm 0:9b334a45a8ff 1606 case RCC_PERIPHCLK_I2S3:
bogdanm 0:9b334a45a8ff 1607 {
bogdanm 0:9b334a45a8ff 1608 #if defined (STM32F103xE) || defined (STM32F103xG)
bogdanm 0:9b334a45a8ff 1609 /* SYSCLK used as source clock for I2S3 */
bogdanm 0:9b334a45a8ff 1610 frequency = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 1611 #else
bogdanm 0:9b334a45a8ff 1612 if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
bogdanm 0:9b334a45a8ff 1613 {
bogdanm 0:9b334a45a8ff 1614 /* SYSCLK used as source clock for I2S3 */
bogdanm 0:9b334a45a8ff 1615 frequency = HAL_RCC_GetSysClockFreq();
bogdanm 0:9b334a45a8ff 1616 }
bogdanm 0:9b334a45a8ff 1617 else
bogdanm 0:9b334a45a8ff 1618 {
bogdanm 0:9b334a45a8ff 1619 /* Check if PLLI2S is enabled */
bogdanm 0:9b334a45a8ff 1620 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
bogdanm 0:9b334a45a8ff 1621 {
bogdanm 0:9b334a45a8ff 1622 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
bogdanm 0:9b334a45a8ff 1623 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
bogdanm 0:9b334a45a8ff 1624 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
bogdanm 0:9b334a45a8ff 1625 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
bogdanm 0:9b334a45a8ff 1626 }
bogdanm 0:9b334a45a8ff 1627 }
bogdanm 0:9b334a45a8ff 1628 #endif /* STM32F103xE || STM32F103xG */
bogdanm 0:9b334a45a8ff 1629 break;
bogdanm 0:9b334a45a8ff 1630 }
bogdanm 0:9b334a45a8ff 1631 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1632 case RCC_PERIPHCLK_RTC:
bogdanm 0:9b334a45a8ff 1633 {
bogdanm 0:9b334a45a8ff 1634 /* Get RCC BDCR configuration ------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1635 tmp_reg = RCC->BDCR;
bogdanm 0:9b334a45a8ff 1636
bogdanm 0:9b334a45a8ff 1637 /* Check if LSE is ready if RTC clock selection is LSE */
bogdanm 0:9b334a45a8ff 1638 if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(tmp_reg, RCC_BDCR_LSERDY)))
bogdanm 0:9b334a45a8ff 1639 {
bogdanm 0:9b334a45a8ff 1640 frequency = LSE_VALUE;
bogdanm 0:9b334a45a8ff 1641 }
bogdanm 0:9b334a45a8ff 1642 /* Check if LSI is ready if RTC clock selection is LSI */
bogdanm 0:9b334a45a8ff 1643 else if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
bogdanm 0:9b334a45a8ff 1644 {
bogdanm 0:9b334a45a8ff 1645 frequency = LSI_VALUE;
bogdanm 0:9b334a45a8ff 1646 }
bogdanm 0:9b334a45a8ff 1647 else if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
bogdanm 0:9b334a45a8ff 1648 {
bogdanm 0:9b334a45a8ff 1649 frequency = HSE_VALUE / 128;
bogdanm 0:9b334a45a8ff 1650 }
bogdanm 0:9b334a45a8ff 1651 /* Clock not enabled for RTC*/
bogdanm 0:9b334a45a8ff 1652 else
bogdanm 0:9b334a45a8ff 1653 {
bogdanm 0:9b334a45a8ff 1654 frequency = 0;
bogdanm 0:9b334a45a8ff 1655 }
bogdanm 0:9b334a45a8ff 1656 break;
bogdanm 0:9b334a45a8ff 1657 }
bogdanm 0:9b334a45a8ff 1658 case RCC_PERIPHCLK_ADC:
bogdanm 0:9b334a45a8ff 1659 {
bogdanm 0:9b334a45a8ff 1660 frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2);
bogdanm 0:9b334a45a8ff 1661 break;
bogdanm 0:9b334a45a8ff 1662 }
bogdanm 0:9b334a45a8ff 1663 default:
bogdanm 0:9b334a45a8ff 1664 {
bogdanm 0:9b334a45a8ff 1665 break;
bogdanm 0:9b334a45a8ff 1666 }
bogdanm 0:9b334a45a8ff 1667 }
bogdanm 0:9b334a45a8ff 1668 return(frequency);
bogdanm 0:9b334a45a8ff 1669 }
bogdanm 0:9b334a45a8ff 1670
bogdanm 0:9b334a45a8ff 1671 /**
bogdanm 0:9b334a45a8ff 1672 * @}
bogdanm 0:9b334a45a8ff 1673 */
bogdanm 0:9b334a45a8ff 1674
bogdanm 0:9b334a45a8ff 1675 #if defined(STM32F105xC) || defined(STM32F107xC)
bogdanm 0:9b334a45a8ff 1676 /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
bogdanm 0:9b334a45a8ff 1677 * @brief PLLI2S Management functions
bogdanm 0:9b334a45a8ff 1678 *
bogdanm 0:9b334a45a8ff 1679 @verbatim
bogdanm 0:9b334a45a8ff 1680 ===============================================================================
bogdanm 0:9b334a45a8ff 1681 ##### Extended PLLI2S Management functions #####
bogdanm 0:9b334a45a8ff 1682 ===============================================================================
bogdanm 0:9b334a45a8ff 1683 [..]
bogdanm 0:9b334a45a8ff 1684 This subsection provides a set of functions allowing to control the PLLI2S
bogdanm 0:9b334a45a8ff 1685 activation or deactivation
bogdanm 0:9b334a45a8ff 1686 @endverbatim
bogdanm 0:9b334a45a8ff 1687 * @{
bogdanm 0:9b334a45a8ff 1688 */
bogdanm 0:9b334a45a8ff 1689
bogdanm 0:9b334a45a8ff 1690 /**
bogdanm 0:9b334a45a8ff 1691 * @brief Enable PLLI2S
bogdanm 0:9b334a45a8ff 1692 * @param PLLI2SInit: pointer to an RCC_PLLI2SInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1693 * contains the configuration information for the PLLI2S
bogdanm 0:9b334a45a8ff 1694 * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
bogdanm 0:9b334a45a8ff 1695 * @retval HAL status
bogdanm 0:9b334a45a8ff 1696 */
bogdanm 0:9b334a45a8ff 1697 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
bogdanm 0:9b334a45a8ff 1698 {
bogdanm 0:9b334a45a8ff 1699 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1700
bogdanm 0:9b334a45a8ff 1701 /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
bogdanm 0:9b334a45a8ff 1702 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
bogdanm 0:9b334a45a8ff 1703 {
bogdanm 0:9b334a45a8ff 1704 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1705 assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
bogdanm 0:9b334a45a8ff 1706 assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
bogdanm 0:9b334a45a8ff 1707
bogdanm 0:9b334a45a8ff 1708 /* Prediv2 can be written only when the PLL2 is disabled. */
bogdanm 0:9b334a45a8ff 1709 /* Return an error only if new value is different from the programmed value */
bogdanm 0:9b334a45a8ff 1710 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
bogdanm 0:9b334a45a8ff 1711 (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
bogdanm 0:9b334a45a8ff 1712 {
bogdanm 0:9b334a45a8ff 1713 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1714 }
bogdanm 0:9b334a45a8ff 1715
bogdanm 0:9b334a45a8ff 1716 /* Disable the main PLLI2S. */
bogdanm 0:9b334a45a8ff 1717 __HAL_RCC_PLLI2S_DISABLE();
bogdanm 0:9b334a45a8ff 1718
bogdanm 0:9b334a45a8ff 1719 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 1720 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1721
bogdanm 0:9b334a45a8ff 1722 /* Wait till PLLI2S is ready */
bogdanm 0:9b334a45a8ff 1723 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
bogdanm 0:9b334a45a8ff 1724 {
bogdanm 0:9b334a45a8ff 1725 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1726 {
bogdanm 0:9b334a45a8ff 1727 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1728 }
bogdanm 0:9b334a45a8ff 1729 }
bogdanm 0:9b334a45a8ff 1730
bogdanm 0:9b334a45a8ff 1731 /* Configure the HSE prediv2 factor --------------------------------*/
bogdanm 0:9b334a45a8ff 1732 __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
bogdanm 0:9b334a45a8ff 1733
bogdanm 0:9b334a45a8ff 1734
bogdanm 0:9b334a45a8ff 1735 /* Configure the main PLLI2S multiplication factors. */
bogdanm 0:9b334a45a8ff 1736 __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
bogdanm 0:9b334a45a8ff 1737
bogdanm 0:9b334a45a8ff 1738 /* Enable the main PLLI2S. */
bogdanm 0:9b334a45a8ff 1739 __HAL_RCC_PLLI2S_ENABLE();
bogdanm 0:9b334a45a8ff 1740
bogdanm 0:9b334a45a8ff 1741 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 1742 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1743
bogdanm 0:9b334a45a8ff 1744 /* Wait till PLLI2S is ready */
bogdanm 0:9b334a45a8ff 1745 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
bogdanm 0:9b334a45a8ff 1746 {
bogdanm 0:9b334a45a8ff 1747 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1748 {
bogdanm 0:9b334a45a8ff 1749 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1750 }
bogdanm 0:9b334a45a8ff 1751 }
bogdanm 0:9b334a45a8ff 1752 }
bogdanm 0:9b334a45a8ff 1753 else
bogdanm 0:9b334a45a8ff 1754 {
bogdanm 0:9b334a45a8ff 1755 /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
bogdanm 0:9b334a45a8ff 1756 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1757 }
bogdanm 0:9b334a45a8ff 1758
bogdanm 0:9b334a45a8ff 1759 return HAL_OK;
bogdanm 0:9b334a45a8ff 1760 }
bogdanm 0:9b334a45a8ff 1761
bogdanm 0:9b334a45a8ff 1762 /**
bogdanm 0:9b334a45a8ff 1763 * @brief Disable PLLI2S
bogdanm 0:9b334a45a8ff 1764 * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
bogdanm 0:9b334a45a8ff 1765 * @retval HAL status
bogdanm 0:9b334a45a8ff 1766 */
bogdanm 0:9b334a45a8ff 1767 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
bogdanm 0:9b334a45a8ff 1768 {
bogdanm 0:9b334a45a8ff 1769 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1770
bogdanm 0:9b334a45a8ff 1771 /* Disable PLL I2S as not requested by I2S2 or I2S3*/
bogdanm 0:9b334a45a8ff 1772 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
bogdanm 0:9b334a45a8ff 1773 {
bogdanm 0:9b334a45a8ff 1774 /* Disable the main PLLI2S. */
bogdanm 0:9b334a45a8ff 1775 __HAL_RCC_PLLI2S_DISABLE();
bogdanm 0:9b334a45a8ff 1776
bogdanm 0:9b334a45a8ff 1777 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 1778 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1779
bogdanm 0:9b334a45a8ff 1780 /* Wait till PLLI2S is ready */
bogdanm 0:9b334a45a8ff 1781 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
bogdanm 0:9b334a45a8ff 1782 {
bogdanm 0:9b334a45a8ff 1783 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1784 {
bogdanm 0:9b334a45a8ff 1785 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1786 }
bogdanm 0:9b334a45a8ff 1787 }
bogdanm 0:9b334a45a8ff 1788 }
bogdanm 0:9b334a45a8ff 1789 else
bogdanm 0:9b334a45a8ff 1790 {
bogdanm 0:9b334a45a8ff 1791 /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
bogdanm 0:9b334a45a8ff 1792 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1793 }
bogdanm 0:9b334a45a8ff 1794
bogdanm 0:9b334a45a8ff 1795 return HAL_OK;
bogdanm 0:9b334a45a8ff 1796 }
bogdanm 0:9b334a45a8ff 1797
bogdanm 0:9b334a45a8ff 1798 /**
bogdanm 0:9b334a45a8ff 1799 * @}
bogdanm 0:9b334a45a8ff 1800 */
bogdanm 0:9b334a45a8ff 1801
bogdanm 0:9b334a45a8ff 1802 /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
bogdanm 0:9b334a45a8ff 1803 * @brief PLL2 Management functions
bogdanm 0:9b334a45a8ff 1804 *
bogdanm 0:9b334a45a8ff 1805 @verbatim
bogdanm 0:9b334a45a8ff 1806 ===============================================================================
bogdanm 0:9b334a45a8ff 1807 ##### Extended PLL2 Management functions #####
bogdanm 0:9b334a45a8ff 1808 ===============================================================================
bogdanm 0:9b334a45a8ff 1809 [..]
bogdanm 0:9b334a45a8ff 1810 This subsection provides a set of functions allowing to control the PLL2
bogdanm 0:9b334a45a8ff 1811 activation or deactivation
bogdanm 0:9b334a45a8ff 1812 @endverbatim
bogdanm 0:9b334a45a8ff 1813 * @{
bogdanm 0:9b334a45a8ff 1814 */
bogdanm 0:9b334a45a8ff 1815
bogdanm 0:9b334a45a8ff 1816 /**
bogdanm 0:9b334a45a8ff 1817 * @brief Enable PLL2
bogdanm 0:9b334a45a8ff 1818 * @param PLL2Init: pointer to an RCC_PLL2InitTypeDef structure that
bogdanm 0:9b334a45a8ff 1819 * contains the configuration information for the PLL2
bogdanm 0:9b334a45a8ff 1820 * @note The PLL2 configuration not modified if used indirectly as system clock.
bogdanm 0:9b334a45a8ff 1821 * @retval HAL status
bogdanm 0:9b334a45a8ff 1822 */
bogdanm 0:9b334a45a8ff 1823 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
bogdanm 0:9b334a45a8ff 1824 {
bogdanm 0:9b334a45a8ff 1825 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1826
bogdanm 0:9b334a45a8ff 1827 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
bogdanm 0:9b334a45a8ff 1828 clock (i.e. it is used as PLL clock entry that is used as system clock). */
bogdanm 0:9b334a45a8ff 1829 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
bogdanm 0:9b334a45a8ff 1830 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
bogdanm 0:9b334a45a8ff 1831 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
bogdanm 0:9b334a45a8ff 1832 {
bogdanm 0:9b334a45a8ff 1833 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1834 }
bogdanm 0:9b334a45a8ff 1835 else
bogdanm 0:9b334a45a8ff 1836 {
bogdanm 0:9b334a45a8ff 1837 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1838 assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
bogdanm 0:9b334a45a8ff 1839 assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
bogdanm 0:9b334a45a8ff 1840
bogdanm 0:9b334a45a8ff 1841 /* Prediv2 can be written only when the PLLI2S is disabled. */
bogdanm 0:9b334a45a8ff 1842 /* Return an error only if new value is different from the programmed value */
bogdanm 0:9b334a45a8ff 1843 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
bogdanm 0:9b334a45a8ff 1844 (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
bogdanm 0:9b334a45a8ff 1845 {
bogdanm 0:9b334a45a8ff 1846 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1847 }
bogdanm 0:9b334a45a8ff 1848
bogdanm 0:9b334a45a8ff 1849 /* Disable the main PLL2. */
bogdanm 0:9b334a45a8ff 1850 __HAL_RCC_PLL2_DISABLE();
bogdanm 0:9b334a45a8ff 1851
bogdanm 0:9b334a45a8ff 1852 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 1853 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1854
bogdanm 0:9b334a45a8ff 1855 /* Wait till PLL2 is disabled */
bogdanm 0:9b334a45a8ff 1856 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
bogdanm 0:9b334a45a8ff 1857 {
bogdanm 0:9b334a45a8ff 1858 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1859 {
bogdanm 0:9b334a45a8ff 1860 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1861 }
bogdanm 0:9b334a45a8ff 1862 }
bogdanm 0:9b334a45a8ff 1863
bogdanm 0:9b334a45a8ff 1864 /* Configure the HSE prediv2 factor --------------------------------*/
bogdanm 0:9b334a45a8ff 1865 __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
bogdanm 0:9b334a45a8ff 1866
bogdanm 0:9b334a45a8ff 1867 /* Configure the main PLL2 multiplication factors. */
bogdanm 0:9b334a45a8ff 1868 __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
bogdanm 0:9b334a45a8ff 1869
bogdanm 0:9b334a45a8ff 1870 /* Enable the main PLL2. */
bogdanm 0:9b334a45a8ff 1871 __HAL_RCC_PLL2_ENABLE();
bogdanm 0:9b334a45a8ff 1872
bogdanm 0:9b334a45a8ff 1873 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 1874 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1875
bogdanm 0:9b334a45a8ff 1876 /* Wait till PLL2 is ready */
bogdanm 0:9b334a45a8ff 1877 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
bogdanm 0:9b334a45a8ff 1878 {
bogdanm 0:9b334a45a8ff 1879 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1880 {
bogdanm 0:9b334a45a8ff 1881 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1882 }
bogdanm 0:9b334a45a8ff 1883 }
bogdanm 0:9b334a45a8ff 1884 }
bogdanm 0:9b334a45a8ff 1885
bogdanm 0:9b334a45a8ff 1886 return HAL_OK;
bogdanm 0:9b334a45a8ff 1887 }
bogdanm 0:9b334a45a8ff 1888
bogdanm 0:9b334a45a8ff 1889 /**
bogdanm 0:9b334a45a8ff 1890 * @brief Disable PLL2
bogdanm 0:9b334a45a8ff 1891 * @note PLL2 is not disabled if used indirectly as system clock.
bogdanm 0:9b334a45a8ff 1892 * @retval HAL status
bogdanm 0:9b334a45a8ff 1893 */
bogdanm 0:9b334a45a8ff 1894 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
bogdanm 0:9b334a45a8ff 1895 {
bogdanm 0:9b334a45a8ff 1896 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 1897
bogdanm 0:9b334a45a8ff 1898 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
bogdanm 0:9b334a45a8ff 1899 clock (i.e. it is used as PLL clock entry that is used as system clock). */
bogdanm 0:9b334a45a8ff 1900 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
bogdanm 0:9b334a45a8ff 1901 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
bogdanm 0:9b334a45a8ff 1902 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
bogdanm 0:9b334a45a8ff 1903 {
bogdanm 0:9b334a45a8ff 1904 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1905 }
bogdanm 0:9b334a45a8ff 1906 else
bogdanm 0:9b334a45a8ff 1907 {
bogdanm 0:9b334a45a8ff 1908 /* Disable the main PLL2. */
bogdanm 0:9b334a45a8ff 1909 __HAL_RCC_PLL2_DISABLE();
bogdanm 0:9b334a45a8ff 1910
bogdanm 0:9b334a45a8ff 1911 /* Get Start Tick*/
bogdanm 0:9b334a45a8ff 1912 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1913
bogdanm 0:9b334a45a8ff 1914 /* Wait till PLL2 is disabled */
bogdanm 0:9b334a45a8ff 1915 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
bogdanm 0:9b334a45a8ff 1916 {
bogdanm 0:9b334a45a8ff 1917 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1918 {
bogdanm 0:9b334a45a8ff 1919 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1920 }
bogdanm 0:9b334a45a8ff 1921 }
bogdanm 0:9b334a45a8ff 1922 }
bogdanm 0:9b334a45a8ff 1923
bogdanm 0:9b334a45a8ff 1924 return HAL_OK;
bogdanm 0:9b334a45a8ff 1925 }
bogdanm 0:9b334a45a8ff 1926
bogdanm 0:9b334a45a8ff 1927 /**
bogdanm 0:9b334a45a8ff 1928 * @}
bogdanm 0:9b334a45a8ff 1929 */
bogdanm 0:9b334a45a8ff 1930 #endif /* STM32F105xC || STM32F107xC */
bogdanm 0:9b334a45a8ff 1931
bogdanm 0:9b334a45a8ff 1932 /**
bogdanm 0:9b334a45a8ff 1933 * @}
bogdanm 0:9b334a45a8ff 1934 */
bogdanm 0:9b334a45a8ff 1935
bogdanm 0:9b334a45a8ff 1936 /**
bogdanm 0:9b334a45a8ff 1937 * @}
bogdanm 0:9b334a45a8ff 1938 */
bogdanm 0:9b334a45a8ff 1939
bogdanm 0:9b334a45a8ff 1940 #endif /* HAL_RCC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1941 /**
bogdanm 0:9b334a45a8ff 1942 * @}
bogdanm 0:9b334a45a8ff 1943 */
bogdanm 0:9b334a45a8ff 1944
bogdanm 0:9b334a45a8ff 1945 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
bogdanm 0:9b334a45a8ff 1946