Kevin Kadooka / mbed-dev

Fork of mbed-dev build 137, last build before FAT file system appears to be broken. Also reduced HSE timeout time in STM4XX HAL

Fork of mbed-dev by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC11UXX/LPC11Uxx.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1
bogdanm 0:9b334a45a8ff 2 /****************************************************************************************************//**
bogdanm 0:9b334a45a8ff 3 * @file LPC11Uxx.h
bogdanm 0:9b334a45a8ff 4 *
bogdanm 0:9b334a45a8ff 5 *
bogdanm 0:9b334a45a8ff 6 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
bogdanm 0:9b334a45a8ff 7 * default LPC11Uxx Device Series
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 * @version V0.1
bogdanm 0:9b334a45a8ff 10 * @date 21. March 2011
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
bogdanm 0:9b334a45a8ff 13 *
bogdanm 0:9b334a45a8ff 14 * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
bogdanm 0:9b334a45a8ff 15 * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 *******************************************************************************************************/
bogdanm 0:9b334a45a8ff 18
bogdanm 0:9b334a45a8ff 19 // ################################################################################
bogdanm 0:9b334a45a8ff 20 // Minor fix 8 April 2011 - changed LPC_CT32B1_BASE from 0x40014000 to 0x40018000
bogdanm 0:9b334a45a8ff 21 // ################################################################################
bogdanm 0:9b334a45a8ff 22
bogdanm 0:9b334a45a8ff 23 /** @addtogroup NXP
bogdanm 0:9b334a45a8ff 24 * @{
bogdanm 0:9b334a45a8ff 25 */
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 /** @addtogroup LPC11Uxx
bogdanm 0:9b334a45a8ff 28 * @{
bogdanm 0:9b334a45a8ff 29 */
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 #ifndef __LPC11UXX_H__
bogdanm 0:9b334a45a8ff 32 #define __LPC11UXX_H__
bogdanm 0:9b334a45a8ff 33
bogdanm 0:9b334a45a8ff 34 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 35 extern "C" {
bogdanm 0:9b334a45a8ff 36 #endif
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38
bogdanm 0:9b334a45a8ff 39 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 40 #pragma anon_unions
bogdanm 0:9b334a45a8ff 41 #endif
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43 /* Interrupt Number Definition */
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 typedef enum {
bogdanm 0:9b334a45a8ff 46 // ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
bogdanm 0:9b334a45a8ff 47 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
bogdanm 0:9b334a45a8ff 48 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
bogdanm 0:9b334a45a8ff 49 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
bogdanm 0:9b334a45a8ff 50 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
bogdanm 0:9b334a45a8ff 51 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
bogdanm 0:9b334a45a8ff 52 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
bogdanm 0:9b334a45a8ff 53 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
bogdanm 0:9b334a45a8ff 54 // --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
bogdanm 0:9b334a45a8ff 55 FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
bogdanm 0:9b334a45a8ff 56 FLEX_INT1_IRQn = 1,
bogdanm 0:9b334a45a8ff 57 FLEX_INT2_IRQn = 2,
bogdanm 0:9b334a45a8ff 58 FLEX_INT3_IRQn = 3,
bogdanm 0:9b334a45a8ff 59 FLEX_INT4_IRQn = 4,
bogdanm 0:9b334a45a8ff 60 FLEX_INT5_IRQn = 5,
bogdanm 0:9b334a45a8ff 61 FLEX_INT6_IRQn = 6,
bogdanm 0:9b334a45a8ff 62 FLEX_INT7_IRQn = 7,
bogdanm 0:9b334a45a8ff 63 GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
bogdanm 0:9b334a45a8ff 64 GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
bogdanm 0:9b334a45a8ff 65 Reserved0_IRQn = 10, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 66 Reserved1_IRQn = 11,
bogdanm 0:9b334a45a8ff 67 Reserved2_IRQn = 12,
bogdanm 0:9b334a45a8ff 68 Reserved3_IRQn = 13,
bogdanm 0:9b334a45a8ff 69 SSP1_IRQn = 14, /*!< SSP1 Interrupt */
bogdanm 0:9b334a45a8ff 70 I2C_IRQn = 15, /*!< I2C Interrupt */
bogdanm 0:9b334a45a8ff 71 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
bogdanm 0:9b334a45a8ff 72 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
bogdanm 0:9b334a45a8ff 73 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
bogdanm 0:9b334a45a8ff 74 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
bogdanm 0:9b334a45a8ff 75 SSP0_IRQn = 20, /*!< SSP0 Interrupt */
bogdanm 0:9b334a45a8ff 76 UART_IRQn = 21, /*!< UART Interrupt */
bogdanm 0:9b334a45a8ff 77 USB_IRQn = 22, /*!< USB IRQ Interrupt */
bogdanm 0:9b334a45a8ff 78 USB_FIQn = 23, /*!< USB FIQ Interrupt */
bogdanm 0:9b334a45a8ff 79 ADC_IRQn = 24, /*!< A/D Converter Interrupt */
bogdanm 0:9b334a45a8ff 80 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
bogdanm 0:9b334a45a8ff 81 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
bogdanm 0:9b334a45a8ff 82 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
bogdanm 0:9b334a45a8ff 83 Reserved4_IRQn = 28, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 84 Reserved5_IRQn = 29, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 85 USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
bogdanm 0:9b334a45a8ff 86 Reserved6_IRQn = 31, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 87 } IRQn_Type;
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /** @addtogroup Configuration_of_CMSIS
bogdanm 0:9b334a45a8ff 91 * @{
bogdanm 0:9b334a45a8ff 92 */
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 0:9b334a45a8ff 97 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 98 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 99 /** @} */ /* End of group Configuration_of_CMSIS */
bogdanm 0:9b334a45a8ff 100
bogdanm 0:9b334a45a8ff 101 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
bogdanm 0:9b334a45a8ff 102 #include "system_LPC11Uxx.h" /*!< LPC11Uxx System */
bogdanm 0:9b334a45a8ff 103
bogdanm 0:9b334a45a8ff 104 /** @addtogroup Device_Peripheral_Registers
bogdanm 0:9b334a45a8ff 105 * @{
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 110 // ----- I2C -----
bogdanm 0:9b334a45a8ff 111 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 112
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /**
bogdanm 0:9b334a45a8ff 115 * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
bogdanm 0:9b334a45a8ff 116 */
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 typedef struct { /*!< (@ 0x40000000) I2C Structure */
bogdanm 0:9b334a45a8ff 119 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
bogdanm 0:9b334a45a8ff 120 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
bogdanm 0:9b334a45a8ff 121 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
bogdanm 0:9b334a45a8ff 122 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
bogdanm 0:9b334a45a8ff 123 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
bogdanm 0:9b334a45a8ff 124 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
bogdanm 0:9b334a45a8ff 125 __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
bogdanm 0:9b334a45a8ff 126 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
bogdanm 0:9b334a45a8ff 127 __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
bogdanm 0:9b334a45a8ff 128 __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
bogdanm 0:9b334a45a8ff 129 __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
bogdanm 0:9b334a45a8ff 130 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
bogdanm 0:9b334a45a8ff 131 union{
bogdanm 0:9b334a45a8ff 132 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
bogdanm 0:9b334a45a8ff 133 struct{
bogdanm 0:9b334a45a8ff 134 __IO uint32_t MASK0;
bogdanm 0:9b334a45a8ff 135 __IO uint32_t MASK1;
bogdanm 0:9b334a45a8ff 136 __IO uint32_t MASK2;
bogdanm 0:9b334a45a8ff 137 __IO uint32_t MASK3;
bogdanm 0:9b334a45a8ff 138 };
bogdanm 0:9b334a45a8ff 139 };
bogdanm 0:9b334a45a8ff 140 } LPC_I2C_Type;
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 144 // ----- WWDT -----
bogdanm 0:9b334a45a8ff 145 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 146
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 /**
bogdanm 0:9b334a45a8ff 149 * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 typedef struct { /*!< (@ 0x40004000) WWDT Structure */
bogdanm 0:9b334a45a8ff 153 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
bogdanm 0:9b334a45a8ff 154 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
bogdanm 0:9b334a45a8ff 155 __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
bogdanm 0:9b334a45a8ff 156 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
bogdanm 0:9b334a45a8ff 157 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
bogdanm 0:9b334a45a8ff 158 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
bogdanm 0:9b334a45a8ff 159 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
bogdanm 0:9b334a45a8ff 160 } LPC_WWDT_Type;
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162
bogdanm 0:9b334a45a8ff 163 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 164 // ----- USART -----
bogdanm 0:9b334a45a8ff 165 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 166
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /**
bogdanm 0:9b334a45a8ff 169 * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 typedef struct { /*!< (@ 0x40008000) USART Structure */
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 union {
bogdanm 0:9b334a45a8ff 175 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
bogdanm 0:9b334a45a8ff 176 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
bogdanm 0:9b334a45a8ff 177 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
bogdanm 0:9b334a45a8ff 178 };
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 union {
bogdanm 0:9b334a45a8ff 181 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
bogdanm 0:9b334a45a8ff 182 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
bogdanm 0:9b334a45a8ff 183 };
bogdanm 0:9b334a45a8ff 184
bogdanm 0:9b334a45a8ff 185 union {
bogdanm 0:9b334a45a8ff 186 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
bogdanm 0:9b334a45a8ff 187 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
bogdanm 0:9b334a45a8ff 188 };
bogdanm 0:9b334a45a8ff 189 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
bogdanm 0:9b334a45a8ff 190 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
bogdanm 0:9b334a45a8ff 191 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
bogdanm 0:9b334a45a8ff 192 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
bogdanm 0:9b334a45a8ff 193 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
bogdanm 0:9b334a45a8ff 194 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
bogdanm 0:9b334a45a8ff 195 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
bogdanm 0:9b334a45a8ff 196 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
bogdanm 0:9b334a45a8ff 197 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
bogdanm 0:9b334a45a8ff 198 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
bogdanm 0:9b334a45a8ff 199 __I uint32_t RESERVED0[3];
bogdanm 0:9b334a45a8ff 200 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
bogdanm 0:9b334a45a8ff 201 __I uint32_t RESERVED1;
bogdanm 0:9b334a45a8ff 202 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
bogdanm 0:9b334a45a8ff 203 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
bogdanm 0:9b334a45a8ff 204 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
bogdanm 0:9b334a45a8ff 205 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
bogdanm 0:9b334a45a8ff 206 __IO uint32_t SYNCCTRL;
bogdanm 0:9b334a45a8ff 207 } LPC_USART_Type;
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 211 // ----- Timer -----
bogdanm 0:9b334a45a8ff 212 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214
bogdanm 0:9b334a45a8ff 215 /**
bogdanm 0:9b334a45a8ff 216 * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
bogdanm 0:9b334a45a8ff 217 */
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
bogdanm 0:9b334a45a8ff 220 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
bogdanm 0:9b334a45a8ff 221 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
bogdanm 0:9b334a45a8ff 222 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
bogdanm 0:9b334a45a8ff 223 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
bogdanm 0:9b334a45a8ff 224 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
bogdanm 0:9b334a45a8ff 225 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
bogdanm 0:9b334a45a8ff 226 union {
bogdanm 0:9b334a45a8ff 227 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
bogdanm 0:9b334a45a8ff 228 struct{
bogdanm 0:9b334a45a8ff 229 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
bogdanm 0:9b334a45a8ff 230 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
bogdanm 0:9b334a45a8ff 231 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
bogdanm 0:9b334a45a8ff 232 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
bogdanm 0:9b334a45a8ff 233 };
bogdanm 0:9b334a45a8ff 234 };
bogdanm 0:9b334a45a8ff 235 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
bogdanm 0:9b334a45a8ff 236 union{
bogdanm 0:9b334a45a8ff 237 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
bogdanm 0:9b334a45a8ff 238 struct{
bogdanm 0:9b334a45a8ff 239 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
bogdanm 0:9b334a45a8ff 240 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
bogdanm 0:9b334a45a8ff 241 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
bogdanm 0:9b334a45a8ff 242 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
bogdanm 0:9b334a45a8ff 243 };
bogdanm 0:9b334a45a8ff 244 };
bogdanm 0:9b334a45a8ff 245 __IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
bogdanm 0:9b334a45a8ff 246 __I uint32_t RESERVED0[12];
bogdanm 0:9b334a45a8ff 247 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
bogdanm 0:9b334a45a8ff 248 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
bogdanm 0:9b334a45a8ff 249 } LPC_CTxxBx_Type;
bogdanm 0:9b334a45a8ff 250
bogdanm 0:9b334a45a8ff 251
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 254 // ----- ADC -----
bogdanm 0:9b334a45a8ff 255 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 /**
bogdanm 0:9b334a45a8ff 259 * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
bogdanm 0:9b334a45a8ff 263 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
bogdanm 0:9b334a45a8ff 264 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
bogdanm 0:9b334a45a8ff 265 __I uint32_t RESERVED0[1];
bogdanm 0:9b334a45a8ff 266 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
bogdanm 0:9b334a45a8ff 267 union{
bogdanm 0:9b334a45a8ff 268 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
bogdanm 0:9b334a45a8ff 269 struct{
bogdanm 0:9b334a45a8ff 270 __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
bogdanm 0:9b334a45a8ff 271 __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
bogdanm 0:9b334a45a8ff 272 __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
bogdanm 0:9b334a45a8ff 273 __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
bogdanm 0:9b334a45a8ff 274 __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
bogdanm 0:9b334a45a8ff 275 __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
bogdanm 0:9b334a45a8ff 276 __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
bogdanm 0:9b334a45a8ff 277 __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
bogdanm 0:9b334a45a8ff 278 };
bogdanm 0:9b334a45a8ff 279 };
bogdanm 0:9b334a45a8ff 280 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
bogdanm 0:9b334a45a8ff 281 } LPC_ADC_Type;
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 285 // ----- PMU -----
bogdanm 0:9b334a45a8ff 286 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288
bogdanm 0:9b334a45a8ff 289 /**
bogdanm 0:9b334a45a8ff 290 * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
bogdanm 0:9b334a45a8ff 291 */
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 typedef struct { /*!< (@ 0x40038000) PMU Structure */
bogdanm 0:9b334a45a8ff 294 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
bogdanm 0:9b334a45a8ff 295 union{
bogdanm 0:9b334a45a8ff 296 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
bogdanm 0:9b334a45a8ff 297 struct{
bogdanm 0:9b334a45a8ff 298 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
bogdanm 0:9b334a45a8ff 299 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
bogdanm 0:9b334a45a8ff 300 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
bogdanm 0:9b334a45a8ff 301 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
bogdanm 0:9b334a45a8ff 302 };
bogdanm 0:9b334a45a8ff 303 };
bogdanm 0:9b334a45a8ff 304 } LPC_PMU_Type;
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306
bogdanm 0:9b334a45a8ff 307 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 308 // ----- FLASHCTRL -----
bogdanm 0:9b334a45a8ff 309 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 310
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /**
bogdanm 0:9b334a45a8ff 313 * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
bogdanm 0:9b334a45a8ff 314 */
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
bogdanm 0:9b334a45a8ff 317 __I uint32_t RESERVED0[4];
bogdanm 0:9b334a45a8ff 318 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
bogdanm 0:9b334a45a8ff 319 __I uint32_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 320 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
bogdanm 0:9b334a45a8ff 321 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
bogdanm 0:9b334a45a8ff 322 __I uint32_t RESERVED2[1];
bogdanm 0:9b334a45a8ff 323 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
bogdanm 0:9b334a45a8ff 324 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
bogdanm 0:9b334a45a8ff 325 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
bogdanm 0:9b334a45a8ff 326 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
bogdanm 0:9b334a45a8ff 327 __I uint32_t RESERVED3[1001];
bogdanm 0:9b334a45a8ff 328 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
bogdanm 0:9b334a45a8ff 329 __I uint32_t RESERVED4[1];
bogdanm 0:9b334a45a8ff 330 __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
bogdanm 0:9b334a45a8ff 331 } LPC_FLASHCTRL_Type;
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 335 // ----- SSP0/1 -----
bogdanm 0:9b334a45a8ff 336 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 /**
bogdanm 0:9b334a45a8ff 340 * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
bogdanm 0:9b334a45a8ff 341 */
bogdanm 0:9b334a45a8ff 342
bogdanm 0:9b334a45a8ff 343 typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
bogdanm 0:9b334a45a8ff 344 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
bogdanm 0:9b334a45a8ff 345 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
bogdanm 0:9b334a45a8ff 346 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
bogdanm 0:9b334a45a8ff 347 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
bogdanm 0:9b334a45a8ff 348 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
bogdanm 0:9b334a45a8ff 349 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
bogdanm 0:9b334a45a8ff 350 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
bogdanm 0:9b334a45a8ff 351 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
bogdanm 0:9b334a45a8ff 352 __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
bogdanm 0:9b334a45a8ff 353 } LPC_SSPx_Type;
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 358 // ----- IOCONFIG -----
bogdanm 0:9b334a45a8ff 359 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361
bogdanm 0:9b334a45a8ff 362 /**
bogdanm 0:9b334a45a8ff 363 * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
bogdanm 0:9b334a45a8ff 364 */
bogdanm 0:9b334a45a8ff 365
bogdanm 0:9b334a45a8ff 366 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
bogdanm 0:9b334a45a8ff 367 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
bogdanm 0:9b334a45a8ff 368 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
bogdanm 0:9b334a45a8ff 369 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
bogdanm 0:9b334a45a8ff 370 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
bogdanm 0:9b334a45a8ff 371 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
bogdanm 0:9b334a45a8ff 372 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
bogdanm 0:9b334a45a8ff 373 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
bogdanm 0:9b334a45a8ff 374 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
bogdanm 0:9b334a45a8ff 375 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
bogdanm 0:9b334a45a8ff 376 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
bogdanm 0:9b334a45a8ff 377 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
bogdanm 0:9b334a45a8ff 378 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
bogdanm 0:9b334a45a8ff 379 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
bogdanm 0:9b334a45a8ff 380 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
bogdanm 0:9b334a45a8ff 381 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
bogdanm 0:9b334a45a8ff 382 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
bogdanm 0:9b334a45a8ff 383 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
bogdanm 0:9b334a45a8ff 384 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
bogdanm 0:9b334a45a8ff 385 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
bogdanm 0:9b334a45a8ff 386 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
bogdanm 0:9b334a45a8ff 387 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
bogdanm 0:9b334a45a8ff 388 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
bogdanm 0:9b334a45a8ff 389 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
bogdanm 0:9b334a45a8ff 390 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
bogdanm 0:9b334a45a8ff 391 __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
bogdanm 0:9b334a45a8ff 392 __IO uint32_t PIO1_1;
bogdanm 0:9b334a45a8ff 393 __IO uint32_t PIO1_2;
bogdanm 0:9b334a45a8ff 394 __IO uint32_t PIO1_3;
bogdanm 0:9b334a45a8ff 395 __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
bogdanm 0:9b334a45a8ff 396 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
bogdanm 0:9b334a45a8ff 397 __IO uint32_t PIO1_6;
bogdanm 0:9b334a45a8ff 398 __IO uint32_t PIO1_7;
bogdanm 0:9b334a45a8ff 399 __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
bogdanm 0:9b334a45a8ff 400 __IO uint32_t PIO1_9;
bogdanm 0:9b334a45a8ff 401 __IO uint32_t PIO1_10;
bogdanm 0:9b334a45a8ff 402 __IO uint32_t PIO1_11;
bogdanm 0:9b334a45a8ff 403 __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
bogdanm 0:9b334a45a8ff 404 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
bogdanm 0:9b334a45a8ff 405 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
bogdanm 0:9b334a45a8ff 406 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
bogdanm 0:9b334a45a8ff 407 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
bogdanm 0:9b334a45a8ff 408 __IO uint32_t PIO1_17;
bogdanm 0:9b334a45a8ff 409 __IO uint32_t PIO1_18;
bogdanm 0:9b334a45a8ff 410 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
bogdanm 0:9b334a45a8ff 411 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
bogdanm 0:9b334a45a8ff 412 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
bogdanm 0:9b334a45a8ff 413 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
bogdanm 0:9b334a45a8ff 414 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
bogdanm 0:9b334a45a8ff 415 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
bogdanm 0:9b334a45a8ff 416 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
bogdanm 0:9b334a45a8ff 417 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
bogdanm 0:9b334a45a8ff 418 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
bogdanm 0:9b334a45a8ff 419 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
bogdanm 0:9b334a45a8ff 420 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
bogdanm 0:9b334a45a8ff 421 __IO uint32_t PIO1_30;
bogdanm 0:9b334a45a8ff 422 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
bogdanm 0:9b334a45a8ff 423 } LPC_IOCON_Type;
bogdanm 0:9b334a45a8ff 424
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 427 // ----- SYSCON -----
bogdanm 0:9b334a45a8ff 428 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 /**
bogdanm 0:9b334a45a8ff 432 * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
bogdanm 0:9b334a45a8ff 433 */
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
bogdanm 0:9b334a45a8ff 436 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
bogdanm 0:9b334a45a8ff 437 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
bogdanm 0:9b334a45a8ff 438 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
bogdanm 0:9b334a45a8ff 439 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
bogdanm 0:9b334a45a8ff 440 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
bogdanm 0:9b334a45a8ff 441 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
bogdanm 0:9b334a45a8ff 442 __I uint32_t RESERVED0[2];
bogdanm 0:9b334a45a8ff 443 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
bogdanm 0:9b334a45a8ff 444 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
bogdanm 0:9b334a45a8ff 445 __I uint32_t RESERVED1[2];
bogdanm 0:9b334a45a8ff 446 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
bogdanm 0:9b334a45a8ff 447 __I uint32_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 448 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
bogdanm 0:9b334a45a8ff 449 __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
bogdanm 0:9b334a45a8ff 450 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
bogdanm 0:9b334a45a8ff 451 __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
bogdanm 0:9b334a45a8ff 452 __I uint32_t RESERVED3[8];
bogdanm 0:9b334a45a8ff 453 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
bogdanm 0:9b334a45a8ff 454 __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
bogdanm 0:9b334a45a8ff 455 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
bogdanm 0:9b334a45a8ff 456 __I uint32_t RESERVED4[1];
bogdanm 0:9b334a45a8ff 457 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
bogdanm 0:9b334a45a8ff 458 __I uint32_t RESERVED5[4];
bogdanm 0:9b334a45a8ff 459 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
bogdanm 0:9b334a45a8ff 460 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
bogdanm 0:9b334a45a8ff 461 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
bogdanm 0:9b334a45a8ff 462 __I uint32_t RESERVED6[8];
bogdanm 0:9b334a45a8ff 463 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
bogdanm 0:9b334a45a8ff 464 __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
bogdanm 0:9b334a45a8ff 465 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
bogdanm 0:9b334a45a8ff 466 __I uint32_t RESERVED7[5];
bogdanm 0:9b334a45a8ff 467 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
bogdanm 0:9b334a45a8ff 468 __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
bogdanm 0:9b334a45a8ff 469 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
bogdanm 0:9b334a45a8ff 470 __I uint32_t RESERVED8[5];
bogdanm 0:9b334a45a8ff 471 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
bogdanm 0:9b334a45a8ff 472 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
bogdanm 0:9b334a45a8ff 473 __I uint32_t RESERVED9[18];
bogdanm 0:9b334a45a8ff 474 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
bogdanm 0:9b334a45a8ff 475 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
bogdanm 0:9b334a45a8ff 476 __I uint32_t RESERVED10[6];
bogdanm 0:9b334a45a8ff 477 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
bogdanm 0:9b334a45a8ff 478 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
bogdanm 0:9b334a45a8ff 479 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
bogdanm 0:9b334a45a8ff 480 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
bogdanm 0:9b334a45a8ff 481 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
bogdanm 0:9b334a45a8ff 482 __I uint32_t RESERVED11[25];
bogdanm 0:9b334a45a8ff 483 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
bogdanm 0:9b334a45a8ff 484 __I uint32_t RESERVED12[3];
bogdanm 0:9b334a45a8ff 485 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
bogdanm 0:9b334a45a8ff 486 __I uint32_t RESERVED13[6];
bogdanm 0:9b334a45a8ff 487 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
bogdanm 0:9b334a45a8ff 488 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
bogdanm 0:9b334a45a8ff 489 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
bogdanm 0:9b334a45a8ff 490 __I uint32_t RESERVED14[110];
bogdanm 0:9b334a45a8ff 491 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
bogdanm 0:9b334a45a8ff 492 } LPC_SYSCON_Type;
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 496 // ----- GPIO_PIN_INT -----
bogdanm 0:9b334a45a8ff 497 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499
bogdanm 0:9b334a45a8ff 500 /**
bogdanm 0:9b334a45a8ff 501 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
bogdanm 0:9b334a45a8ff 502 */
bogdanm 0:9b334a45a8ff 503
bogdanm 0:9b334a45a8ff 504 typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
bogdanm 0:9b334a45a8ff 505 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
bogdanm 0:9b334a45a8ff 506 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 507 __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 508 __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 509 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 0:9b334a45a8ff 510 __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 0:9b334a45a8ff 511 __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
bogdanm 0:9b334a45a8ff 512 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
bogdanm 0:9b334a45a8ff 513 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
bogdanm 0:9b334a45a8ff 514 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
bogdanm 0:9b334a45a8ff 515 } LPC_GPIO_PIN_INT_Type;
bogdanm 0:9b334a45a8ff 516
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 519 // ----- GPIO_GROUP_INT0/1 -----
bogdanm 0:9b334a45a8ff 520 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522
bogdanm 0:9b334a45a8ff 523 /**
bogdanm 0:9b334a45a8ff 524 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
bogdanm 0:9b334a45a8ff 525 */
bogdanm 0:9b334a45a8ff 526
bogdanm 0:9b334a45a8ff 527 typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
bogdanm 0:9b334a45a8ff 528 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
bogdanm 0:9b334a45a8ff 529 __I uint32_t RESERVED0[7];
bogdanm 0:9b334a45a8ff 530 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
bogdanm 0:9b334a45a8ff 531 __I uint32_t RESERVED1[6];
bogdanm 0:9b334a45a8ff 532 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
bogdanm 0:9b334a45a8ff 533 } LPC_GPIO_GROUP_INTx_Type;
bogdanm 0:9b334a45a8ff 534
bogdanm 0:9b334a45a8ff 535
bogdanm 0:9b334a45a8ff 536
bogdanm 0:9b334a45a8ff 537 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 538 // ----- USB -----
bogdanm 0:9b334a45a8ff 539 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 540
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /**
bogdanm 0:9b334a45a8ff 543 * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
bogdanm 0:9b334a45a8ff 544 */
bogdanm 0:9b334a45a8ff 545
bogdanm 0:9b334a45a8ff 546 typedef struct { /*!< (@ 0x40080000) USB Structure */
bogdanm 0:9b334a45a8ff 547 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
bogdanm 0:9b334a45a8ff 548 __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
bogdanm 0:9b334a45a8ff 549 __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
bogdanm 0:9b334a45a8ff 550 __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
bogdanm 0:9b334a45a8ff 551 __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
bogdanm 0:9b334a45a8ff 552 __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
bogdanm 0:9b334a45a8ff 553 __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
bogdanm 0:9b334a45a8ff 554 __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
bogdanm 0:9b334a45a8ff 555 __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
bogdanm 0:9b334a45a8ff 556 __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
bogdanm 0:9b334a45a8ff 557 __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
bogdanm 0:9b334a45a8ff 558 __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
bogdanm 0:9b334a45a8ff 559 __I uint32_t RESERVED0[1];
bogdanm 0:9b334a45a8ff 560 __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
bogdanm 0:9b334a45a8ff 561 } LPC_USB_Type;
bogdanm 0:9b334a45a8ff 562
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 565 // ----- GPIO_PORT -----
bogdanm 0:9b334a45a8ff 566 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 567
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 /**
bogdanm 0:9b334a45a8ff 570 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
bogdanm 0:9b334a45a8ff 571 */
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 typedef struct {
bogdanm 0:9b334a45a8ff 574 union {
bogdanm 0:9b334a45a8ff 575 struct {
bogdanm 0:9b334a45a8ff 576 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
bogdanm 0:9b334a45a8ff 577 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
bogdanm 0:9b334a45a8ff 578 };
bogdanm 0:9b334a45a8ff 579 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
bogdanm 0:9b334a45a8ff 580 };
bogdanm 0:9b334a45a8ff 581 __I uint32_t RESERVED0[1008];
bogdanm 0:9b334a45a8ff 582 union {
bogdanm 0:9b334a45a8ff 583 struct {
bogdanm 0:9b334a45a8ff 584 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
bogdanm 0:9b334a45a8ff 585 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
bogdanm 0:9b334a45a8ff 586 };
bogdanm 0:9b334a45a8ff 587 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
bogdanm 0:9b334a45a8ff 588 };
bogdanm 0:9b334a45a8ff 589 uint32_t RESERVED1[960];
bogdanm 0:9b334a45a8ff 590 __IO uint32_t DIR[2]; /* 0x2000 */
bogdanm 0:9b334a45a8ff 591 uint32_t RESERVED2[30];
bogdanm 0:9b334a45a8ff 592 __IO uint32_t MASK[2]; /* 0x2080 */
bogdanm 0:9b334a45a8ff 593 uint32_t RESERVED3[30];
bogdanm 0:9b334a45a8ff 594 __IO uint32_t PIN[2]; /* 0x2100 */
bogdanm 0:9b334a45a8ff 595 uint32_t RESERVED4[30];
bogdanm 0:9b334a45a8ff 596 __IO uint32_t MPIN[2]; /* 0x2180 */
bogdanm 0:9b334a45a8ff 597 uint32_t RESERVED5[30];
bogdanm 0:9b334a45a8ff 598 __IO uint32_t SET[2]; /* 0x2200 */
bogdanm 0:9b334a45a8ff 599 uint32_t RESERVED6[30];
bogdanm 0:9b334a45a8ff 600 __O uint32_t CLR[2]; /* 0x2280 */
bogdanm 0:9b334a45a8ff 601 uint32_t RESERVED7[30];
bogdanm 0:9b334a45a8ff 602 __O uint32_t NOT[2]; /* 0x2300 */
bogdanm 0:9b334a45a8ff 603 } LPC_GPIO_Type;
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605
bogdanm 0:9b334a45a8ff 606 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 607 #pragma no_anon_unions
bogdanm 0:9b334a45a8ff 608 #endif
bogdanm 0:9b334a45a8ff 609
bogdanm 0:9b334a45a8ff 610
bogdanm 0:9b334a45a8ff 611 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 612 // ----- Peripheral memory map -----
bogdanm 0:9b334a45a8ff 613 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 614
bogdanm 0:9b334a45a8ff 615 #define LPC_I2C_BASE (0x40000000)
bogdanm 0:9b334a45a8ff 616 #define LPC_WWDT_BASE (0x40004000)
bogdanm 0:9b334a45a8ff 617 #define LPC_USART_BASE (0x40008000)
bogdanm 0:9b334a45a8ff 618 #define LPC_CT16B0_BASE (0x4000C000)
bogdanm 0:9b334a45a8ff 619 #define LPC_CT16B1_BASE (0x40010000)
bogdanm 0:9b334a45a8ff 620 #define LPC_CT32B0_BASE (0x40014000)
bogdanm 0:9b334a45a8ff 621 #define LPC_CT32B1_BASE (0x40018000)
bogdanm 0:9b334a45a8ff 622 #define LPC_ADC_BASE (0x4001C000)
bogdanm 0:9b334a45a8ff 623 #define LPC_PMU_BASE (0x40038000)
bogdanm 0:9b334a45a8ff 624 #define LPC_FLASHCTRL_BASE (0x4003C000)
bogdanm 0:9b334a45a8ff 625 #define LPC_SSP0_BASE (0x40040000)
bogdanm 0:9b334a45a8ff 626 #define LPC_SSP1_BASE (0x40058000)
bogdanm 0:9b334a45a8ff 627 #define LPC_IOCON_BASE (0x40044000)
bogdanm 0:9b334a45a8ff 628 #define LPC_SYSCON_BASE (0x40048000)
bogdanm 0:9b334a45a8ff 629 #define LPC_GPIO_PIN_INT_BASE (0x4004C000)
bogdanm 0:9b334a45a8ff 630 #define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
bogdanm 0:9b334a45a8ff 631 #define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
bogdanm 0:9b334a45a8ff 632 #define LPC_USB_BASE (0x40080000)
bogdanm 0:9b334a45a8ff 633 #define LPC_GPIO_BASE (0x50000000)
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 637 // ----- Peripheral declaration -----
bogdanm 0:9b334a45a8ff 638 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 #define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
bogdanm 0:9b334a45a8ff 641 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
bogdanm 0:9b334a45a8ff 642 #define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
bogdanm 0:9b334a45a8ff 643 #define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
bogdanm 0:9b334a45a8ff 644 #define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
bogdanm 0:9b334a45a8ff 645 #define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
bogdanm 0:9b334a45a8ff 646 #define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
bogdanm 0:9b334a45a8ff 647 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
bogdanm 0:9b334a45a8ff 648 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
bogdanm 0:9b334a45a8ff 649 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
bogdanm 0:9b334a45a8ff 650 #define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
bogdanm 0:9b334a45a8ff 651 #define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
bogdanm 0:9b334a45a8ff 652 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
bogdanm 0:9b334a45a8ff 653 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
bogdanm 0:9b334a45a8ff 654 #define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
bogdanm 0:9b334a45a8ff 655 #define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
bogdanm 0:9b334a45a8ff 656 #define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
bogdanm 0:9b334a45a8ff 657 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
bogdanm 0:9b334a45a8ff 658 #define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
bogdanm 0:9b334a45a8ff 659
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 /** @} */ /* End of group Device_Peripheral_Registers */
bogdanm 0:9b334a45a8ff 662 /** @} */ /* End of group (null) */
bogdanm 0:9b334a45a8ff 663 /** @} */ /* End of group LPC11Uxx */
bogdanm 0:9b334a45a8ff 664
bogdanm 0:9b334a45a8ff 665 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 666 }
bogdanm 0:9b334a45a8ff 667 #endif
bogdanm 0:9b334a45a8ff 668
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 #endif // __LPC11UXX_H__