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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:: <>
Date:: Wed Jan 04 16:58:05 2017 +0000
Revision:: 154:37f96f9d4de2
Child:: 165:e614a9f1c9e2

This updates the lib to the mbed lib v133

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	154:37f96f9d4de2	1	/**
<>	154:37f96f9d4de2	2	******************************************************************************
<>	154:37f96f9d4de2	3	* @file stm32f1xx_ll_rcc.h
<>	154:37f96f9d4de2	4	* @author MCD Application Team
<>	154:37f96f9d4de2	5	* @version $VERSION$
<>	154:37f96f9d4de2	6	* @date $DATE$
<>	154:37f96f9d4de2	7	* @brief Header file of RCC LL module.
<>	154:37f96f9d4de2	8	******************************************************************************
<>	154:37f96f9d4de2	9	* @attention
<>	154:37f96f9d4de2	10	*
<>	154:37f96f9d4de2	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	154:37f96f9d4de2	12	*
<>	154:37f96f9d4de2	13	* Redistribution and use in source and binary forms, with or without modification,
<>	154:37f96f9d4de2	14	* are permitted provided that the following conditions are met:
<>	154:37f96f9d4de2	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	154:37f96f9d4de2	16	* this list of conditions and the following disclaimer.
<>	154:37f96f9d4de2	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	154:37f96f9d4de2	18	* this list of conditions and the following disclaimer in the documentation
<>	154:37f96f9d4de2	19	* and/or other materials provided with the distribution.
<>	154:37f96f9d4de2	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	154:37f96f9d4de2	21	* may be used to endorse or promote products derived from this software
<>	154:37f96f9d4de2	22	* without specific prior written permission.
<>	154:37f96f9d4de2	23	*
<>	154:37f96f9d4de2	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	154:37f96f9d4de2	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	154:37f96f9d4de2	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	154:37f96f9d4de2	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	154:37f96f9d4de2	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	154:37f96f9d4de2	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	154:37f96f9d4de2	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	154:37f96f9d4de2	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	154:37f96f9d4de2	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	154:37f96f9d4de2	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	154:37f96f9d4de2	34	*
<>	154:37f96f9d4de2	35	******************************************************************************
<>	154:37f96f9d4de2	36	*/
<>	154:37f96f9d4de2	37
<>	154:37f96f9d4de2	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	154:37f96f9d4de2	39	#ifndef __STM32F1xx_LL_RCC_H
<>	154:37f96f9d4de2	40	#define __STM32F1xx_LL_RCC_H
<>	154:37f96f9d4de2	41
<>	154:37f96f9d4de2	42	#ifdef __cplusplus
<>	154:37f96f9d4de2	43	extern "C" {
<>	154:37f96f9d4de2	44	#endif
<>	154:37f96f9d4de2	45
<>	154:37f96f9d4de2	46	/* Includes ------------------------------------------------------------------*/
<>	154:37f96f9d4de2	47	#include "stm32f1xx.h"
<>	154:37f96f9d4de2	48
<>	154:37f96f9d4de2	49	/** @addtogroup STM32F1xx_LL_Driver
<>	154:37f96f9d4de2	50	* @{
<>	154:37f96f9d4de2	51	*/
<>	154:37f96f9d4de2	52
<>	154:37f96f9d4de2	53	#if defined(RCC)
<>	154:37f96f9d4de2	54
<>	154:37f96f9d4de2	55	/** @defgroup RCC_LL RCC
<>	154:37f96f9d4de2	56	* @{
<>	154:37f96f9d4de2	57	*/
<>	154:37f96f9d4de2	58
<>	154:37f96f9d4de2	59	/* Private types -------------------------------------------------------------*/
<>	154:37f96f9d4de2	60	/* Private variables ---------------------------------------------------------*/
<>	154:37f96f9d4de2	61	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
<>	154:37f96f9d4de2	62	* @{
<>	154:37f96f9d4de2	63	*/
<>	154:37f96f9d4de2	64
<>	154:37f96f9d4de2	65	/**
<>	154:37f96f9d4de2	66	* @}
<>	154:37f96f9d4de2	67	*/
<>	154:37f96f9d4de2	68
<>	154:37f96f9d4de2	69	/* Private constants ---------------------------------------------------------*/
<>	154:37f96f9d4de2	70	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
<>	154:37f96f9d4de2	71	* @{
<>	154:37f96f9d4de2	72	*/
<>	154:37f96f9d4de2	73	/* Define used for feature activation */
<>	154:37f96f9d4de2	74	#if defined(RCC_CFGR2_PREDIV2)
<>	154:37f96f9d4de2	75	#define RCC_PREDIV2_SUPPORT
<>	154:37f96f9d4de2	76	#endif /* RCC_CFGR2_PREDIV2 */
<>	154:37f96f9d4de2	77
<>	154:37f96f9d4de2	78	#if defined(RCC_CR_PLL3ON)
<>	154:37f96f9d4de2	79	#define RCC_PLLI2S_SUPPORT
<>	154:37f96f9d4de2	80	#endif /* RCC_CR_PLL3ON */
<>	154:37f96f9d4de2	81
<>	154:37f96f9d4de2	82	#if defined(RCC_CR_PLL2ON)
<>	154:37f96f9d4de2	83	#define RCC_PLL2_SUPPORT
<>	154:37f96f9d4de2	84	#endif /* RCC_CR_PLL2ON */
<>	154:37f96f9d4de2	85
<>	154:37f96f9d4de2	86	#if defined(RCC_CFGR2_PREDIV1SRC)
<>	154:37f96f9d4de2	87	#define RCC_SRC_PREDIV1_SUPPORT
<>	154:37f96f9d4de2	88	#endif /* RCC_CFGR2_PREDIV1SRC */
<>	154:37f96f9d4de2	89
<>	154:37f96f9d4de2	90	#if defined(RCC_CFGR2_PREDIV1)
<>	154:37f96f9d4de2	91	#define RCC_PREDIV1_DIV_2_16_SUPPORT
<>	154:37f96f9d4de2	92	#endif /* RCC_CFGR2_PREDIV1 */
<>	154:37f96f9d4de2	93
<>	154:37f96f9d4de2	94
<>	154:37f96f9d4de2	95	/* Defines used for the bit position in the register and perform offsets*/
<>	154:37f96f9d4de2	96	#define RCC_POSITION_HPRE (uint32_t)POSITION_VAL(RCC_CFGR_HPRE) /!< field position in register RCC_CFGR /
<>	154:37f96f9d4de2	97	#define RCC_POSITION_PPRE1 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE1) /!< field position in register RCC_CFGR /
<>	154:37f96f9d4de2	98	#define RCC_POSITION_PPRE2 (uint32_t)POSITION_VAL(RCC_CFGR_PPRE2) /!< field position in register RCC_CFGR /
<>	154:37f96f9d4de2	99	#define RCC_POSITION_HSICAL (uint32_t)POSITION_VAL(RCC_CR_HSICAL) /!< field position in register RCC_CR /
<>	154:37f96f9d4de2	100	#define RCC_POSITION_HSITRIM (uint32_t)POSITION_VAL(RCC_CR_HSITRIM) /!< field position in register RCC_CR /
<>	154:37f96f9d4de2	101	#define RCC_POSITION_PLLMUL (uint32_t)POSITION_VAL(RCC_CFGR_PLLMULL) /!< field position in register RCC_CFGR /
<>	154:37f96f9d4de2	102	#define RCC_POSITION_I2S2SRC 17U /!< field position in register RCC_CFGR2 /
<>	154:37f96f9d4de2	103	#define RCC_POSITION_I2S3SRC 18U /!< field position in register RCC_CFGR2 /
<>	154:37f96f9d4de2	104
<>	154:37f96f9d4de2	105	/**
<>	154:37f96f9d4de2	106	* @}
<>	154:37f96f9d4de2	107	*/
<>	154:37f96f9d4de2	108
<>	154:37f96f9d4de2	109	/* Private macros ------------------------------------------------------------*/
<>	154:37f96f9d4de2	110	#if defined(USE_FULL_LL_DRIVER)
<>	154:37f96f9d4de2	111	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
<>	154:37f96f9d4de2	112	* @{
<>	154:37f96f9d4de2	113	*/
<>	154:37f96f9d4de2	114	/**
<>	154:37f96f9d4de2	115	* @}
<>	154:37f96f9d4de2	116	*/
<>	154:37f96f9d4de2	117	#endif /USE_FULL_LL_DRIVER/
<>	154:37f96f9d4de2	118	/* Exported types ------------------------------------------------------------*/
<>	154:37f96f9d4de2	119	#if defined(USE_FULL_LL_DRIVER)
<>	154:37f96f9d4de2	120	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
<>	154:37f96f9d4de2	121	* @{
<>	154:37f96f9d4de2	122	*/
<>	154:37f96f9d4de2	123
<>	154:37f96f9d4de2	124	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
<>	154:37f96f9d4de2	125	* @{
<>	154:37f96f9d4de2	126	*/
<>	154:37f96f9d4de2	127
<>	154:37f96f9d4de2	128	/**
<>	154:37f96f9d4de2	129	* @brief RCC Clocks Frequency Structure
<>	154:37f96f9d4de2	130	*/
<>	154:37f96f9d4de2	131	typedef struct
<>	154:37f96f9d4de2	132	{
<>	154:37f96f9d4de2	133	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
<>	154:37f96f9d4de2	134	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
<>	154:37f96f9d4de2	135	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
<>	154:37f96f9d4de2	136	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
<>	154:37f96f9d4de2	137	} LL_RCC_ClocksTypeDef;
<>	154:37f96f9d4de2	138
<>	154:37f96f9d4de2	139	/**
<>	154:37f96f9d4de2	140	* @}
<>	154:37f96f9d4de2	141	*/
<>	154:37f96f9d4de2	142
<>	154:37f96f9d4de2	143	/**
<>	154:37f96f9d4de2	144	* @}
<>	154:37f96f9d4de2	145	*/
<>	154:37f96f9d4de2	146	#endif /* USE_FULL_LL_DRIVER */
<>	154:37f96f9d4de2	147
<>	154:37f96f9d4de2	148	/* Exported constants --------------------------------------------------------*/
<>	154:37f96f9d4de2	149	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
<>	154:37f96f9d4de2	150	* @{
<>	154:37f96f9d4de2	151	*/
<>	154:37f96f9d4de2	152
<>	154:37f96f9d4de2	153	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
<>	154:37f96f9d4de2	154	* @brief Defines used to adapt values of different oscillators
<>	154:37f96f9d4de2	155	* @note These values could be modified in the user environment according to
<>	154:37f96f9d4de2	156	* HW set-up.
<>	154:37f96f9d4de2	157	* @{
<>	154:37f96f9d4de2	158	*/
<>	154:37f96f9d4de2	159	#if !defined (HSE_VALUE)
<>	154:37f96f9d4de2	160	#define HSE_VALUE ((uint32_t)8000000U) /!< Value of the HSE oscillator in Hz /
<>	154:37f96f9d4de2	161	#endif /* HSE_VALUE */
<>	154:37f96f9d4de2	162
<>	154:37f96f9d4de2	163	#if !defined (HSI_VALUE)
<>	154:37f96f9d4de2	164	#define HSI_VALUE ((uint32_t)8000000U) /!< Value of the HSI oscillator in Hz /
<>	154:37f96f9d4de2	165	#endif /* HSI_VALUE */
<>	154:37f96f9d4de2	166
<>	154:37f96f9d4de2	167	#if !defined (LSE_VALUE)
<>	154:37f96f9d4de2	168	#define LSE_VALUE ((uint32_t)32768U) /!< Value of the LSE oscillator in Hz /
<>	154:37f96f9d4de2	169	#endif /* LSE_VALUE */
<>	154:37f96f9d4de2	170
<>	154:37f96f9d4de2	171	#if !defined (LSI_VALUE)
<>	154:37f96f9d4de2	172	#define LSI_VALUE ((uint32_t)32000U) /!< Value of the LSI oscillator in Hz /
<>	154:37f96f9d4de2	173	#endif /* LSI_VALUE */
<>	154:37f96f9d4de2	174	/**
<>	154:37f96f9d4de2	175	* @}
<>	154:37f96f9d4de2	176	*/
<>	154:37f96f9d4de2	177
<>	154:37f96f9d4de2	178	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
<>	154:37f96f9d4de2	179	* @brief Flags defines which can be used with LL_RCC_WriteReg function
<>	154:37f96f9d4de2	180	* @{
<>	154:37f96f9d4de2	181	*/
<>	154:37f96f9d4de2	182	#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /!< LSI Ready Interrupt Clear /
<>	154:37f96f9d4de2	183	#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /!< LSE Ready Interrupt Clear /
<>	154:37f96f9d4de2	184	#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /!< HSI Ready Interrupt Clear /
<>	154:37f96f9d4de2	185	#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /!< HSE Ready Interrupt Clear /
<>	154:37f96f9d4de2	186	#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /!< PLL Ready Interrupt Clear /
<>	154:37f96f9d4de2	187	#define LL_RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC /!< PLL3(PLLI2S) Ready Interrupt Clear /
<>	154:37f96f9d4de2	188	#define LL_RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC /!< PLL2 Ready Interrupt Clear /
<>	154:37f96f9d4de2	189	#define LL_RCC_CIR_CSSC RCC_CIR_CSSC /!< Clock Security System Interrupt Clear /
<>	154:37f96f9d4de2	190	/**
<>	154:37f96f9d4de2	191	* @}
<>	154:37f96f9d4de2	192	*/
<>	154:37f96f9d4de2	193
<>	154:37f96f9d4de2	194	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
<>	154:37f96f9d4de2	195	* @brief Flags defines which can be used with LL_RCC_ReadReg function
<>	154:37f96f9d4de2	196	* @{
<>	154:37f96f9d4de2	197	*/
<>	154:37f96f9d4de2	198	#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /!< LSI Ready Interrupt flag /
<>	154:37f96f9d4de2	199	#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /!< LSE Ready Interrupt flag /
<>	154:37f96f9d4de2	200	#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /!< HSI Ready Interrupt flag /
<>	154:37f96f9d4de2	201	#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /!< HSE Ready Interrupt flag /
<>	154:37f96f9d4de2	202	#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /!< PLL Ready Interrupt flag /
<>	154:37f96f9d4de2	203	#define LL_RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF /!< PLL3(PLLI2S) Ready Interrupt flag /
<>	154:37f96f9d4de2	204	#define LL_RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF /!< PLL2 Ready Interrupt flag /
<>	154:37f96f9d4de2	205	#define LL_RCC_CIR_CSSF RCC_CIR_CSSF /!< Clock Security System Interrupt flag /
<>	154:37f96f9d4de2	206	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
<>	154:37f96f9d4de2	207	#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /!< POR/PDR reset flag /
<>	154:37f96f9d4de2	208	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
<>	154:37f96f9d4de2	209	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
<>	154:37f96f9d4de2	210	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
<>	154:37f96f9d4de2	211	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
<>	154:37f96f9d4de2	212	/**
<>	154:37f96f9d4de2	213	* @}
<>	154:37f96f9d4de2	214	*/
<>	154:37f96f9d4de2	215
<>	154:37f96f9d4de2	216	/** @defgroup RCC_LL_EC_IT IT Defines
<>	154:37f96f9d4de2	217	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
<>	154:37f96f9d4de2	218	* @{
<>	154:37f96f9d4de2	219	*/
<>	154:37f96f9d4de2	220	#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /!< LSI Ready Interrupt Enable /
<>	154:37f96f9d4de2	221	#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /!< LSE Ready Interrupt Enable /
<>	154:37f96f9d4de2	222	#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /!< HSI Ready Interrupt Enable /
<>	154:37f96f9d4de2	223	#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /!< HSE Ready Interrupt Enable /
<>	154:37f96f9d4de2	224	#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /!< PLL Ready Interrupt Enable /
<>	154:37f96f9d4de2	225	#define LL_RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE /!< PLL3(PLLI2S) Ready Interrupt Enable /
<>	154:37f96f9d4de2	226	#define LL_RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE /!< PLL2 Ready Interrupt Enable /
<>	154:37f96f9d4de2	227	/**
<>	154:37f96f9d4de2	228	* @}
<>	154:37f96f9d4de2	229	*/
<>	154:37f96f9d4de2	230
<>	154:37f96f9d4de2	231	#if defined(RCC_PREDIV2_SUPPORT)
<>	154:37f96f9d4de2	232	/** @defgroup RCC_LL_EC_HSE_PREDIV2_DIV HSE PREDIV2 Division factor
<>	154:37f96f9d4de2	233	* @{
<>	154:37f96f9d4de2	234	*/
<>	154:37f96f9d4de2	235	#define LL_RCC_HSE_PREDIV2_DIV_1 RCC_CFGR2_PREDIV2_DIV1 /!< PREDIV2 input clock not divided /
<>	154:37f96f9d4de2	236	#define LL_RCC_HSE_PREDIV2_DIV_2 RCC_CFGR2_PREDIV2_DIV2 /!< PREDIV2 input clock divided by 2 /
<>	154:37f96f9d4de2	237	#define LL_RCC_HSE_PREDIV2_DIV_3 RCC_CFGR2_PREDIV2_DIV3 /!< PREDIV2 input clock divided by 3 /
<>	154:37f96f9d4de2	238	#define LL_RCC_HSE_PREDIV2_DIV_4 RCC_CFGR2_PREDIV2_DIV4 /!< PREDIV2 input clock divided by 4 /
<>	154:37f96f9d4de2	239	#define LL_RCC_HSE_PREDIV2_DIV_5 RCC_CFGR2_PREDIV2_DIV5 /!< PREDIV2 input clock divided by 5 /
<>	154:37f96f9d4de2	240	#define LL_RCC_HSE_PREDIV2_DIV_6 RCC_CFGR2_PREDIV2_DIV6 /!< PREDIV2 input clock divided by 6 /
<>	154:37f96f9d4de2	241	#define LL_RCC_HSE_PREDIV2_DIV_7 RCC_CFGR2_PREDIV2_DIV7 /!< PREDIV2 input clock divided by 7 /
<>	154:37f96f9d4de2	242	#define LL_RCC_HSE_PREDIV2_DIV_8 RCC_CFGR2_PREDIV2_DIV8 /!< PREDIV2 input clock divided by 8 /
<>	154:37f96f9d4de2	243	#define LL_RCC_HSE_PREDIV2_DIV_9 RCC_CFGR2_PREDIV2_DIV9 /!< PREDIV2 input clock divided by 9 /
<>	154:37f96f9d4de2	244	#define LL_RCC_HSE_PREDIV2_DIV_10 RCC_CFGR2_PREDIV2_DIV10 /!< PREDIV2 input clock divided by 10 /
<>	154:37f96f9d4de2	245	#define LL_RCC_HSE_PREDIV2_DIV_11 RCC_CFGR2_PREDIV2_DIV11 /!< PREDIV2 input clock divided by 11 /
<>	154:37f96f9d4de2	246	#define LL_RCC_HSE_PREDIV2_DIV_12 RCC_CFGR2_PREDIV2_DIV12 /!< PREDIV2 input clock divided by 12 /
<>	154:37f96f9d4de2	247	#define LL_RCC_HSE_PREDIV2_DIV_13 RCC_CFGR2_PREDIV2_DIV13 /!< PREDIV2 input clock divided by 13 /
<>	154:37f96f9d4de2	248	#define LL_RCC_HSE_PREDIV2_DIV_14 RCC_CFGR2_PREDIV2_DIV14 /!< PREDIV2 input clock divided by 14 /
<>	154:37f96f9d4de2	249	#define LL_RCC_HSE_PREDIV2_DIV_15 RCC_CFGR2_PREDIV2_DIV15 /!< PREDIV2 input clock divided by 15 /
<>	154:37f96f9d4de2	250	#define LL_RCC_HSE_PREDIV2_DIV_16 RCC_CFGR2_PREDIV2_DIV16 /!< PREDIV2 input clock divided by 16 /
<>	154:37f96f9d4de2	251	/**
<>	154:37f96f9d4de2	252	* @}
<>	154:37f96f9d4de2	253	*/
<>	154:37f96f9d4de2	254
<>	154:37f96f9d4de2	255	#endif /* RCC_PREDIV2_SUPPORT */
<>	154:37f96f9d4de2	256
<>	154:37f96f9d4de2	257	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
<>	154:37f96f9d4de2	258	* @{
<>	154:37f96f9d4de2	259	*/
<>	154:37f96f9d4de2	260	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
<>	154:37f96f9d4de2	261	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
<>	154:37f96f9d4de2	262	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
<>	154:37f96f9d4de2	263	/**
<>	154:37f96f9d4de2	264	* @}
<>	154:37f96f9d4de2	265	*/
<>	154:37f96f9d4de2	266
<>	154:37f96f9d4de2	267	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
<>	154:37f96f9d4de2	268	* @{
<>	154:37f96f9d4de2	269	*/
<>	154:37f96f9d4de2	270	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
<>	154:37f96f9d4de2	271	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
<>	154:37f96f9d4de2	272	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
<>	154:37f96f9d4de2	273	/**
<>	154:37f96f9d4de2	274	* @}
<>	154:37f96f9d4de2	275	*/
<>	154:37f96f9d4de2	276
<>	154:37f96f9d4de2	277	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
<>	154:37f96f9d4de2	278	* @{
<>	154:37f96f9d4de2	279	*/
<>	154:37f96f9d4de2	280	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
<>	154:37f96f9d4de2	281	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
<>	154:37f96f9d4de2	282	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
<>	154:37f96f9d4de2	283	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
<>	154:37f96f9d4de2	284	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
<>	154:37f96f9d4de2	285	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
<>	154:37f96f9d4de2	286	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
<>	154:37f96f9d4de2	287	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
<>	154:37f96f9d4de2	288	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
<>	154:37f96f9d4de2	289	/**
<>	154:37f96f9d4de2	290	* @}
<>	154:37f96f9d4de2	291	*/
<>	154:37f96f9d4de2	292
<>	154:37f96f9d4de2	293	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
<>	154:37f96f9d4de2	294	* @{
<>	154:37f96f9d4de2	295	*/
<>	154:37f96f9d4de2	296	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
<>	154:37f96f9d4de2	297	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
<>	154:37f96f9d4de2	298	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
<>	154:37f96f9d4de2	299	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
<>	154:37f96f9d4de2	300	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
<>	154:37f96f9d4de2	301	/**
<>	154:37f96f9d4de2	302	* @}
<>	154:37f96f9d4de2	303	*/
<>	154:37f96f9d4de2	304
<>	154:37f96f9d4de2	305	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
<>	154:37f96f9d4de2	306	* @{
<>	154:37f96f9d4de2	307	*/
<>	154:37f96f9d4de2	308	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
<>	154:37f96f9d4de2	309	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
<>	154:37f96f9d4de2	310	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
<>	154:37f96f9d4de2	311	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
<>	154:37f96f9d4de2	312	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
<>	154:37f96f9d4de2	313	/**
<>	154:37f96f9d4de2	314	* @}
<>	154:37f96f9d4de2	315	*/
<>	154:37f96f9d4de2	316
<>	154:37f96f9d4de2	317	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
<>	154:37f96f9d4de2	318	* @{
<>	154:37f96f9d4de2	319	*/
<>	154:37f96f9d4de2	320	#define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /!< MCO output disabled, no clock on MCO /
<>	154:37f96f9d4de2	321	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /!< SYSCLK selection as MCO source /
<>	154:37f96f9d4de2	322	#define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /!< HSI selection as MCO source /
<>	154:37f96f9d4de2	323	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /!< HSE selection as MCO source /
<>	154:37f96f9d4de2	324	#define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /!< PLL clock divided by 2/
<>	154:37f96f9d4de2	325	#if defined(RCC_CFGR_MCOSEL_PLL2CLK)
<>	154:37f96f9d4de2	326	#define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /!< PLL2 clock selected as MCO source/
<>	154:37f96f9d4de2	327	#endif /* RCC_CFGR_MCOSEL_PLL2CLK */
<>	154:37f96f9d4de2	328	#if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2)
<>	154:37f96f9d4de2	329	#define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /!< PLLI2S clock divided by 2 selected as MCO source/
<>	154:37f96f9d4de2	330	#endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */
<>	154:37f96f9d4de2	331	#if defined(RCC_CFGR_MCOSEL_EXT_HSE)
<>	154:37f96f9d4de2	332	#define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /!< XT1 external 3-25 MHz oscillator clock selected as MCO source /
<>	154:37f96f9d4de2	333	#endif /* RCC_CFGR_MCOSEL_EXT_HSE */
<>	154:37f96f9d4de2	334	#if defined(RCC_CFGR_MCOSEL_PLL3CLK)
<>	154:37f96f9d4de2	335	#define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /!< PLLI2S clock selected as MCO source /
<>	154:37f96f9d4de2	336	#endif /* RCC_CFGR_MCOSEL_PLL3CLK */
<>	154:37f96f9d4de2	337	/**
<>	154:37f96f9d4de2	338	* @}
<>	154:37f96f9d4de2	339	*/
<>	154:37f96f9d4de2	340
<>	154:37f96f9d4de2	341	#if defined(USE_FULL_LL_DRIVER)
<>	154:37f96f9d4de2	342	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
<>	154:37f96f9d4de2	343	* @{
<>	154:37f96f9d4de2	344	*/
<>	154:37f96f9d4de2	345	#define LL_RCC_PERIPH_FREQUENCY_NO (uint32_t)0x00000000U /!< No clock enabled for the peripheral /
<>	154:37f96f9d4de2	346	#define LL_RCC_PERIPH_FREQUENCY_NA (uint32_t)0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
<>	154:37f96f9d4de2	347	/**
<>	154:37f96f9d4de2	348	* @}
<>	154:37f96f9d4de2	349	*/
<>	154:37f96f9d4de2	350	#endif /* USE_FULL_LL_DRIVER */
<>	154:37f96f9d4de2	351
<>	154:37f96f9d4de2	352	#if defined(RCC_CFGR2_I2S2SRC)
<>	154:37f96f9d4de2	353	/** @defgroup RCC_LL_EC_I2S2CLKSOURCE Peripheral I2S clock source selection
<>	154:37f96f9d4de2	354	* @{
<>	154:37f96f9d4de2	355	*/
<>	154:37f96f9d4de2	356	#define LL_RCC_I2S2_CLKSOURCE_SYSCLK (uint32_t)(RCC_CFGR2_I2S2SRC \| (0x00000000 >> 16)) /!< System clock (SYSCLK) selected as I2S2 clock entry /
<>	154:37f96f9d4de2	357	#define LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S2SRC \| (RCC_CFGR2_I2S2SRC >> 16)) /!< PLLI2S VCO clock selected as I2S2 clock entry /
<>	154:37f96f9d4de2	358	#define LL_RCC_I2S3_CLKSOURCE_SYSCLK (uint32_t)(RCC_CFGR2_I2S3SRC \| (0x00000000 >> 16)) /!< System clock (SYSCLK) selected as I2S3 clock entry /
<>	154:37f96f9d4de2	359	#define LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO (uint32_t)(RCC_CFGR2_I2S3SRC \| (RCC_CFGR2_I2S3SRC >> 16)) /!< PLLI2S VCO clock selected as I2S3 clock entry /
<>	154:37f96f9d4de2	360	/**
<>	154:37f96f9d4de2	361	* @}
<>	154:37f96f9d4de2	362	*/
<>	154:37f96f9d4de2	363
<>	154:37f96f9d4de2	364	#endif /* RCC_CFGR2_I2S2SRC */
<>	154:37f96f9d4de2	365
<>	154:37f96f9d4de2	366	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	154:37f96f9d4de2	367	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
<>	154:37f96f9d4de2	368	* @{
<>	154:37f96f9d4de2	369	*/
<>	154:37f96f9d4de2	370	#if defined(RCC_CFGR_USBPRE)
<>	154:37f96f9d4de2	371	#define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /!< PLL clock is not divided /
<>	154:37f96f9d4de2	372	#define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 ((uint32_t)0x00000000) /!< PLL clock is divided by 1.5 /
<>	154:37f96f9d4de2	373	#endif /RCC_CFGR_USBPRE/
<>	154:37f96f9d4de2	374	#if defined(RCC_CFGR_OTGFSPRE)
<>	154:37f96f9d4de2	375	#define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /!< PLL clock is divided by 2 /
<>	154:37f96f9d4de2	376	#define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 ((uint32_t)0x00000000) /!< PLL clock is divided by 3 /
<>	154:37f96f9d4de2	377	#endif /RCC_CFGR_OTGFSPRE/
<>	154:37f96f9d4de2	378	/**
<>	154:37f96f9d4de2	379	* @}
<>	154:37f96f9d4de2	380	*/
<>	154:37f96f9d4de2	381
<>	154:37f96f9d4de2	382	#endif /* USB_OTG_FS \|\| USB */
<>	154:37f96f9d4de2	383
<>	154:37f96f9d4de2	384	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE_PCLK2 Peripheral ADC clock source selection
<>	154:37f96f9d4de2	385	* @{
<>	154:37f96f9d4de2	386	*/
<>	154:37f96f9d4de2	387	#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_2 RCC_CFGR_ADCPRE_DIV2 /ADC prescaler PCLK2 divided by 2/
<>	154:37f96f9d4de2	388	#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_4 RCC_CFGR_ADCPRE_DIV4 /ADC prescaler PCLK2 divided by 4/
<>	154:37f96f9d4de2	389	#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_6 RCC_CFGR_ADCPRE_DIV6 /ADC prescaler PCLK2 divided by 6/
<>	154:37f96f9d4de2	390	#define LL_RCC_ADC_CLKSRC_PCLK2_DIV_8 RCC_CFGR_ADCPRE_DIV8 /ADC prescaler PCLK2 divided by 8/
<>	154:37f96f9d4de2	391	/**
<>	154:37f96f9d4de2	392	* @}
<>	154:37f96f9d4de2	393	*/
<>	154:37f96f9d4de2	394
<>	154:37f96f9d4de2	395	#if defined(RCC_CFGR2_I2S2SRC)
<>	154:37f96f9d4de2	396	/** @defgroup RCC_LL_EC_I2S2 Peripheral I2S get clock source
<>	154:37f96f9d4de2	397	* @{
<>	154:37f96f9d4de2	398	*/
<>	154:37f96f9d4de2	399	#define LL_RCC_I2S2_CLKSOURCE RCC_CFGR2_I2S2SRC /!< I2S2 Clock source selection /
<>	154:37f96f9d4de2	400	#define LL_RCC_I2S3_CLKSOURCE RCC_CFGR2_I2S3SRC /!< I2S3 Clock source selection /
<>	154:37f96f9d4de2	401	/**
<>	154:37f96f9d4de2	402	* @}
<>	154:37f96f9d4de2	403	*/
<>	154:37f96f9d4de2	404
<>	154:37f96f9d4de2	405	#endif /* RCC_CFGR2_I2S2SRC */
<>	154:37f96f9d4de2	406
<>	154:37f96f9d4de2	407	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	154:37f96f9d4de2	408	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
<>	154:37f96f9d4de2	409	* @{
<>	154:37f96f9d4de2	410	*/
<>	154:37f96f9d4de2	411	#define LL_RCC_USB_CLKSOURCE ((uint32_t)0x00400000) /!< USB Clock source selection /
<>	154:37f96f9d4de2	412	/**
<>	154:37f96f9d4de2	413	* @}
<>	154:37f96f9d4de2	414	*/
<>	154:37f96f9d4de2	415
<>	154:37f96f9d4de2	416	#endif /* USB_OTG_FS \|\| USB */
<>	154:37f96f9d4de2	417
<>	154:37f96f9d4de2	418	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
<>	154:37f96f9d4de2	419	* @{
<>	154:37f96f9d4de2	420	*/
<>	154:37f96f9d4de2	421	#define LL_RCC_ADC_CLKSOURCE RCC_CFGR_ADCPRE /!< ADC Clock source selection /
<>	154:37f96f9d4de2	422	/**
<>	154:37f96f9d4de2	423	* @}
<>	154:37f96f9d4de2	424	*/
<>	154:37f96f9d4de2	425
<>	154:37f96f9d4de2	426	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
<>	154:37f96f9d4de2	427	* @{
<>	154:37f96f9d4de2	428	*/
<>	154:37f96f9d4de2	429	#define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)0x00000000U /!< No clock used as RTC clock /
<>	154:37f96f9d4de2	430	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
<>	154:37f96f9d4de2	431	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
<>	154:37f96f9d4de2	432	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 128 used as RTC clock /
<>	154:37f96f9d4de2	433	/**
<>	154:37f96f9d4de2	434	* @}
<>	154:37f96f9d4de2	435	*/
<>	154:37f96f9d4de2	436
<>	154:37f96f9d4de2	437	/** @defgroup RCC_LL_EC_PLL_MUL PLL Multiplicator factor
<>	154:37f96f9d4de2	438	* @{
<>	154:37f96f9d4de2	439	*/
<>	154:37f96f9d4de2	440	#if defined(RCC_CFGR_PLLMULL2)
<>	154:37f96f9d4de2	441	#define LL_RCC_PLL_MUL_2 RCC_CFGR_PLLMULL2 /!< PLL input clock2 */
<>	154:37f96f9d4de2	442	#endif /RCC_CFGR_PLLMULL2/
<>	154:37f96f9d4de2	443	#if defined(RCC_CFGR_PLLMULL3)
<>	154:37f96f9d4de2	444	#define LL_RCC_PLL_MUL_3 RCC_CFGR_PLLMULL3 /!< PLL input clock3 */
<>	154:37f96f9d4de2	445	#endif /RCC_CFGR_PLLMULL3/
<>	154:37f96f9d4de2	446	#define LL_RCC_PLL_MUL_4 RCC_CFGR_PLLMULL4 /!< PLL input clock4 */
<>	154:37f96f9d4de2	447	#define LL_RCC_PLL_MUL_5 RCC_CFGR_PLLMULL5 /!< PLL input clock5 */
<>	154:37f96f9d4de2	448	#define LL_RCC_PLL_MUL_6 RCC_CFGR_PLLMULL6 /!< PLL input clock6 */
<>	154:37f96f9d4de2	449	#define LL_RCC_PLL_MUL_7 RCC_CFGR_PLLMULL7 /!< PLL input clock7 */
<>	154:37f96f9d4de2	450	#define LL_RCC_PLL_MUL_8 RCC_CFGR_PLLMULL8 /!< PLL input clock8 */
<>	154:37f96f9d4de2	451	#define LL_RCC_PLL_MUL_9 RCC_CFGR_PLLMULL9 /!< PLL input clock9 */
<>	154:37f96f9d4de2	452	#if defined(RCC_CFGR_PLLMULL6_5)
<>	154:37f96f9d4de2	453	#define LL_RCC_PLL_MUL_6_5 RCC_CFGR_PLLMULL6_5 /!< PLL input clock6 */
<>	154:37f96f9d4de2	454	#else
<>	154:37f96f9d4de2	455	#define LL_RCC_PLL_MUL_10 RCC_CFGR_PLLMULL10 /!< PLL input clock10 */
<>	154:37f96f9d4de2	456	#define LL_RCC_PLL_MUL_11 RCC_CFGR_PLLMULL11 /!< PLL input clock11 */
<>	154:37f96f9d4de2	457	#define LL_RCC_PLL_MUL_12 RCC_CFGR_PLLMULL12 /!< PLL input clock12 */
<>	154:37f96f9d4de2	458	#define LL_RCC_PLL_MUL_13 RCC_CFGR_PLLMULL13 /!< PLL input clock13 */
<>	154:37f96f9d4de2	459	#define LL_RCC_PLL_MUL_14 RCC_CFGR_PLLMULL14 /!< PLL input clock14 */
<>	154:37f96f9d4de2	460	#define LL_RCC_PLL_MUL_15 RCC_CFGR_PLLMULL15 /!< PLL input clock15 */
<>	154:37f96f9d4de2	461	#define LL_RCC_PLL_MUL_16 RCC_CFGR_PLLMULL16 /!< PLL input clock16 */
<>	154:37f96f9d4de2	462	#endif /RCC_CFGR_PLLMULL6_5/
<>	154:37f96f9d4de2	463	/**
<>	154:37f96f9d4de2	464	* @}
<>	154:37f96f9d4de2	465	*/
<>	154:37f96f9d4de2	466
<>	154:37f96f9d4de2	467	/** @defgroup RCC_LL_EC_PLLSOURCE PLL SOURCE
<>	154:37f96f9d4de2	468	* @{
<>	154:37f96f9d4de2	469	*/
<>	154:37f96f9d4de2	470	#define LL_RCC_PLLSOURCE_HSI_DIV_2 ((uint32_t)0x00000000U) /!< HSI clock divided by 2 selected as PLL entry clock source /
<>	154:37f96f9d4de2	471	#define LL_RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /!< HSE/PREDIV1 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	472	#if defined(RCC_SRC_PREDIV1_SUPPORT)
<>	154:37f96f9d4de2	473	#define LL_RCC_PLLSOURCE_PLL2 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/PREDIV1 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	474	#endif /RCC_SRC_PREDIV1_SUPPORT/
<>	154:37f96f9d4de2	475
<>	154:37f96f9d4de2	476	#define LL_RCC_PLLSOURCE_HSE_DIV_1 RCC_CFGR_PLLSRC /!< HSE clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	477	#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT)
<>	154:37f96f9d4de2	478	#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV2) /!< HSE/2 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	479	#define LL_RCC_PLLSOURCE_HSE_DIV_3 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV3) /!< HSE/3 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	480	#define LL_RCC_PLLSOURCE_HSE_DIV_4 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV4) /!< HSE/4 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	481	#define LL_RCC_PLLSOURCE_HSE_DIV_5 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV5) /!< HSE/5 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	482	#define LL_RCC_PLLSOURCE_HSE_DIV_6 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV6) /!< HSE/6 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	483	#define LL_RCC_PLLSOURCE_HSE_DIV_7 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV7) /!< HSE/7 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	484	#define LL_RCC_PLLSOURCE_HSE_DIV_8 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV8) /!< HSE/8 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	485	#define LL_RCC_PLLSOURCE_HSE_DIV_9 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV9) /!< HSE/9 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	486	#define LL_RCC_PLLSOURCE_HSE_DIV_10 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV10) /!< HSE/10 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	487	#define LL_RCC_PLLSOURCE_HSE_DIV_11 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV11) /!< HSE/11 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	488	#define LL_RCC_PLLSOURCE_HSE_DIV_12 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV12) /!< HSE/12 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	489	#define LL_RCC_PLLSOURCE_HSE_DIV_13 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV13) /!< HSE/13 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	490	#define LL_RCC_PLLSOURCE_HSE_DIV_14 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV14) /!< HSE/14 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	491	#define LL_RCC_PLLSOURCE_HSE_DIV_15 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV15) /!< HSE/15 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	492	#define LL_RCC_PLLSOURCE_HSE_DIV_16 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV16) /!< HSE/16 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	493	#if defined(RCC_SRC_PREDIV1_SUPPORT)
<>	154:37f96f9d4de2	494	#define LL_RCC_PLLSOURCE_PLL2_DIV_2 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV2 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/2 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	495	#define LL_RCC_PLLSOURCE_PLL2_DIV_3 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV3 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/3 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	496	#define LL_RCC_PLLSOURCE_PLL2_DIV_4 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV4 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/4 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	497	#define LL_RCC_PLLSOURCE_PLL2_DIV_5 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV5 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/5 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	498	#define LL_RCC_PLLSOURCE_PLL2_DIV_6 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV6 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/6 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	499	#define LL_RCC_PLLSOURCE_PLL2_DIV_7 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV7 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/7 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	500	#define LL_RCC_PLLSOURCE_PLL2_DIV_8 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV8 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/8 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	501	#define LL_RCC_PLLSOURCE_PLL2_DIV_9 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV9 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/9 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	502	#define LL_RCC_PLLSOURCE_PLL2_DIV_10 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV10 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/10 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	503	#define LL_RCC_PLLSOURCE_PLL2_DIV_11 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV11 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/11 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	504	#define LL_RCC_PLLSOURCE_PLL2_DIV_12 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV12 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/12 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	505	#define LL_RCC_PLLSOURCE_PLL2_DIV_13 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV13 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/13 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	506	#define LL_RCC_PLLSOURCE_PLL2_DIV_14 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV14 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/14 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	507	#define LL_RCC_PLLSOURCE_PLL2_DIV_15 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV15 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/15 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	508	#define LL_RCC_PLLSOURCE_PLL2_DIV_16 (RCC_CFGR_PLLSRC \| RCC_CFGR2_PREDIV1_DIV16 \| RCC_CFGR2_PREDIV1SRC << 4) /!< PLL2/16 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	509	#endif /RCC_SRC_PREDIV1_SUPPORT/
<>	154:37f96f9d4de2	510	#else
<>	154:37f96f9d4de2	511	#define LL_RCC_PLLSOURCE_HSE_DIV_2 (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE) /!< HSE/2 clock selected as PLL entry clock source /
<>	154:37f96f9d4de2	512	#endif /RCC_PREDIV1_DIV_2_16_SUPPORT/
<>	154:37f96f9d4de2	513	/**
<>	154:37f96f9d4de2	514	* @}
<>	154:37f96f9d4de2	515	*/
<>	154:37f96f9d4de2	516
<>	154:37f96f9d4de2	517	/** @defgroup RCC_LL_EC_PREDIV_DIV PREDIV Division factor
<>	154:37f96f9d4de2	518	* @{
<>	154:37f96f9d4de2	519	*/
<>	154:37f96f9d4de2	520	#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT)
<>	154:37f96f9d4de2	521	#define LL_RCC_PREDIV_DIV_1 RCC_CFGR2_PREDIV1_DIV1 /!< PREDIV1 input clock not divided /
<>	154:37f96f9d4de2	522	#define LL_RCC_PREDIV_DIV_2 RCC_CFGR2_PREDIV1_DIV2 /!< PREDIV1 input clock divided by 2 /
<>	154:37f96f9d4de2	523	#define LL_RCC_PREDIV_DIV_3 RCC_CFGR2_PREDIV1_DIV3 /!< PREDIV1 input clock divided by 3 /
<>	154:37f96f9d4de2	524	#define LL_RCC_PREDIV_DIV_4 RCC_CFGR2_PREDIV1_DIV4 /!< PREDIV1 input clock divided by 4 /
<>	154:37f96f9d4de2	525	#define LL_RCC_PREDIV_DIV_5 RCC_CFGR2_PREDIV1_DIV5 /!< PREDIV1 input clock divided by 5 /
<>	154:37f96f9d4de2	526	#define LL_RCC_PREDIV_DIV_6 RCC_CFGR2_PREDIV1_DIV6 /!< PREDIV1 input clock divided by 6 /
<>	154:37f96f9d4de2	527	#define LL_RCC_PREDIV_DIV_7 RCC_CFGR2_PREDIV1_DIV7 /!< PREDIV1 input clock divided by 7 /
<>	154:37f96f9d4de2	528	#define LL_RCC_PREDIV_DIV_8 RCC_CFGR2_PREDIV1_DIV8 /!< PREDIV1 input clock divided by 8 /
<>	154:37f96f9d4de2	529	#define LL_RCC_PREDIV_DIV_9 RCC_CFGR2_PREDIV1_DIV9 /!< PREDIV1 input clock divided by 9 /
<>	154:37f96f9d4de2	530	#define LL_RCC_PREDIV_DIV_10 RCC_CFGR2_PREDIV1_DIV10 /!< PREDIV1 input clock divided by 10 /
<>	154:37f96f9d4de2	531	#define LL_RCC_PREDIV_DIV_11 RCC_CFGR2_PREDIV1_DIV11 /!< PREDIV1 input clock divided by 11 /
<>	154:37f96f9d4de2	532	#define LL_RCC_PREDIV_DIV_12 RCC_CFGR2_PREDIV1_DIV12 /!< PREDIV1 input clock divided by 12 /
<>	154:37f96f9d4de2	533	#define LL_RCC_PREDIV_DIV_13 RCC_CFGR2_PREDIV1_DIV13 /!< PREDIV1 input clock divided by 13 /
<>	154:37f96f9d4de2	534	#define LL_RCC_PREDIV_DIV_14 RCC_CFGR2_PREDIV1_DIV14 /!< PREDIV1 input clock divided by 14 /
<>	154:37f96f9d4de2	535	#define LL_RCC_PREDIV_DIV_15 RCC_CFGR2_PREDIV1_DIV15 /!< PREDIV1 input clock divided by 15 /
<>	154:37f96f9d4de2	536	#define LL_RCC_PREDIV_DIV_16 RCC_CFGR2_PREDIV1_DIV16 /!< PREDIV1 input clock divided by 16 /
<>	154:37f96f9d4de2	537	#else
<>	154:37f96f9d4de2	538	#define LL_RCC_PREDIV_DIV_1 ((uint32_t)0x00000000U) /!< HSE divider clock clock not divided /
<>	154:37f96f9d4de2	539	#define LL_RCC_PREDIV_DIV_2 RCC_CFGR_PLLXTPRE /!< HSE divider clock divided by 2 for PLL entry /
<>	154:37f96f9d4de2	540	#endif /RCC_PREDIV1_DIV_2_16_SUPPORT/
<>	154:37f96f9d4de2	541	/**
<>	154:37f96f9d4de2	542	* @}
<>	154:37f96f9d4de2	543	*/
<>	154:37f96f9d4de2	544
<>	154:37f96f9d4de2	545	#if defined(RCC_PLLI2S_SUPPORT)
<>	154:37f96f9d4de2	546	/** @defgroup RCC_LL_EC_PLLI2S_MUL PLLI2S MUL
<>	154:37f96f9d4de2	547	* @{
<>	154:37f96f9d4de2	548	*/
<>	154:37f96f9d4de2	549	#define LL_RCC_PLLI2S_MUL_8 RCC_CFGR2_PLL3MUL8 /!< PLLI2S input clock 8 */
<>	154:37f96f9d4de2	550	#define LL_RCC_PLLI2S_MUL_9 RCC_CFGR2_PLL3MUL9 /!< PLLI2S input clock 9 */
<>	154:37f96f9d4de2	551	#define LL_RCC_PLLI2S_MUL_10 RCC_CFGR2_PLL3MUL10 /!< PLLI2S input clock 10 */
<>	154:37f96f9d4de2	552	#define LL_RCC_PLLI2S_MUL_11 RCC_CFGR2_PLL3MUL11 /!< PLLI2S input clock 11 */
<>	154:37f96f9d4de2	553	#define LL_RCC_PLLI2S_MUL_12 RCC_CFGR2_PLL3MUL12 /!< PLLI2S input clock 12 */
<>	154:37f96f9d4de2	554	#define LL_RCC_PLLI2S_MUL_13 RCC_CFGR2_PLL3MUL13 /!< PLLI2S input clock 13 */
<>	154:37f96f9d4de2	555	#define LL_RCC_PLLI2S_MUL_14 RCC_CFGR2_PLL3MUL14 /!< PLLI2S input clock 14 */
<>	154:37f96f9d4de2	556	#define LL_RCC_PLLI2S_MUL_16 RCC_CFGR2_PLL3MUL16 /!< PLLI2S input clock 16 */
<>	154:37f96f9d4de2	557	#define LL_RCC_PLLI2S_MUL_20 RCC_CFGR2_PLL3MUL20 /!< PLLI2S input clock 20 */
<>	154:37f96f9d4de2	558	/**
<>	154:37f96f9d4de2	559	* @}
<>	154:37f96f9d4de2	560	*/
<>	154:37f96f9d4de2	561
<>	154:37f96f9d4de2	562	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	563
<>	154:37f96f9d4de2	564	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	565	/** @defgroup RCC_LL_EC_PLL2_MUL PLL2 MUL
<>	154:37f96f9d4de2	566	* @{
<>	154:37f96f9d4de2	567	*/
<>	154:37f96f9d4de2	568	#define LL_RCC_PLL2_MUL_8 RCC_CFGR2_PLL2MUL8 /!< PLL2 input clock 8 */
<>	154:37f96f9d4de2	569	#define LL_RCC_PLL2_MUL_9 RCC_CFGR2_PLL2MUL9 /!< PLL2 input clock 9 */
<>	154:37f96f9d4de2	570	#define LL_RCC_PLL2_MUL_10 RCC_CFGR2_PLL2MUL10 /!< PLL2 input clock 10 */
<>	154:37f96f9d4de2	571	#define LL_RCC_PLL2_MUL_11 RCC_CFGR2_PLL2MUL11 /!< PLL2 input clock 11 */
<>	154:37f96f9d4de2	572	#define LL_RCC_PLL2_MUL_12 RCC_CFGR2_PLL2MUL12 /!< PLL2 input clock 12 */
<>	154:37f96f9d4de2	573	#define LL_RCC_PLL2_MUL_13 RCC_CFGR2_PLL2MUL13 /!< PLL2 input clock 13 */
<>	154:37f96f9d4de2	574	#define LL_RCC_PLL2_MUL_14 RCC_CFGR2_PLL2MUL14 /!< PLL2 input clock 14 */
<>	154:37f96f9d4de2	575	#define LL_RCC_PLL2_MUL_16 RCC_CFGR2_PLL2MUL16 /!< PLL2 input clock 16 */
<>	154:37f96f9d4de2	576	#define LL_RCC_PLL2_MUL_20 RCC_CFGR2_PLL2MUL20 /!< PLL2 input clock 20 */
<>	154:37f96f9d4de2	577	/**
<>	154:37f96f9d4de2	578	* @}
<>	154:37f96f9d4de2	579	*/
<>	154:37f96f9d4de2	580
<>	154:37f96f9d4de2	581	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	582
<>	154:37f96f9d4de2	583	/**
<>	154:37f96f9d4de2	584	* @}
<>	154:37f96f9d4de2	585	*/
<>	154:37f96f9d4de2	586
<>	154:37f96f9d4de2	587	/* Exported macro ------------------------------------------------------------*/
<>	154:37f96f9d4de2	588	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
<>	154:37f96f9d4de2	589	* @{
<>	154:37f96f9d4de2	590	*/
<>	154:37f96f9d4de2	591
<>	154:37f96f9d4de2	592	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
<>	154:37f96f9d4de2	593	* @{
<>	154:37f96f9d4de2	594	*/
<>	154:37f96f9d4de2	595
<>	154:37f96f9d4de2	596	/**
<>	154:37f96f9d4de2	597	* @brief Write a value in RCC register
<>	154:37f96f9d4de2	598	* @param __REG__ Register to be written
<>	154:37f96f9d4de2	599	* @param __VALUE__ Value to be written in the register
<>	154:37f96f9d4de2	600	* @retval None
<>	154:37f96f9d4de2	601	*/
<>	154:37f96f9d4de2	602	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
<>	154:37f96f9d4de2	603
<>	154:37f96f9d4de2	604	/**
<>	154:37f96f9d4de2	605	* @brief Read a value in RCC register
<>	154:37f96f9d4de2	606	* @param __REG__ Register to be read
<>	154:37f96f9d4de2	607	* @retval Register value
<>	154:37f96f9d4de2	608	*/
<>	154:37f96f9d4de2	609	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
<>	154:37f96f9d4de2	610	/**
<>	154:37f96f9d4de2	611	* @}
<>	154:37f96f9d4de2	612	*/
<>	154:37f96f9d4de2	613
<>	154:37f96f9d4de2	614	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
<>	154:37f96f9d4de2	615	* @{
<>	154:37f96f9d4de2	616	*/
<>	154:37f96f9d4de2	617
<>	154:37f96f9d4de2	618	#if defined(RCC_CFGR_PLLMULL6_5)
<>	154:37f96f9d4de2	619	/**
<>	154:37f96f9d4de2	620	* @brief Helper macro to calculate the PLLCLK frequency
<>	154:37f96f9d4de2	621	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator());
<>	154:37f96f9d4de2	622	* @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 / HSI div 2 / PLL2 div Prediv1)
<>	154:37f96f9d4de2	623	* @param __PLLMUL__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	624	* @arg @ref LL_RCC_PLL_MUL_4
<>	154:37f96f9d4de2	625	* @arg @ref LL_RCC_PLL_MUL_5
<>	154:37f96f9d4de2	626	* @arg @ref LL_RCC_PLL_MUL_6
<>	154:37f96f9d4de2	627	* @arg @ref LL_RCC_PLL_MUL_7
<>	154:37f96f9d4de2	628	* @arg @ref LL_RCC_PLL_MUL_8
<>	154:37f96f9d4de2	629	* @arg @ref LL_RCC_PLL_MUL_9
<>	154:37f96f9d4de2	630	* @arg @ref LL_RCC_PLL_MUL_6_5
<>	154:37f96f9d4de2	631	* @retval PLL clock frequency (in Hz)
<>	154:37f96f9d4de2	632	*/
<>	154:37f96f9d4de2	633	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) \
<>	154:37f96f9d4de2	634	(((__PLLMUL__) != RCC_CFGR_PLLMULL6_5) ? \
<>	154:37f96f9d4de2	635	((__INPUTFREQ__) * ((((__PLLMUL__) & RCC_CFGR_PLLMULL) >> RCC_POSITION_PLLMUL) + 2U)) :\
<>	154:37f96f9d4de2	636	(((__INPUTFREQ__) * 13U) / 2U))
<>	154:37f96f9d4de2	637
<>	154:37f96f9d4de2	638	#else
<>	154:37f96f9d4de2	639	/**
<>	154:37f96f9d4de2	640	* @brief Helper macro to calculate the PLLCLK frequency
<>	154:37f96f9d4de2	641	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE / (@ref LL_RCC_PLL_GetPrediv () + 1), @ref LL_RCC_PLL_GetMultiplicator ());
<>	154:37f96f9d4de2	642	* @param __INPUTFREQ__ PLL Input frequency (based on HSE div Prediv1 or div 2 / HSI div 2)
<>	154:37f96f9d4de2	643	* @param __PLLMUL__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	644	* @arg @ref LL_RCC_PLL_MUL_2
<>	154:37f96f9d4de2	645	* @arg @ref LL_RCC_PLL_MUL_3
<>	154:37f96f9d4de2	646	* @arg @ref LL_RCC_PLL_MUL_4
<>	154:37f96f9d4de2	647	* @arg @ref LL_RCC_PLL_MUL_5
<>	154:37f96f9d4de2	648	* @arg @ref LL_RCC_PLL_MUL_6
<>	154:37f96f9d4de2	649	* @arg @ref LL_RCC_PLL_MUL_7
<>	154:37f96f9d4de2	650	* @arg @ref LL_RCC_PLL_MUL_8
<>	154:37f96f9d4de2	651	* @arg @ref LL_RCC_PLL_MUL_9
<>	154:37f96f9d4de2	652	* @arg @ref LL_RCC_PLL_MUL_10
<>	154:37f96f9d4de2	653	* @arg @ref LL_RCC_PLL_MUL_11
<>	154:37f96f9d4de2	654	* @arg @ref LL_RCC_PLL_MUL_12
<>	154:37f96f9d4de2	655	* @arg @ref LL_RCC_PLL_MUL_13
<>	154:37f96f9d4de2	656	* @arg @ref LL_RCC_PLL_MUL_14
<>	154:37f96f9d4de2	657	* @arg @ref LL_RCC_PLL_MUL_15
<>	154:37f96f9d4de2	658	* @arg @ref LL_RCC_PLL_MUL_16
<>	154:37f96f9d4de2	659	* @retval PLL clock frequency (in Hz)
<>	154:37f96f9d4de2	660	*/
<>	154:37f96f9d4de2	661	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLMUL__) ((__INPUTFREQ__) * (((__PLLMUL__) >> RCC_POSITION_PLLMUL) + 2U))
<>	154:37f96f9d4de2	662	#endif /* RCC_CFGR_PLLMULL6_5 */
<>	154:37f96f9d4de2	663
<>	154:37f96f9d4de2	664	#if defined(RCC_PLLI2S_SUPPORT)
<>	154:37f96f9d4de2	665	/**
<>	154:37f96f9d4de2	666	* @brief Helper macro to calculate the PLLI2S frequency
<>	154:37f96f9d4de2	667	* @note ex: @ref __LL_RCC_CALC_PLLI2SCLK_FREQ (HSE_VALUE, @ref LL_RCC_PLLI2S_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
<>	154:37f96f9d4de2	668	* @param __INPUTFREQ__ PLLI2S Input frequency (based on HSE value)
<>	154:37f96f9d4de2	669	* @param __PLLI2SMUL__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	670	* @arg @ref LL_RCC_PLLI2S_MUL_8
<>	154:37f96f9d4de2	671	* @arg @ref LL_RCC_PLLI2S_MUL_9
<>	154:37f96f9d4de2	672	* @arg @ref LL_RCC_PLLI2S_MUL_10
<>	154:37f96f9d4de2	673	* @arg @ref LL_RCC_PLLI2S_MUL_11
<>	154:37f96f9d4de2	674	* @arg @ref LL_RCC_PLLI2S_MUL_12
<>	154:37f96f9d4de2	675	* @arg @ref LL_RCC_PLLI2S_MUL_13
<>	154:37f96f9d4de2	676	* @arg @ref LL_RCC_PLLI2S_MUL_14
<>	154:37f96f9d4de2	677	* @arg @ref LL_RCC_PLLI2S_MUL_16
<>	154:37f96f9d4de2	678	* @arg @ref LL_RCC_PLLI2S_MUL_20
<>	154:37f96f9d4de2	679	* @param __PLLI2SDIV__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	680	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<>	154:37f96f9d4de2	681	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<>	154:37f96f9d4de2	682	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<>	154:37f96f9d4de2	683	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<>	154:37f96f9d4de2	684	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<>	154:37f96f9d4de2	685	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<>	154:37f96f9d4de2	686	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<>	154:37f96f9d4de2	687	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<>	154:37f96f9d4de2	688	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<>	154:37f96f9d4de2	689	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<>	154:37f96f9d4de2	690	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<>	154:37f96f9d4de2	691	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<>	154:37f96f9d4de2	692	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<>	154:37f96f9d4de2	693	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<>	154:37f96f9d4de2	694	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<>	154:37f96f9d4de2	695	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<>	154:37f96f9d4de2	696	* @retval PLLI2S clock frequency (in Hz)
<>	154:37f96f9d4de2	697	*/
<>	154:37f96f9d4de2	698	#define __LL_RCC_CALC_PLLI2SCLK_FREQ(__INPUTFREQ__, __PLLI2SMUL__, __PLLI2SDIV__) (((__INPUTFREQ__) * (((__PLLI2SMUL__) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2U)) / (((__PLLI2SDIV__) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1U))
<>	154:37f96f9d4de2	699	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	700
<>	154:37f96f9d4de2	701	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	702	/**
<>	154:37f96f9d4de2	703	* @brief Helper macro to calculate the PLL2 frequency
<>	154:37f96f9d4de2	704	* @note ex: @ref __LL_RCC_CALC_PLL2CLK_FREQ (HSE_VALUE, @ref LL_RCC_PLL2_GetMultiplicator (), @ref LL_RCC_HSE_GetPrediv2 ());
<>	154:37f96f9d4de2	705	* @param __INPUTFREQ__ PLL2 Input frequency (based on HSE value)
<>	154:37f96f9d4de2	706	* @param __PLL2MUL__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	707	* @arg @ref LL_RCC_PLL2_MUL_8
<>	154:37f96f9d4de2	708	* @arg @ref LL_RCC_PLL2_MUL_9
<>	154:37f96f9d4de2	709	* @arg @ref LL_RCC_PLL2_MUL_10
<>	154:37f96f9d4de2	710	* @arg @ref LL_RCC_PLL2_MUL_11
<>	154:37f96f9d4de2	711	* @arg @ref LL_RCC_PLL2_MUL_12
<>	154:37f96f9d4de2	712	* @arg @ref LL_RCC_PLL2_MUL_13
<>	154:37f96f9d4de2	713	* @arg @ref LL_RCC_PLL2_MUL_14
<>	154:37f96f9d4de2	714	* @arg @ref LL_RCC_PLL2_MUL_16
<>	154:37f96f9d4de2	715	* @arg @ref LL_RCC_PLL2_MUL_20
<>	154:37f96f9d4de2	716	* @param __PLL2DIV__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	717	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<>	154:37f96f9d4de2	718	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<>	154:37f96f9d4de2	719	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<>	154:37f96f9d4de2	720	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<>	154:37f96f9d4de2	721	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<>	154:37f96f9d4de2	722	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<>	154:37f96f9d4de2	723	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<>	154:37f96f9d4de2	724	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<>	154:37f96f9d4de2	725	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<>	154:37f96f9d4de2	726	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<>	154:37f96f9d4de2	727	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<>	154:37f96f9d4de2	728	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<>	154:37f96f9d4de2	729	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<>	154:37f96f9d4de2	730	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<>	154:37f96f9d4de2	731	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<>	154:37f96f9d4de2	732	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<>	154:37f96f9d4de2	733	* @retval PLL2 clock frequency (in Hz)
<>	154:37f96f9d4de2	734	*/
<>	154:37f96f9d4de2	735	#define __LL_RCC_CALC_PLL2CLK_FREQ(__INPUTFREQ__, __PLL2MUL__, __PLL2DIV__) (((__INPUTFREQ__) * (((__PLL2MUL__) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2U)) / (((__PLL2DIV__) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1U))
<>	154:37f96f9d4de2	736	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	737
<>	154:37f96f9d4de2	738	/**
<>	154:37f96f9d4de2	739	* @brief Helper macro to calculate the HCLK frequency
<>	154:37f96f9d4de2	740	* @note: __AHBPRESCALER__ be retrieved by @ref LL_RCC_GetAHBPrescaler
<>	154:37f96f9d4de2	741	* ex: __LL_RCC_CALC_HCLK_FREQ(LL_RCC_GetAHBPrescaler())
<>	154:37f96f9d4de2	742	* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
<>	154:37f96f9d4de2	743	* @param __AHBPRESCALER__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	744	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	154:37f96f9d4de2	745	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	154:37f96f9d4de2	746	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	154:37f96f9d4de2	747	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	154:37f96f9d4de2	748	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	154:37f96f9d4de2	749	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	154:37f96f9d4de2	750	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	154:37f96f9d4de2	751	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	154:37f96f9d4de2	752	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	154:37f96f9d4de2	753	* @retval HCLK clock frequency (in Hz)
<>	154:37f96f9d4de2	754	*/
<>	154:37f96f9d4de2	755	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_POSITION_HPRE])
<>	154:37f96f9d4de2	756
<>	154:37f96f9d4de2	757	/**
<>	154:37f96f9d4de2	758	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
<>	154:37f96f9d4de2	759	* @note: __APB1PRESCALER__ be retrieved by @ref LL_RCC_GetAPB1Prescaler
<>	154:37f96f9d4de2	760	* ex: __LL_RCC_CALC_PCLK1_FREQ(LL_RCC_GetAPB1Prescaler())
<>	154:37f96f9d4de2	761	* @param __HCLKFREQ__ HCLK frequency
<>	154:37f96f9d4de2	762	* @param __APB1PRESCALER__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	763	* @arg @ref LL_RCC_APB1_DIV_1
<>	154:37f96f9d4de2	764	* @arg @ref LL_RCC_APB1_DIV_2
<>	154:37f96f9d4de2	765	* @arg @ref LL_RCC_APB1_DIV_4
<>	154:37f96f9d4de2	766	* @arg @ref LL_RCC_APB1_DIV_8
<>	154:37f96f9d4de2	767	* @arg @ref LL_RCC_APB1_DIV_16
<>	154:37f96f9d4de2	768	* @retval PCLK1 clock frequency (in Hz)
<>	154:37f96f9d4de2	769	*/
<>	154:37f96f9d4de2	770	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_POSITION_PPRE1])
<>	154:37f96f9d4de2	771
<>	154:37f96f9d4de2	772	/**
<>	154:37f96f9d4de2	773	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
<>	154:37f96f9d4de2	774	* @note: __APB2PRESCALER__ be retrieved by @ref LL_RCC_GetAPB2Prescaler
<>	154:37f96f9d4de2	775	* ex: __LL_RCC_CALC_PCLK2_FREQ(LL_RCC_GetAPB2Prescaler())
<>	154:37f96f9d4de2	776	* @param __HCLKFREQ__ HCLK frequency
<>	154:37f96f9d4de2	777	* @param __APB2PRESCALER__: This parameter can be one of the following values:
<>	154:37f96f9d4de2	778	* @arg @ref LL_RCC_APB2_DIV_1
<>	154:37f96f9d4de2	779	* @arg @ref LL_RCC_APB2_DIV_2
<>	154:37f96f9d4de2	780	* @arg @ref LL_RCC_APB2_DIV_4
<>	154:37f96f9d4de2	781	* @arg @ref LL_RCC_APB2_DIV_8
<>	154:37f96f9d4de2	782	* @arg @ref LL_RCC_APB2_DIV_16
<>	154:37f96f9d4de2	783	* @retval PCLK2 clock frequency (in Hz)
<>	154:37f96f9d4de2	784	*/
<>	154:37f96f9d4de2	785	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_POSITION_PPRE2])
<>	154:37f96f9d4de2	786
<>	154:37f96f9d4de2	787	/**
<>	154:37f96f9d4de2	788	* @}
<>	154:37f96f9d4de2	789	*/
<>	154:37f96f9d4de2	790
<>	154:37f96f9d4de2	791	/**
<>	154:37f96f9d4de2	792	* @}
<>	154:37f96f9d4de2	793	*/
<>	154:37f96f9d4de2	794
<>	154:37f96f9d4de2	795	/* Exported functions --------------------------------------------------------*/
<>	154:37f96f9d4de2	796	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
<>	154:37f96f9d4de2	797	* @{
<>	154:37f96f9d4de2	798	*/
<>	154:37f96f9d4de2	799
<>	154:37f96f9d4de2	800	/** @defgroup RCC_LL_EF_HSE HSE
<>	154:37f96f9d4de2	801	* @{
<>	154:37f96f9d4de2	802	*/
<>	154:37f96f9d4de2	803
<>	154:37f96f9d4de2	804	/**
<>	154:37f96f9d4de2	805	* @brief Enable the Clock Security System.
<>	154:37f96f9d4de2	806	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
<>	154:37f96f9d4de2	807	* @retval None
<>	154:37f96f9d4de2	808	*/
<>	154:37f96f9d4de2	809	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
<>	154:37f96f9d4de2	810	{
<>	154:37f96f9d4de2	811	SET_BIT(RCC->CR, RCC_CR_CSSON);
<>	154:37f96f9d4de2	812	}
<>	154:37f96f9d4de2	813
<>	154:37f96f9d4de2	814	/**
<>	154:37f96f9d4de2	815	* @brief Enable HSE external oscillator (HSE Bypass)
<>	154:37f96f9d4de2	816	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
<>	154:37f96f9d4de2	817	* @retval None
<>	154:37f96f9d4de2	818	*/
<>	154:37f96f9d4de2	819	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
<>	154:37f96f9d4de2	820	{
<>	154:37f96f9d4de2	821	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	154:37f96f9d4de2	822	}
<>	154:37f96f9d4de2	823
<>	154:37f96f9d4de2	824	/**
<>	154:37f96f9d4de2	825	* @brief Disable HSE external oscillator (HSE Bypass)
<>	154:37f96f9d4de2	826	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
<>	154:37f96f9d4de2	827	* @retval None
<>	154:37f96f9d4de2	828	*/
<>	154:37f96f9d4de2	829	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
<>	154:37f96f9d4de2	830	{
<>	154:37f96f9d4de2	831	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<>	154:37f96f9d4de2	832	}
<>	154:37f96f9d4de2	833
<>	154:37f96f9d4de2	834	/**
<>	154:37f96f9d4de2	835	* @brief Enable HSE crystal oscillator (HSE ON)
<>	154:37f96f9d4de2	836	* @rmtoll CR HSEON LL_RCC_HSE_Enable
<>	154:37f96f9d4de2	837	* @retval None
<>	154:37f96f9d4de2	838	*/
<>	154:37f96f9d4de2	839	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
<>	154:37f96f9d4de2	840	{
<>	154:37f96f9d4de2	841	SET_BIT(RCC->CR, RCC_CR_HSEON);
<>	154:37f96f9d4de2	842	}
<>	154:37f96f9d4de2	843
<>	154:37f96f9d4de2	844	/**
<>	154:37f96f9d4de2	845	* @brief Disable HSE crystal oscillator (HSE ON)
<>	154:37f96f9d4de2	846	* @rmtoll CR HSEON LL_RCC_HSE_Disable
<>	154:37f96f9d4de2	847	* @retval None
<>	154:37f96f9d4de2	848	*/
<>	154:37f96f9d4de2	849	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
<>	154:37f96f9d4de2	850	{
<>	154:37f96f9d4de2	851	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
<>	154:37f96f9d4de2	852	}
<>	154:37f96f9d4de2	853
<>	154:37f96f9d4de2	854	/**
<>	154:37f96f9d4de2	855	* @brief Check if HSE oscillator Ready
<>	154:37f96f9d4de2	856	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
<>	154:37f96f9d4de2	857	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	858	*/
<>	154:37f96f9d4de2	859	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
<>	154:37f96f9d4de2	860	{
<>	154:37f96f9d4de2	861	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
<>	154:37f96f9d4de2	862	}
<>	154:37f96f9d4de2	863
<>	154:37f96f9d4de2	864	#if defined(RCC_PREDIV2_SUPPORT)
<>	154:37f96f9d4de2	865	/**
<>	154:37f96f9d4de2	866	* @brief Get PREDIV2 division factor
<>	154:37f96f9d4de2	867	* @rmtoll CFGR2 PREDIV2 LL_RCC_HSE_GetPrediv2
<>	154:37f96f9d4de2	868	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	869	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<>	154:37f96f9d4de2	870	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<>	154:37f96f9d4de2	871	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<>	154:37f96f9d4de2	872	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<>	154:37f96f9d4de2	873	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<>	154:37f96f9d4de2	874	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<>	154:37f96f9d4de2	875	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<>	154:37f96f9d4de2	876	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<>	154:37f96f9d4de2	877	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<>	154:37f96f9d4de2	878	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<>	154:37f96f9d4de2	879	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<>	154:37f96f9d4de2	880	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<>	154:37f96f9d4de2	881	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<>	154:37f96f9d4de2	882	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<>	154:37f96f9d4de2	883	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<>	154:37f96f9d4de2	884	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<>	154:37f96f9d4de2	885	*/
<>	154:37f96f9d4de2	886	__STATIC_INLINE uint32_t LL_RCC_HSE_GetPrediv2(void)
<>	154:37f96f9d4de2	887	{
<>	154:37f96f9d4de2	888	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2));
<>	154:37f96f9d4de2	889	}
<>	154:37f96f9d4de2	890	#endif /* RCC_PREDIV2_SUPPORT */
<>	154:37f96f9d4de2	891
<>	154:37f96f9d4de2	892	/**
<>	154:37f96f9d4de2	893	* @}
<>	154:37f96f9d4de2	894	*/
<>	154:37f96f9d4de2	895
<>	154:37f96f9d4de2	896	/** @defgroup RCC_LL_EF_HSI HSI
<>	154:37f96f9d4de2	897	* @{
<>	154:37f96f9d4de2	898	*/
<>	154:37f96f9d4de2	899
<>	154:37f96f9d4de2	900	/**
<>	154:37f96f9d4de2	901	* @brief Enable HSI oscillator
<>	154:37f96f9d4de2	902	* @rmtoll CR HSION LL_RCC_HSI_Enable
<>	154:37f96f9d4de2	903	* @retval None
<>	154:37f96f9d4de2	904	*/
<>	154:37f96f9d4de2	905	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
<>	154:37f96f9d4de2	906	{
<>	154:37f96f9d4de2	907	SET_BIT(RCC->CR, RCC_CR_HSION);
<>	154:37f96f9d4de2	908	}
<>	154:37f96f9d4de2	909
<>	154:37f96f9d4de2	910	/**
<>	154:37f96f9d4de2	911	* @brief Disable HSI oscillator
<>	154:37f96f9d4de2	912	* @rmtoll CR HSION LL_RCC_HSI_Disable
<>	154:37f96f9d4de2	913	* @retval None
<>	154:37f96f9d4de2	914	*/
<>	154:37f96f9d4de2	915	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
<>	154:37f96f9d4de2	916	{
<>	154:37f96f9d4de2	917	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
<>	154:37f96f9d4de2	918	}
<>	154:37f96f9d4de2	919
<>	154:37f96f9d4de2	920	/**
<>	154:37f96f9d4de2	921	* @brief Check if HSI clock is ready
<>	154:37f96f9d4de2	922	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
<>	154:37f96f9d4de2	923	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	924	*/
<>	154:37f96f9d4de2	925	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
<>	154:37f96f9d4de2	926	{
<>	154:37f96f9d4de2	927	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
<>	154:37f96f9d4de2	928	}
<>	154:37f96f9d4de2	929
<>	154:37f96f9d4de2	930	/**
<>	154:37f96f9d4de2	931	* @brief Get HSI Calibration value
<>	154:37f96f9d4de2	932	* @note When HSITRIM is written, HSICAL is updated with the sum of
<>	154:37f96f9d4de2	933	* HSITRIM and the factory trim value
<>	154:37f96f9d4de2	934	* @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
<>	154:37f96f9d4de2	935	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
<>	154:37f96f9d4de2	936	*/
<>	154:37f96f9d4de2	937	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
<>	154:37f96f9d4de2	938	{
<>	154:37f96f9d4de2	939	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_POSITION_HSICAL);
<>	154:37f96f9d4de2	940	}
<>	154:37f96f9d4de2	941
<>	154:37f96f9d4de2	942	/**
<>	154:37f96f9d4de2	943	* @brief Set HSI Calibration trimming
<>	154:37f96f9d4de2	944	* @note user-programmable trimming value that is added to the HSICAL
<>	154:37f96f9d4de2	945	* @note Default value is 16, which, when added to the HSICAL value,
<>	154:37f96f9d4de2	946	* should trim the HSI to 16 MHz +/- 1 %
<>	154:37f96f9d4de2	947	* @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
<>	154:37f96f9d4de2	948	* @param Value between Min_Data = 0x00 and Max_Data = 0x1F
<>	154:37f96f9d4de2	949	* @retval None
<>	154:37f96f9d4de2	950	*/
<>	154:37f96f9d4de2	951	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
<>	154:37f96f9d4de2	952	{
<>	154:37f96f9d4de2	953	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_POSITION_HSITRIM);
<>	154:37f96f9d4de2	954	}
<>	154:37f96f9d4de2	955
<>	154:37f96f9d4de2	956	/**
<>	154:37f96f9d4de2	957	* @brief Get HSI Calibration trimming
<>	154:37f96f9d4de2	958	* @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
<>	154:37f96f9d4de2	959	* @retval Between Min_Data = 0x00 and Max_Data = 0x1F
<>	154:37f96f9d4de2	960	*/
<>	154:37f96f9d4de2	961	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
<>	154:37f96f9d4de2	962	{
<>	154:37f96f9d4de2	963	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_POSITION_HSITRIM);
<>	154:37f96f9d4de2	964	}
<>	154:37f96f9d4de2	965
<>	154:37f96f9d4de2	966	/**
<>	154:37f96f9d4de2	967	* @}
<>	154:37f96f9d4de2	968	*/
<>	154:37f96f9d4de2	969
<>	154:37f96f9d4de2	970	/** @defgroup RCC_LL_EF_LSE LSE
<>	154:37f96f9d4de2	971	* @{
<>	154:37f96f9d4de2	972	*/
<>	154:37f96f9d4de2	973
<>	154:37f96f9d4de2	974	/**
<>	154:37f96f9d4de2	975	* @brief Enable Low Speed External (LSE) crystal.
<>	154:37f96f9d4de2	976	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
<>	154:37f96f9d4de2	977	* @retval None
<>	154:37f96f9d4de2	978	*/
<>	154:37f96f9d4de2	979	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
<>	154:37f96f9d4de2	980	{
<>	154:37f96f9d4de2	981	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<>	154:37f96f9d4de2	982	}
<>	154:37f96f9d4de2	983
<>	154:37f96f9d4de2	984	/**
<>	154:37f96f9d4de2	985	* @brief Disable Low Speed External (LSE) crystal.
<>	154:37f96f9d4de2	986	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
<>	154:37f96f9d4de2	987	* @retval None
<>	154:37f96f9d4de2	988	*/
<>	154:37f96f9d4de2	989	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
<>	154:37f96f9d4de2	990	{
<>	154:37f96f9d4de2	991	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
<>	154:37f96f9d4de2	992	}
<>	154:37f96f9d4de2	993
<>	154:37f96f9d4de2	994	/**
<>	154:37f96f9d4de2	995	* @brief Enable external clock source (LSE bypass).
<>	154:37f96f9d4de2	996	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
<>	154:37f96f9d4de2	997	* @retval None
<>	154:37f96f9d4de2	998	*/
<>	154:37f96f9d4de2	999	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
<>	154:37f96f9d4de2	1000	{
<>	154:37f96f9d4de2	1001	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<>	154:37f96f9d4de2	1002	}
<>	154:37f96f9d4de2	1003
<>	154:37f96f9d4de2	1004	/**
<>	154:37f96f9d4de2	1005	* @brief Disable external clock source (LSE bypass).
<>	154:37f96f9d4de2	1006	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
<>	154:37f96f9d4de2	1007	* @retval None
<>	154:37f96f9d4de2	1008	*/
<>	154:37f96f9d4de2	1009	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
<>	154:37f96f9d4de2	1010	{
<>	154:37f96f9d4de2	1011	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
<>	154:37f96f9d4de2	1012	}
<>	154:37f96f9d4de2	1013
<>	154:37f96f9d4de2	1014	/**
<>	154:37f96f9d4de2	1015	* @brief Check if LSE oscillator Ready
<>	154:37f96f9d4de2	1016	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
<>	154:37f96f9d4de2	1017	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1018	*/
<>	154:37f96f9d4de2	1019	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
<>	154:37f96f9d4de2	1020	{
<>	154:37f96f9d4de2	1021	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
<>	154:37f96f9d4de2	1022	}
<>	154:37f96f9d4de2	1023
<>	154:37f96f9d4de2	1024	/**
<>	154:37f96f9d4de2	1025	* @}
<>	154:37f96f9d4de2	1026	*/
<>	154:37f96f9d4de2	1027
<>	154:37f96f9d4de2	1028	/** @defgroup RCC_LL_EF_LSI LSI
<>	154:37f96f9d4de2	1029	* @{
<>	154:37f96f9d4de2	1030	*/
<>	154:37f96f9d4de2	1031
<>	154:37f96f9d4de2	1032	/**
<>	154:37f96f9d4de2	1033	* @brief Enable LSI Oscillator
<>	154:37f96f9d4de2	1034	* @rmtoll CSR LSION LL_RCC_LSI_Enable
<>	154:37f96f9d4de2	1035	* @retval None
<>	154:37f96f9d4de2	1036	*/
<>	154:37f96f9d4de2	1037	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
<>	154:37f96f9d4de2	1038	{
<>	154:37f96f9d4de2	1039	SET_BIT(RCC->CSR, RCC_CSR_LSION);
<>	154:37f96f9d4de2	1040	}
<>	154:37f96f9d4de2	1041
<>	154:37f96f9d4de2	1042	/**
<>	154:37f96f9d4de2	1043	* @brief Disable LSI Oscillator
<>	154:37f96f9d4de2	1044	* @rmtoll CSR LSION LL_RCC_LSI_Disable
<>	154:37f96f9d4de2	1045	* @retval None
<>	154:37f96f9d4de2	1046	*/
<>	154:37f96f9d4de2	1047	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
<>	154:37f96f9d4de2	1048	{
<>	154:37f96f9d4de2	1049	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
<>	154:37f96f9d4de2	1050	}
<>	154:37f96f9d4de2	1051
<>	154:37f96f9d4de2	1052	/**
<>	154:37f96f9d4de2	1053	* @brief Check if LSI is Ready
<>	154:37f96f9d4de2	1054	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
<>	154:37f96f9d4de2	1055	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1056	*/
<>	154:37f96f9d4de2	1057	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
<>	154:37f96f9d4de2	1058	{
<>	154:37f96f9d4de2	1059	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
<>	154:37f96f9d4de2	1060	}
<>	154:37f96f9d4de2	1061
<>	154:37f96f9d4de2	1062	/**
<>	154:37f96f9d4de2	1063	* @}
<>	154:37f96f9d4de2	1064	*/
<>	154:37f96f9d4de2	1065
<>	154:37f96f9d4de2	1066	/** @defgroup RCC_LL_EF_System System
<>	154:37f96f9d4de2	1067	* @{
<>	154:37f96f9d4de2	1068	*/
<>	154:37f96f9d4de2	1069
<>	154:37f96f9d4de2	1070	/**
<>	154:37f96f9d4de2	1071	* @brief Configure the system clock source
<>	154:37f96f9d4de2	1072	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
<>	154:37f96f9d4de2	1073	* @param Source This parameter can be one of the following values:
<>	154:37f96f9d4de2	1074	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
<>	154:37f96f9d4de2	1075	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
<>	154:37f96f9d4de2	1076	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
<>	154:37f96f9d4de2	1077	* @retval None
<>	154:37f96f9d4de2	1078	*/
<>	154:37f96f9d4de2	1079	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
<>	154:37f96f9d4de2	1080	{
<>	154:37f96f9d4de2	1081	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
<>	154:37f96f9d4de2	1082	}
<>	154:37f96f9d4de2	1083
<>	154:37f96f9d4de2	1084	/**
<>	154:37f96f9d4de2	1085	* @brief Get the system clock source
<>	154:37f96f9d4de2	1086	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
<>	154:37f96f9d4de2	1087	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1088	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
<>	154:37f96f9d4de2	1089	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
<>	154:37f96f9d4de2	1090	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
<>	154:37f96f9d4de2	1091	*/
<>	154:37f96f9d4de2	1092	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
<>	154:37f96f9d4de2	1093	{
<>	154:37f96f9d4de2	1094	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
<>	154:37f96f9d4de2	1095	}
<>	154:37f96f9d4de2	1096
<>	154:37f96f9d4de2	1097	/**
<>	154:37f96f9d4de2	1098	* @brief Set AHB prescaler
<>	154:37f96f9d4de2	1099	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
<>	154:37f96f9d4de2	1100	* @param Prescaler This parameter can be one of the following values:
<>	154:37f96f9d4de2	1101	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	154:37f96f9d4de2	1102	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	154:37f96f9d4de2	1103	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	154:37f96f9d4de2	1104	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	154:37f96f9d4de2	1105	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	154:37f96f9d4de2	1106	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	154:37f96f9d4de2	1107	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	154:37f96f9d4de2	1108	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	154:37f96f9d4de2	1109	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	154:37f96f9d4de2	1110	* @retval None
<>	154:37f96f9d4de2	1111	*/
<>	154:37f96f9d4de2	1112	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
<>	154:37f96f9d4de2	1113	{
<>	154:37f96f9d4de2	1114	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
<>	154:37f96f9d4de2	1115	}
<>	154:37f96f9d4de2	1116
<>	154:37f96f9d4de2	1117	/**
<>	154:37f96f9d4de2	1118	* @brief Set APB1 prescaler
<>	154:37f96f9d4de2	1119	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
<>	154:37f96f9d4de2	1120	* @param Prescaler This parameter can be one of the following values:
<>	154:37f96f9d4de2	1121	* @arg @ref LL_RCC_APB1_DIV_1
<>	154:37f96f9d4de2	1122	* @arg @ref LL_RCC_APB1_DIV_2
<>	154:37f96f9d4de2	1123	* @arg @ref LL_RCC_APB1_DIV_4
<>	154:37f96f9d4de2	1124	* @arg @ref LL_RCC_APB1_DIV_8
<>	154:37f96f9d4de2	1125	* @arg @ref LL_RCC_APB1_DIV_16
<>	154:37f96f9d4de2	1126	* @retval None
<>	154:37f96f9d4de2	1127	*/
<>	154:37f96f9d4de2	1128	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
<>	154:37f96f9d4de2	1129	{
<>	154:37f96f9d4de2	1130	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
<>	154:37f96f9d4de2	1131	}
<>	154:37f96f9d4de2	1132
<>	154:37f96f9d4de2	1133	/**
<>	154:37f96f9d4de2	1134	* @brief Set APB2 prescaler
<>	154:37f96f9d4de2	1135	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
<>	154:37f96f9d4de2	1136	* @param Prescaler This parameter can be one of the following values:
<>	154:37f96f9d4de2	1137	* @arg @ref LL_RCC_APB2_DIV_1
<>	154:37f96f9d4de2	1138	* @arg @ref LL_RCC_APB2_DIV_2
<>	154:37f96f9d4de2	1139	* @arg @ref LL_RCC_APB2_DIV_4
<>	154:37f96f9d4de2	1140	* @arg @ref LL_RCC_APB2_DIV_8
<>	154:37f96f9d4de2	1141	* @arg @ref LL_RCC_APB2_DIV_16
<>	154:37f96f9d4de2	1142	* @retval None
<>	154:37f96f9d4de2	1143	*/
<>	154:37f96f9d4de2	1144	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
<>	154:37f96f9d4de2	1145	{
<>	154:37f96f9d4de2	1146	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
<>	154:37f96f9d4de2	1147	}
<>	154:37f96f9d4de2	1148
<>	154:37f96f9d4de2	1149	/**
<>	154:37f96f9d4de2	1150	* @brief Get AHB prescaler
<>	154:37f96f9d4de2	1151	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
<>	154:37f96f9d4de2	1152	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1153	* @arg @ref LL_RCC_SYSCLK_DIV_1
<>	154:37f96f9d4de2	1154	* @arg @ref LL_RCC_SYSCLK_DIV_2
<>	154:37f96f9d4de2	1155	* @arg @ref LL_RCC_SYSCLK_DIV_4
<>	154:37f96f9d4de2	1156	* @arg @ref LL_RCC_SYSCLK_DIV_8
<>	154:37f96f9d4de2	1157	* @arg @ref LL_RCC_SYSCLK_DIV_16
<>	154:37f96f9d4de2	1158	* @arg @ref LL_RCC_SYSCLK_DIV_64
<>	154:37f96f9d4de2	1159	* @arg @ref LL_RCC_SYSCLK_DIV_128
<>	154:37f96f9d4de2	1160	* @arg @ref LL_RCC_SYSCLK_DIV_256
<>	154:37f96f9d4de2	1161	* @arg @ref LL_RCC_SYSCLK_DIV_512
<>	154:37f96f9d4de2	1162	*/
<>	154:37f96f9d4de2	1163	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
<>	154:37f96f9d4de2	1164	{
<>	154:37f96f9d4de2	1165	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
<>	154:37f96f9d4de2	1166	}
<>	154:37f96f9d4de2	1167
<>	154:37f96f9d4de2	1168	/**
<>	154:37f96f9d4de2	1169	* @brief Get APB1 prescaler
<>	154:37f96f9d4de2	1170	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
<>	154:37f96f9d4de2	1171	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1172	* @arg @ref LL_RCC_APB1_DIV_1
<>	154:37f96f9d4de2	1173	* @arg @ref LL_RCC_APB1_DIV_2
<>	154:37f96f9d4de2	1174	* @arg @ref LL_RCC_APB1_DIV_4
<>	154:37f96f9d4de2	1175	* @arg @ref LL_RCC_APB1_DIV_8
<>	154:37f96f9d4de2	1176	* @arg @ref LL_RCC_APB1_DIV_16
<>	154:37f96f9d4de2	1177	*/
<>	154:37f96f9d4de2	1178	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
<>	154:37f96f9d4de2	1179	{
<>	154:37f96f9d4de2	1180	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
<>	154:37f96f9d4de2	1181	}
<>	154:37f96f9d4de2	1182
<>	154:37f96f9d4de2	1183	/**
<>	154:37f96f9d4de2	1184	* @brief Get APB2 prescaler
<>	154:37f96f9d4de2	1185	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
<>	154:37f96f9d4de2	1186	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1187	* @arg @ref LL_RCC_APB2_DIV_1
<>	154:37f96f9d4de2	1188	* @arg @ref LL_RCC_APB2_DIV_2
<>	154:37f96f9d4de2	1189	* @arg @ref LL_RCC_APB2_DIV_4
<>	154:37f96f9d4de2	1190	* @arg @ref LL_RCC_APB2_DIV_8
<>	154:37f96f9d4de2	1191	* @arg @ref LL_RCC_APB2_DIV_16
<>	154:37f96f9d4de2	1192	*/
<>	154:37f96f9d4de2	1193	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
<>	154:37f96f9d4de2	1194	{
<>	154:37f96f9d4de2	1195	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
<>	154:37f96f9d4de2	1196	}
<>	154:37f96f9d4de2	1197
<>	154:37f96f9d4de2	1198	/**
<>	154:37f96f9d4de2	1199	* @}
<>	154:37f96f9d4de2	1200	*/
<>	154:37f96f9d4de2	1201
<>	154:37f96f9d4de2	1202	/** @defgroup RCC_LL_EF_MCO MCO
<>	154:37f96f9d4de2	1203	* @{
<>	154:37f96f9d4de2	1204	*/
<>	154:37f96f9d4de2	1205
<>	154:37f96f9d4de2	1206	/**
<>	154:37f96f9d4de2	1207	* @brief Configure MCOx
<>	154:37f96f9d4de2	1208	* @rmtoll CFGR MCO LL_RCC_ConfigMCO
<>	154:37f96f9d4de2	1209	* @param MCOxSource This parameter can be one of the following values:
<>	154:37f96f9d4de2	1210	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
<>	154:37f96f9d4de2	1211	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
<>	154:37f96f9d4de2	1212	* @arg @ref LL_RCC_MCO1SOURCE_HSI
<>	154:37f96f9d4de2	1213	* @arg @ref LL_RCC_MCO1SOURCE_HSE
<>	154:37f96f9d4de2	1214	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK_DIV_2
<>	154:37f96f9d4de2	1215	* @arg @ref LL_RCC_MCO1SOURCE_PLL2CLK (*)
<>	154:37f96f9d4de2	1216	* @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 (*)
<>	154:37f96f9d4de2	1217	* @arg @ref LL_RCC_MCO1SOURCE_EXT_HSE (*)
<>	154:37f96f9d4de2	1218	* @arg @ref LL_RCC_MCO1SOURCE_PLLI2SCLK (*)
<>	154:37f96f9d4de2	1219	*
<>	154:37f96f9d4de2	1220	* (*) value not defined in all devices
<>	154:37f96f9d4de2	1221	* @retval None
<>	154:37f96f9d4de2	1222	*/
<>	154:37f96f9d4de2	1223	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource)
<>	154:37f96f9d4de2	1224	{
<>	154:37f96f9d4de2	1225	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL, MCOxSource);
<>	154:37f96f9d4de2	1226	}
<>	154:37f96f9d4de2	1227
<>	154:37f96f9d4de2	1228	/**
<>	154:37f96f9d4de2	1229	* @}
<>	154:37f96f9d4de2	1230	*/
<>	154:37f96f9d4de2	1231
<>	154:37f96f9d4de2	1232	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
<>	154:37f96f9d4de2	1233	* @{
<>	154:37f96f9d4de2	1234	*/
<>	154:37f96f9d4de2	1235
<>	154:37f96f9d4de2	1236	#if defined(RCC_CFGR2_I2S2SRC)
<>	154:37f96f9d4de2	1237	/**
<>	154:37f96f9d4de2	1238	* @brief Configure I2Sx clock source
<>	154:37f96f9d4de2	1239	* @rmtoll CFGR2 I2S2SRC LL_RCC_SetI2SClockSource\n
<>	154:37f96f9d4de2	1240	* CFGR2 I2S3SRC LL_RCC_SetI2SClockSource
<>	154:37f96f9d4de2	1241	* @param I2SxSource This parameter can be one of the following values:
<>	154:37f96f9d4de2	1242	* @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
<>	154:37f96f9d4de2	1243	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
<>	154:37f96f9d4de2	1244	* @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
<>	154:37f96f9d4de2	1245	* @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
<>	154:37f96f9d4de2	1246	* @retval None
<>	154:37f96f9d4de2	1247	*/
<>	154:37f96f9d4de2	1248	__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
<>	154:37f96f9d4de2	1249	{
<>	154:37f96f9d4de2	1250	MODIFY_REG(RCC->CFGR2, (I2SxSource & 0xFFFF0000U), (I2SxSource << 16U));
<>	154:37f96f9d4de2	1251	}
<>	154:37f96f9d4de2	1252	#endif /* RCC_CFGR2_I2S2SRC */
<>	154:37f96f9d4de2	1253
<>	154:37f96f9d4de2	1254	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	154:37f96f9d4de2	1255	/**
<>	154:37f96f9d4de2	1256	* @brief Configure USB clock source
<>	154:37f96f9d4de2	1257	* @rmtoll CFGR OTGFSPRE LL_RCC_SetUSBClockSource\n
<>	154:37f96f9d4de2	1258	* CFGR USBPRE LL_RCC_SetUSBClockSource
<>	154:37f96f9d4de2	1259	* @param USBxSource This parameter can be one of the following values:
<>	154:37f96f9d4de2	1260	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
<>	154:37f96f9d4de2	1261	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
<>	154:37f96f9d4de2	1262	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
<>	154:37f96f9d4de2	1263	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
<>	154:37f96f9d4de2	1264	*
<>	154:37f96f9d4de2	1265	* (*) value not defined in all devices
<>	154:37f96f9d4de2	1266	* @retval None
<>	154:37f96f9d4de2	1267	*/
<>	154:37f96f9d4de2	1268	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
<>	154:37f96f9d4de2	1269	{
<>	154:37f96f9d4de2	1270	#if defined(RCC_CFGR_USBPRE)
<>	154:37f96f9d4de2	1271	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, USBxSource);
<>	154:37f96f9d4de2	1272	#else /RCC_CFGR_OTGFSPRE/
<>	154:37f96f9d4de2	1273	MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, USBxSource);
<>	154:37f96f9d4de2	1274	#endif /RCC_CFGR_USBPRE/
<>	154:37f96f9d4de2	1275	}
<>	154:37f96f9d4de2	1276	#endif /* USB_OTG_FS \|\| USB */
<>	154:37f96f9d4de2	1277
<>	154:37f96f9d4de2	1278	/**
<>	154:37f96f9d4de2	1279	* @brief Configure ADC clock source
<>	154:37f96f9d4de2	1280	* @rmtoll CFGR ADCPRE LL_RCC_SetADCClockSource
<>	154:37f96f9d4de2	1281	* @param ADCxSource This parameter can be one of the following values:
<>	154:37f96f9d4de2	1282	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
<>	154:37f96f9d4de2	1283	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
<>	154:37f96f9d4de2	1284	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
<>	154:37f96f9d4de2	1285	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
<>	154:37f96f9d4de2	1286	* @retval None
<>	154:37f96f9d4de2	1287	*/
<>	154:37f96f9d4de2	1288	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
<>	154:37f96f9d4de2	1289	{
<>	154:37f96f9d4de2	1290	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, ADCxSource);
<>	154:37f96f9d4de2	1291	}
<>	154:37f96f9d4de2	1292
<>	154:37f96f9d4de2	1293	#if defined(RCC_CFGR2_I2S2SRC)
<>	154:37f96f9d4de2	1294	/**
<>	154:37f96f9d4de2	1295	* @brief Get I2Sx clock source
<>	154:37f96f9d4de2	1296	* @rmtoll CFGR2 I2S2SRC LL_RCC_GetI2SClockSource\n
<>	154:37f96f9d4de2	1297	* CFGR2 I2S3SRC LL_RCC_GetI2SClockSource
<>	154:37f96f9d4de2	1298	* @param I2Sx This parameter can be one of the following values:
<>	154:37f96f9d4de2	1299	* @arg @ref LL_RCC_I2S2_CLKSOURCE
<>	154:37f96f9d4de2	1300	* @arg @ref LL_RCC_I2S3_CLKSOURCE
<>	154:37f96f9d4de2	1301	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1302	* @arg @ref LL_RCC_I2S2_CLKSOURCE_SYSCLK
<>	154:37f96f9d4de2	1303	* @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S_VCO
<>	154:37f96f9d4de2	1304	* @arg @ref LL_RCC_I2S3_CLKSOURCE_SYSCLK
<>	154:37f96f9d4de2	1305	* @arg @ref LL_RCC_I2S3_CLKSOURCE_PLLI2S_VCO
<>	154:37f96f9d4de2	1306	*/
<>	154:37f96f9d4de2	1307	__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
<>	154:37f96f9d4de2	1308	{
<>	154:37f96f9d4de2	1309	return (uint32_t)(READ_BIT(RCC->CFGR2, I2Sx) >> 16 \| I2Sx);
<>	154:37f96f9d4de2	1310	}
<>	154:37f96f9d4de2	1311	#endif /* RCC_CFGR2_I2S2SRC */
<>	154:37f96f9d4de2	1312
<>	154:37f96f9d4de2	1313	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	154:37f96f9d4de2	1314	/**
<>	154:37f96f9d4de2	1315	* @brief Get USBx clock source
<>	154:37f96f9d4de2	1316	* @rmtoll CFGR OTGFSPRE LL_RCC_GetUSBClockSource\n
<>	154:37f96f9d4de2	1317	* CFGR USBPRE LL_RCC_GetUSBClockSource
<>	154:37f96f9d4de2	1318	* @param USBx This parameter can be one of the following values:
<>	154:37f96f9d4de2	1319	* @arg @ref LL_RCC_USB_CLKSOURCE
<>	154:37f96f9d4de2	1320	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1321	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL (*)
<>	154:37f96f9d4de2	1322	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 (*)
<>	154:37f96f9d4de2	1323	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_2 (*)
<>	154:37f96f9d4de2	1324	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL_DIV_3 (*)
<>	154:37f96f9d4de2	1325	*
<>	154:37f96f9d4de2	1326	* (*) value not defined in all devices
<>	154:37f96f9d4de2	1327	*/
<>	154:37f96f9d4de2	1328	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
<>	154:37f96f9d4de2	1329	{
<>	154:37f96f9d4de2	1330	return (uint32_t)(READ_BIT(RCC->CFGR, USBx));
<>	154:37f96f9d4de2	1331	}
<>	154:37f96f9d4de2	1332	#endif /* USB_OTG_FS \|\| USB */
<>	154:37f96f9d4de2	1333
<>	154:37f96f9d4de2	1334	/**
<>	154:37f96f9d4de2	1335	* @brief Get ADCx clock source
<>	154:37f96f9d4de2	1336	* @rmtoll CFGR ADCPRE LL_RCC_GetADCClockSource
<>	154:37f96f9d4de2	1337	* @param ADCx This parameter can be one of the following values:
<>	154:37f96f9d4de2	1338	* @arg @ref LL_RCC_ADC_CLKSOURCE
<>	154:37f96f9d4de2	1339	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1340	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_2
<>	154:37f96f9d4de2	1341	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_4
<>	154:37f96f9d4de2	1342	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_6
<>	154:37f96f9d4de2	1343	* @arg @ref LL_RCC_ADC_CLKSRC_PCLK2_DIV_8
<>	154:37f96f9d4de2	1344	*/
<>	154:37f96f9d4de2	1345	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
<>	154:37f96f9d4de2	1346	{
<>	154:37f96f9d4de2	1347	return (uint32_t)(READ_BIT(RCC->CFGR, ADCx));
<>	154:37f96f9d4de2	1348	}
<>	154:37f96f9d4de2	1349
<>	154:37f96f9d4de2	1350	/**
<>	154:37f96f9d4de2	1351	* @}
<>	154:37f96f9d4de2	1352	*/
<>	154:37f96f9d4de2	1353
<>	154:37f96f9d4de2	1354	/** @defgroup RCC_LL_EF_RTC RTC
<>	154:37f96f9d4de2	1355	* @{
<>	154:37f96f9d4de2	1356	*/
<>	154:37f96f9d4de2	1357
<>	154:37f96f9d4de2	1358	/**
<>	154:37f96f9d4de2	1359	* @brief Set RTC Clock Source
<>	154:37f96f9d4de2	1360	* @note Once the RTC clock source has been selected, it cannot be changed any more unless
<>	154:37f96f9d4de2	1361	* the Backup domain is reset. The BDRST bit can be used to reset them.
<>	154:37f96f9d4de2	1362	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
<>	154:37f96f9d4de2	1363	* @param Source This parameter can be one of the following values:
<>	154:37f96f9d4de2	1364	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	154:37f96f9d4de2	1365	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	154:37f96f9d4de2	1366	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	154:37f96f9d4de2	1367	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
<>	154:37f96f9d4de2	1368	* @retval None
<>	154:37f96f9d4de2	1369	*/
<>	154:37f96f9d4de2	1370	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
<>	154:37f96f9d4de2	1371	{
<>	154:37f96f9d4de2	1372	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
<>	154:37f96f9d4de2	1373	}
<>	154:37f96f9d4de2	1374
<>	154:37f96f9d4de2	1375	/**
<>	154:37f96f9d4de2	1376	* @brief Get RTC Clock Source
<>	154:37f96f9d4de2	1377	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
<>	154:37f96f9d4de2	1378	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1379	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
<>	154:37f96f9d4de2	1380	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
<>	154:37f96f9d4de2	1381	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
<>	154:37f96f9d4de2	1382	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128
<>	154:37f96f9d4de2	1383	*/
<>	154:37f96f9d4de2	1384	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
<>	154:37f96f9d4de2	1385	{
<>	154:37f96f9d4de2	1386	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
<>	154:37f96f9d4de2	1387	}
<>	154:37f96f9d4de2	1388
<>	154:37f96f9d4de2	1389	/**
<>	154:37f96f9d4de2	1390	* @brief Enable RTC
<>	154:37f96f9d4de2	1391	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
<>	154:37f96f9d4de2	1392	* @retval None
<>	154:37f96f9d4de2	1393	*/
<>	154:37f96f9d4de2	1394	__STATIC_INLINE void LL_RCC_EnableRTC(void)
<>	154:37f96f9d4de2	1395	{
<>	154:37f96f9d4de2	1396	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<>	154:37f96f9d4de2	1397	}
<>	154:37f96f9d4de2	1398
<>	154:37f96f9d4de2	1399	/**
<>	154:37f96f9d4de2	1400	* @brief Disable RTC
<>	154:37f96f9d4de2	1401	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
<>	154:37f96f9d4de2	1402	* @retval None
<>	154:37f96f9d4de2	1403	*/
<>	154:37f96f9d4de2	1404	__STATIC_INLINE void LL_RCC_DisableRTC(void)
<>	154:37f96f9d4de2	1405	{
<>	154:37f96f9d4de2	1406	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
<>	154:37f96f9d4de2	1407	}
<>	154:37f96f9d4de2	1408
<>	154:37f96f9d4de2	1409	/**
<>	154:37f96f9d4de2	1410	* @brief Check if RTC has been enabled or not
<>	154:37f96f9d4de2	1411	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
<>	154:37f96f9d4de2	1412	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1413	*/
<>	154:37f96f9d4de2	1414	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
<>	154:37f96f9d4de2	1415	{
<>	154:37f96f9d4de2	1416	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
<>	154:37f96f9d4de2	1417	}
<>	154:37f96f9d4de2	1418
<>	154:37f96f9d4de2	1419	/**
<>	154:37f96f9d4de2	1420	* @brief Force the Backup domain reset
<>	154:37f96f9d4de2	1421	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
<>	154:37f96f9d4de2	1422	* @retval None
<>	154:37f96f9d4de2	1423	*/
<>	154:37f96f9d4de2	1424	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
<>	154:37f96f9d4de2	1425	{
<>	154:37f96f9d4de2	1426	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<>	154:37f96f9d4de2	1427	}
<>	154:37f96f9d4de2	1428
<>	154:37f96f9d4de2	1429	/**
<>	154:37f96f9d4de2	1430	* @brief Release the Backup domain reset
<>	154:37f96f9d4de2	1431	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
<>	154:37f96f9d4de2	1432	* @retval None
<>	154:37f96f9d4de2	1433	*/
<>	154:37f96f9d4de2	1434	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
<>	154:37f96f9d4de2	1435	{
<>	154:37f96f9d4de2	1436	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
<>	154:37f96f9d4de2	1437	}
<>	154:37f96f9d4de2	1438
<>	154:37f96f9d4de2	1439	/**
<>	154:37f96f9d4de2	1440	* @}
<>	154:37f96f9d4de2	1441	*/
<>	154:37f96f9d4de2	1442
<>	154:37f96f9d4de2	1443	/** @defgroup RCC_LL_EF_PLL PLL
<>	154:37f96f9d4de2	1444	* @{
<>	154:37f96f9d4de2	1445	*/
<>	154:37f96f9d4de2	1446
<>	154:37f96f9d4de2	1447	/**
<>	154:37f96f9d4de2	1448	* @brief Enable PLL
<>	154:37f96f9d4de2	1449	* @rmtoll CR PLLON LL_RCC_PLL_Enable
<>	154:37f96f9d4de2	1450	* @retval None
<>	154:37f96f9d4de2	1451	*/
<>	154:37f96f9d4de2	1452	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
<>	154:37f96f9d4de2	1453	{
<>	154:37f96f9d4de2	1454	SET_BIT(RCC->CR, RCC_CR_PLLON);
<>	154:37f96f9d4de2	1455	}
<>	154:37f96f9d4de2	1456
<>	154:37f96f9d4de2	1457	/**
<>	154:37f96f9d4de2	1458	* @brief Disable PLL
<>	154:37f96f9d4de2	1459	* @note Cannot be disabled if the PLL clock is used as the system clock
<>	154:37f96f9d4de2	1460	* @rmtoll CR PLLON LL_RCC_PLL_Disable
<>	154:37f96f9d4de2	1461	* @retval None
<>	154:37f96f9d4de2	1462	*/
<>	154:37f96f9d4de2	1463	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
<>	154:37f96f9d4de2	1464	{
<>	154:37f96f9d4de2	1465	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
<>	154:37f96f9d4de2	1466	}
<>	154:37f96f9d4de2	1467
<>	154:37f96f9d4de2	1468	/**
<>	154:37f96f9d4de2	1469	* @brief Check if PLL Ready
<>	154:37f96f9d4de2	1470	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
<>	154:37f96f9d4de2	1471	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1472	*/
<>	154:37f96f9d4de2	1473	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
<>	154:37f96f9d4de2	1474	{
<>	154:37f96f9d4de2	1475	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
<>	154:37f96f9d4de2	1476	}
<>	154:37f96f9d4de2	1477
<>	154:37f96f9d4de2	1478	/**
<>	154:37f96f9d4de2	1479	* @brief Configure PLL used for SYSCLK Domain
<>	154:37f96f9d4de2	1480	* @rmtoll CFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
<>	154:37f96f9d4de2	1481	* CFGR PLLXTPRE LL_RCC_PLL_ConfigDomain_SYS\n
<>	154:37f96f9d4de2	1482	* CFGR PLLMULL LL_RCC_PLL_ConfigDomain_SYS\n
<>	154:37f96f9d4de2	1483	* CFGR2 PREDIV1 LL_RCC_PLL_ConfigDomain_SYS\n
<>	154:37f96f9d4de2	1484	* CFGR2 PREDIV1SRC LL_RCC_PLL_ConfigDomain_SYS
<>	154:37f96f9d4de2	1485	* @param Source This parameter can be one of the following values:
<>	154:37f96f9d4de2	1486	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
<>	154:37f96f9d4de2	1487	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_1
<>	154:37f96f9d4de2	1488	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_2 (*)
<>	154:37f96f9d4de2	1489	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_3 (*)
<>	154:37f96f9d4de2	1490	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_4 (*)
<>	154:37f96f9d4de2	1491	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_5 (*)
<>	154:37f96f9d4de2	1492	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_6 (*)
<>	154:37f96f9d4de2	1493	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_7 (*)
<>	154:37f96f9d4de2	1494	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_8 (*)
<>	154:37f96f9d4de2	1495	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_9 (*)
<>	154:37f96f9d4de2	1496	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_10 (*)
<>	154:37f96f9d4de2	1497	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_11 (*)
<>	154:37f96f9d4de2	1498	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_12 (*)
<>	154:37f96f9d4de2	1499	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_13 (*)
<>	154:37f96f9d4de2	1500	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_14 (*)
<>	154:37f96f9d4de2	1501	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_15 (*)
<>	154:37f96f9d4de2	1502	* @arg @ref LL_RCC_PLLSOURCE_HSE_DIV_16 (*)
<>	154:37f96f9d4de2	1503	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_2 (*)
<>	154:37f96f9d4de2	1504	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_3 (*)
<>	154:37f96f9d4de2	1505	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_4 (*)
<>	154:37f96f9d4de2	1506	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_5 (*)
<>	154:37f96f9d4de2	1507	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_6 (*)
<>	154:37f96f9d4de2	1508	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_7 (*)
<>	154:37f96f9d4de2	1509	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_8 (*)
<>	154:37f96f9d4de2	1510	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_9 (*)
<>	154:37f96f9d4de2	1511	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_10 (*)
<>	154:37f96f9d4de2	1512	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_11 (*)
<>	154:37f96f9d4de2	1513	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_12 (*)
<>	154:37f96f9d4de2	1514	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_13 (*)
<>	154:37f96f9d4de2	1515	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_14 (*)
<>	154:37f96f9d4de2	1516	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_15 (*)
<>	154:37f96f9d4de2	1517	* @arg @ref LL_RCC_PLLSOURCE_PLL2_DIV_16 (*)
<>	154:37f96f9d4de2	1518	*
<>	154:37f96f9d4de2	1519	* (*) value not defined in all devices
<>	154:37f96f9d4de2	1520	* @param PLLMul This parameter can be one of the following values:
<>	154:37f96f9d4de2	1521	* @arg @ref LL_RCC_PLL_MUL_2 (*)
<>	154:37f96f9d4de2	1522	* @arg @ref LL_RCC_PLL_MUL_3 (*)
<>	154:37f96f9d4de2	1523	* @arg @ref LL_RCC_PLL_MUL_4
<>	154:37f96f9d4de2	1524	* @arg @ref LL_RCC_PLL_MUL_5
<>	154:37f96f9d4de2	1525	* @arg @ref LL_RCC_PLL_MUL_6
<>	154:37f96f9d4de2	1526	* @arg @ref LL_RCC_PLL_MUL_7
<>	154:37f96f9d4de2	1527	* @arg @ref LL_RCC_PLL_MUL_8
<>	154:37f96f9d4de2	1528	* @arg @ref LL_RCC_PLL_MUL_9
<>	154:37f96f9d4de2	1529	* @arg @ref LL_RCC_PLL_MUL_6_5 (*)
<>	154:37f96f9d4de2	1530	* @arg @ref LL_RCC_PLL_MUL_10 (*)
<>	154:37f96f9d4de2	1531	* @arg @ref LL_RCC_PLL_MUL_11 (*)
<>	154:37f96f9d4de2	1532	* @arg @ref LL_RCC_PLL_MUL_12 (*)
<>	154:37f96f9d4de2	1533	* @arg @ref LL_RCC_PLL_MUL_13 (*)
<>	154:37f96f9d4de2	1534	* @arg @ref LL_RCC_PLL_MUL_14 (*)
<>	154:37f96f9d4de2	1535	* @arg @ref LL_RCC_PLL_MUL_15 (*)
<>	154:37f96f9d4de2	1536	* @arg @ref LL_RCC_PLL_MUL_16 (*)
<>	154:37f96f9d4de2	1537	*
<>	154:37f96f9d4de2	1538	* (*) value not defined in all devices
<>	154:37f96f9d4de2	1539	* @retval None
<>	154:37f96f9d4de2	1540	*/
<>	154:37f96f9d4de2	1541	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLMul)
<>	154:37f96f9d4de2	1542	{
<>	154:37f96f9d4de2	1543	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE \| RCC_CFGR_PLLMULL,
<>	154:37f96f9d4de2	1544	(Source & (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLXTPRE)) \| PLLMul);
<>	154:37f96f9d4de2	1545	#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT)
<>	154:37f96f9d4de2	1546	#if defined(RCC_SRC_PREDIV1_SUPPORT)
<>	154:37f96f9d4de2	1547	MODIFY_REG(RCC->CFGR2, (RCC_CFGR2_PREDIV1 \| RCC_CFGR2_PREDIV1SRC),
<>	154:37f96f9d4de2	1548	(Source & RCC_CFGR2_PREDIV1) \| ((Source & (RCC_CFGR2_PREDIV1SRC << 4)) >> 4));
<>	154:37f96f9d4de2	1549	#else
<>	154:37f96f9d4de2	1550	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (Source & RCC_CFGR2_PREDIV1));
<>	154:37f96f9d4de2	1551	#endif /RCC_SRC_PREDIV1_SUPPORT/
<>	154:37f96f9d4de2	1552	#endif /RCC_PREDIV1_DIV_2_16_SUPPORT/
<>	154:37f96f9d4de2	1553	}
<>	154:37f96f9d4de2	1554
<>	154:37f96f9d4de2	1555	/**
<>	154:37f96f9d4de2	1556	* @brief Get the oscillator used as PLL clock source.
<>	154:37f96f9d4de2	1557	* @rmtoll CFGR PLLSRC LL_RCC_PLL_GetMainSource\n
<>	154:37f96f9d4de2	1558	* CFGR2 PREDIV1SRC LL_RCC_PLL_GetMainSource
<>	154:37f96f9d4de2	1559	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1560	* @arg @ref LL_RCC_PLLSOURCE_HSI_DIV_2
<>	154:37f96f9d4de2	1561	* @arg @ref LL_RCC_PLLSOURCE_HSE
<>	154:37f96f9d4de2	1562	* @arg @ref LL_RCC_PLLSOURCE_PLL2 (*)
<>	154:37f96f9d4de2	1563	*
<>	154:37f96f9d4de2	1564	* (*) value not defined in all devices
<>	154:37f96f9d4de2	1565	*/
<>	154:37f96f9d4de2	1566	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
<>	154:37f96f9d4de2	1567	{
<>	154:37f96f9d4de2	1568	#if defined(RCC_SRC_PREDIV1_SUPPORT)
<>	154:37f96f9d4de2	1569	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) \| (READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4));
<>	154:37f96f9d4de2	1570	#else
<>	154:37f96f9d4de2	1571	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC));
<>	154:37f96f9d4de2	1572	#endif /RCC_SRC_PREDIV1_SUPPORT/
<>	154:37f96f9d4de2	1573	}
<>	154:37f96f9d4de2	1574
<>	154:37f96f9d4de2	1575	/**
<>	154:37f96f9d4de2	1576	* @brief Get PLL multiplication Factor
<>	154:37f96f9d4de2	1577	* @rmtoll CFGR PLLMULL LL_RCC_PLL_GetMultiplicator
<>	154:37f96f9d4de2	1578	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1579	* @arg @ref LL_RCC_PLL_MUL_2 (*)
<>	154:37f96f9d4de2	1580	* @arg @ref LL_RCC_PLL_MUL_3 (*)
<>	154:37f96f9d4de2	1581	* @arg @ref LL_RCC_PLL_MUL_4
<>	154:37f96f9d4de2	1582	* @arg @ref LL_RCC_PLL_MUL_5
<>	154:37f96f9d4de2	1583	* @arg @ref LL_RCC_PLL_MUL_6
<>	154:37f96f9d4de2	1584	* @arg @ref LL_RCC_PLL_MUL_7
<>	154:37f96f9d4de2	1585	* @arg @ref LL_RCC_PLL_MUL_8
<>	154:37f96f9d4de2	1586	* @arg @ref LL_RCC_PLL_MUL_9
<>	154:37f96f9d4de2	1587	* @arg @ref LL_RCC_PLL_MUL_6_5 (*)
<>	154:37f96f9d4de2	1588	* @arg @ref LL_RCC_PLL_MUL_10 (*)
<>	154:37f96f9d4de2	1589	* @arg @ref LL_RCC_PLL_MUL_11 (*)
<>	154:37f96f9d4de2	1590	* @arg @ref LL_RCC_PLL_MUL_12 (*)
<>	154:37f96f9d4de2	1591	* @arg @ref LL_RCC_PLL_MUL_13 (*)
<>	154:37f96f9d4de2	1592	* @arg @ref LL_RCC_PLL_MUL_14 (*)
<>	154:37f96f9d4de2	1593	* @arg @ref LL_RCC_PLL_MUL_15 (*)
<>	154:37f96f9d4de2	1594	* @arg @ref LL_RCC_PLL_MUL_16 (*)
<>	154:37f96f9d4de2	1595	*
<>	154:37f96f9d4de2	1596	* (*) value not defined in all devices
<>	154:37f96f9d4de2	1597	*/
<>	154:37f96f9d4de2	1598	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMultiplicator(void)
<>	154:37f96f9d4de2	1599	{
<>	154:37f96f9d4de2	1600	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLMULL));
<>	154:37f96f9d4de2	1601	}
<>	154:37f96f9d4de2	1602
<>	154:37f96f9d4de2	1603	/**
<>	154:37f96f9d4de2	1604	* @brief Get PREDIV1 division factor for the main PLL
<>	154:37f96f9d4de2	1605	* @note They can be written only when the PLL is disabled
<>	154:37f96f9d4de2	1606	* @rmtoll CFGR2 PREDIV1 LL_RCC_PLL_GetPrediv\n
<>	154:37f96f9d4de2	1607	* CFGR2 PLLXTPRE LL_RCC_PLL_GetPrediv
<>	154:37f96f9d4de2	1608	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1609	* @arg @ref LL_RCC_PREDIV_DIV_1
<>	154:37f96f9d4de2	1610	* @arg @ref LL_RCC_PREDIV_DIV_2
<>	154:37f96f9d4de2	1611	* @arg @ref LL_RCC_PREDIV_DIV_3 (*)
<>	154:37f96f9d4de2	1612	* @arg @ref LL_RCC_PREDIV_DIV_4 (*)
<>	154:37f96f9d4de2	1613	* @arg @ref LL_RCC_PREDIV_DIV_5 (*)
<>	154:37f96f9d4de2	1614	* @arg @ref LL_RCC_PREDIV_DIV_6 (*)
<>	154:37f96f9d4de2	1615	* @arg @ref LL_RCC_PREDIV_DIV_7 (*)
<>	154:37f96f9d4de2	1616	* @arg @ref LL_RCC_PREDIV_DIV_8 (*)
<>	154:37f96f9d4de2	1617	* @arg @ref LL_RCC_PREDIV_DIV_9 (*)
<>	154:37f96f9d4de2	1618	* @arg @ref LL_RCC_PREDIV_DIV_10 (*)
<>	154:37f96f9d4de2	1619	* @arg @ref LL_RCC_PREDIV_DIV_11 (*)
<>	154:37f96f9d4de2	1620	* @arg @ref LL_RCC_PREDIV_DIV_12 (*)
<>	154:37f96f9d4de2	1621	* @arg @ref LL_RCC_PREDIV_DIV_13 (*)
<>	154:37f96f9d4de2	1622	* @arg @ref LL_RCC_PREDIV_DIV_14 (*)
<>	154:37f96f9d4de2	1623	* @arg @ref LL_RCC_PREDIV_DIV_15 (*)
<>	154:37f96f9d4de2	1624	* @arg @ref LL_RCC_PREDIV_DIV_16 (*)
<>	154:37f96f9d4de2	1625	*
<>	154:37f96f9d4de2	1626	* (*) value not defined in all devices
<>	154:37f96f9d4de2	1627	*/
<>	154:37f96f9d4de2	1628	__STATIC_INLINE uint32_t LL_RCC_PLL_GetPrediv(void)
<>	154:37f96f9d4de2	1629	{
<>	154:37f96f9d4de2	1630	#if defined(RCC_PREDIV1_DIV_2_16_SUPPORT)
<>	154:37f96f9d4de2	1631	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1));
<>	154:37f96f9d4de2	1632	#else
<>	154:37f96f9d4de2	1633	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE));
<>	154:37f96f9d4de2	1634	#endif /RCC_PREDIV1_DIV_2_16_SUPPORT/
<>	154:37f96f9d4de2	1635	}
<>	154:37f96f9d4de2	1636
<>	154:37f96f9d4de2	1637	/**
<>	154:37f96f9d4de2	1638	* @}
<>	154:37f96f9d4de2	1639	*/
<>	154:37f96f9d4de2	1640
<>	154:37f96f9d4de2	1641	#if defined(RCC_PLLI2S_SUPPORT)
<>	154:37f96f9d4de2	1642	/** @defgroup RCC_LL_EF_PLLI2S PLLI2S
<>	154:37f96f9d4de2	1643	* @{
<>	154:37f96f9d4de2	1644	*/
<>	154:37f96f9d4de2	1645
<>	154:37f96f9d4de2	1646	/**
<>	154:37f96f9d4de2	1647	* @brief Enable PLLI2S
<>	154:37f96f9d4de2	1648	* @rmtoll CR PLL3ON LL_RCC_PLLI2S_Enable
<>	154:37f96f9d4de2	1649	* @retval None
<>	154:37f96f9d4de2	1650	*/
<>	154:37f96f9d4de2	1651	__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
<>	154:37f96f9d4de2	1652	{
<>	154:37f96f9d4de2	1653	SET_BIT(RCC->CR, RCC_CR_PLL3ON);
<>	154:37f96f9d4de2	1654	}
<>	154:37f96f9d4de2	1655
<>	154:37f96f9d4de2	1656	/**
<>	154:37f96f9d4de2	1657	* @brief Disable PLLI2S
<>	154:37f96f9d4de2	1658	* @rmtoll CR PLL3ON LL_RCC_PLLI2S_Disable
<>	154:37f96f9d4de2	1659	* @retval None
<>	154:37f96f9d4de2	1660	*/
<>	154:37f96f9d4de2	1661	__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
<>	154:37f96f9d4de2	1662	{
<>	154:37f96f9d4de2	1663	CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
<>	154:37f96f9d4de2	1664	}
<>	154:37f96f9d4de2	1665
<>	154:37f96f9d4de2	1666	/**
<>	154:37f96f9d4de2	1667	* @brief Check if PLLI2S Ready
<>	154:37f96f9d4de2	1668	* @rmtoll CR PLL3RDY LL_RCC_PLLI2S_IsReady
<>	154:37f96f9d4de2	1669	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1670	*/
<>	154:37f96f9d4de2	1671	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
<>	154:37f96f9d4de2	1672	{
<>	154:37f96f9d4de2	1673	return (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY));
<>	154:37f96f9d4de2	1674	}
<>	154:37f96f9d4de2	1675
<>	154:37f96f9d4de2	1676	/**
<>	154:37f96f9d4de2	1677	* @brief Configure PLLI2S used for I2S Domain
<>	154:37f96f9d4de2	1678	* @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLLI2S\n
<>	154:37f96f9d4de2	1679	* CFGR2 PLL3MUL LL_RCC_PLL_ConfigDomain_PLLI2S
<>	154:37f96f9d4de2	1680	* @param Divider This parameter can be one of the following values:
<>	154:37f96f9d4de2	1681	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<>	154:37f96f9d4de2	1682	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<>	154:37f96f9d4de2	1683	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<>	154:37f96f9d4de2	1684	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<>	154:37f96f9d4de2	1685	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<>	154:37f96f9d4de2	1686	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<>	154:37f96f9d4de2	1687	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<>	154:37f96f9d4de2	1688	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<>	154:37f96f9d4de2	1689	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<>	154:37f96f9d4de2	1690	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<>	154:37f96f9d4de2	1691	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<>	154:37f96f9d4de2	1692	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<>	154:37f96f9d4de2	1693	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<>	154:37f96f9d4de2	1694	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<>	154:37f96f9d4de2	1695	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<>	154:37f96f9d4de2	1696	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<>	154:37f96f9d4de2	1697	* @param Multiplicator This parameter can be one of the following values:
<>	154:37f96f9d4de2	1698	* @arg @ref LL_RCC_PLLI2S_MUL_8
<>	154:37f96f9d4de2	1699	* @arg @ref LL_RCC_PLLI2S_MUL_9
<>	154:37f96f9d4de2	1700	* @arg @ref LL_RCC_PLLI2S_MUL_10
<>	154:37f96f9d4de2	1701	* @arg @ref LL_RCC_PLLI2S_MUL_11
<>	154:37f96f9d4de2	1702	* @arg @ref LL_RCC_PLLI2S_MUL_12
<>	154:37f96f9d4de2	1703	* @arg @ref LL_RCC_PLLI2S_MUL_13
<>	154:37f96f9d4de2	1704	* @arg @ref LL_RCC_PLLI2S_MUL_14
<>	154:37f96f9d4de2	1705	* @arg @ref LL_RCC_PLLI2S_MUL_16
<>	154:37f96f9d4de2	1706	* @arg @ref LL_RCC_PLLI2S_MUL_20
<>	154:37f96f9d4de2	1707	* @retval None
<>	154:37f96f9d4de2	1708	*/
<>	154:37f96f9d4de2	1709	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLLI2S(uint32_t Divider, uint32_t Multiplicator)
<>	154:37f96f9d4de2	1710	{
<>	154:37f96f9d4de2	1711	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL3MUL, Divider \| Multiplicator);
<>	154:37f96f9d4de2	1712	}
<>	154:37f96f9d4de2	1713
<>	154:37f96f9d4de2	1714	/**
<>	154:37f96f9d4de2	1715	* @brief Get PLLI2S Multiplication Factor
<>	154:37f96f9d4de2	1716	* @rmtoll CFGR2 PLL3MUL LL_RCC_PLLI2S_GetMultiplicator
<>	154:37f96f9d4de2	1717	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1718	* @arg @ref LL_RCC_PLLI2S_MUL_8
<>	154:37f96f9d4de2	1719	* @arg @ref LL_RCC_PLLI2S_MUL_9
<>	154:37f96f9d4de2	1720	* @arg @ref LL_RCC_PLLI2S_MUL_10
<>	154:37f96f9d4de2	1721	* @arg @ref LL_RCC_PLLI2S_MUL_11
<>	154:37f96f9d4de2	1722	* @arg @ref LL_RCC_PLLI2S_MUL_12
<>	154:37f96f9d4de2	1723	* @arg @ref LL_RCC_PLLI2S_MUL_13
<>	154:37f96f9d4de2	1724	* @arg @ref LL_RCC_PLLI2S_MUL_14
<>	154:37f96f9d4de2	1725	* @arg @ref LL_RCC_PLLI2S_MUL_16
<>	154:37f96f9d4de2	1726	* @arg @ref LL_RCC_PLLI2S_MUL_20
<>	154:37f96f9d4de2	1727	*/
<>	154:37f96f9d4de2	1728	__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMultiplicator(void)
<>	154:37f96f9d4de2	1729	{
<>	154:37f96f9d4de2	1730	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL));
<>	154:37f96f9d4de2	1731	}
<>	154:37f96f9d4de2	1732
<>	154:37f96f9d4de2	1733	/**
<>	154:37f96f9d4de2	1734	* @}
<>	154:37f96f9d4de2	1735	*/
<>	154:37f96f9d4de2	1736	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	1737
<>	154:37f96f9d4de2	1738	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	1739	/** @defgroup RCC_LL_EF_PLL2 PLL2
<>	154:37f96f9d4de2	1740	* @{
<>	154:37f96f9d4de2	1741	*/
<>	154:37f96f9d4de2	1742
<>	154:37f96f9d4de2	1743	/**
<>	154:37f96f9d4de2	1744	* @brief Enable PLL2
<>	154:37f96f9d4de2	1745	* @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
<>	154:37f96f9d4de2	1746	* @retval None
<>	154:37f96f9d4de2	1747	*/
<>	154:37f96f9d4de2	1748	__STATIC_INLINE void LL_RCC_PLL2_Enable(void)
<>	154:37f96f9d4de2	1749	{
<>	154:37f96f9d4de2	1750	SET_BIT(RCC->CR, RCC_CR_PLL2ON);
<>	154:37f96f9d4de2	1751	}
<>	154:37f96f9d4de2	1752
<>	154:37f96f9d4de2	1753	/**
<>	154:37f96f9d4de2	1754	* @brief Disable PLL2
<>	154:37f96f9d4de2	1755	* @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
<>	154:37f96f9d4de2	1756	* @retval None
<>	154:37f96f9d4de2	1757	*/
<>	154:37f96f9d4de2	1758	__STATIC_INLINE void LL_RCC_PLL2_Disable(void)
<>	154:37f96f9d4de2	1759	{
<>	154:37f96f9d4de2	1760	CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
<>	154:37f96f9d4de2	1761	}
<>	154:37f96f9d4de2	1762
<>	154:37f96f9d4de2	1763	/**
<>	154:37f96f9d4de2	1764	* @brief Check if PLL2 Ready
<>	154:37f96f9d4de2	1765	* @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
<>	154:37f96f9d4de2	1766	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1767	*/
<>	154:37f96f9d4de2	1768	__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
<>	154:37f96f9d4de2	1769	{
<>	154:37f96f9d4de2	1770	return (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY));
<>	154:37f96f9d4de2	1771	}
<>	154:37f96f9d4de2	1772
<>	154:37f96f9d4de2	1773	/**
<>	154:37f96f9d4de2	1774	* @brief Configure PLL2 used for PLL2 Domain
<>	154:37f96f9d4de2	1775	* @rmtoll CFGR2 PREDIV2 LL_RCC_PLL_ConfigDomain_PLL2\n
<>	154:37f96f9d4de2	1776	* CFGR2 PLL2MUL LL_RCC_PLL_ConfigDomain_PLL2
<>	154:37f96f9d4de2	1777	* @param Divider This parameter can be one of the following values:
<>	154:37f96f9d4de2	1778	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_1
<>	154:37f96f9d4de2	1779	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_2
<>	154:37f96f9d4de2	1780	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_3
<>	154:37f96f9d4de2	1781	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_4
<>	154:37f96f9d4de2	1782	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_5
<>	154:37f96f9d4de2	1783	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_6
<>	154:37f96f9d4de2	1784	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_7
<>	154:37f96f9d4de2	1785	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_8
<>	154:37f96f9d4de2	1786	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_9
<>	154:37f96f9d4de2	1787	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_10
<>	154:37f96f9d4de2	1788	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_11
<>	154:37f96f9d4de2	1789	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_12
<>	154:37f96f9d4de2	1790	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_13
<>	154:37f96f9d4de2	1791	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_14
<>	154:37f96f9d4de2	1792	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_15
<>	154:37f96f9d4de2	1793	* @arg @ref LL_RCC_HSE_PREDIV2_DIV_16
<>	154:37f96f9d4de2	1794	* @param Multiplicator This parameter can be one of the following values:
<>	154:37f96f9d4de2	1795	* @arg @ref LL_RCC_PLL2_MUL_8
<>	154:37f96f9d4de2	1796	* @arg @ref LL_RCC_PLL2_MUL_9
<>	154:37f96f9d4de2	1797	* @arg @ref LL_RCC_PLL2_MUL_10
<>	154:37f96f9d4de2	1798	* @arg @ref LL_RCC_PLL2_MUL_11
<>	154:37f96f9d4de2	1799	* @arg @ref LL_RCC_PLL2_MUL_12
<>	154:37f96f9d4de2	1800	* @arg @ref LL_RCC_PLL2_MUL_13
<>	154:37f96f9d4de2	1801	* @arg @ref LL_RCC_PLL2_MUL_14
<>	154:37f96f9d4de2	1802	* @arg @ref LL_RCC_PLL2_MUL_16
<>	154:37f96f9d4de2	1803	* @arg @ref LL_RCC_PLL2_MUL_20
<>	154:37f96f9d4de2	1804	* @retval None
<>	154:37f96f9d4de2	1805	*/
<>	154:37f96f9d4de2	1806	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_PLL2(uint32_t Divider, uint32_t Multiplicator)
<>	154:37f96f9d4de2	1807	{
<>	154:37f96f9d4de2	1808	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2 \| RCC_CFGR2_PLL2MUL, Divider \| Multiplicator);
<>	154:37f96f9d4de2	1809	}
<>	154:37f96f9d4de2	1810
<>	154:37f96f9d4de2	1811	/**
<>	154:37f96f9d4de2	1812	* @brief Get PLL2 Multiplication Factor
<>	154:37f96f9d4de2	1813	* @rmtoll CFGR2 PLL2MUL LL_RCC_PLL2_GetMultiplicator
<>	154:37f96f9d4de2	1814	* @retval Returned value can be one of the following values:
<>	154:37f96f9d4de2	1815	* @arg @ref LL_RCC_PLL2_MUL_8
<>	154:37f96f9d4de2	1816	* @arg @ref LL_RCC_PLL2_MUL_9
<>	154:37f96f9d4de2	1817	* @arg @ref LL_RCC_PLL2_MUL_10
<>	154:37f96f9d4de2	1818	* @arg @ref LL_RCC_PLL2_MUL_11
<>	154:37f96f9d4de2	1819	* @arg @ref LL_RCC_PLL2_MUL_12
<>	154:37f96f9d4de2	1820	* @arg @ref LL_RCC_PLL2_MUL_13
<>	154:37f96f9d4de2	1821	* @arg @ref LL_RCC_PLL2_MUL_14
<>	154:37f96f9d4de2	1822	* @arg @ref LL_RCC_PLL2_MUL_16
<>	154:37f96f9d4de2	1823	* @arg @ref LL_RCC_PLL2_MUL_20
<>	154:37f96f9d4de2	1824	*/
<>	154:37f96f9d4de2	1825	__STATIC_INLINE uint32_t LL_RCC_PLL2_GetMultiplicator(void)
<>	154:37f96f9d4de2	1826	{
<>	154:37f96f9d4de2	1827	return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL2MUL));
<>	154:37f96f9d4de2	1828	}
<>	154:37f96f9d4de2	1829
<>	154:37f96f9d4de2	1830	/**
<>	154:37f96f9d4de2	1831	* @}
<>	154:37f96f9d4de2	1832	*/
<>	154:37f96f9d4de2	1833	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	1834
<>	154:37f96f9d4de2	1835	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
<>	154:37f96f9d4de2	1836	* @{
<>	154:37f96f9d4de2	1837	*/
<>	154:37f96f9d4de2	1838
<>	154:37f96f9d4de2	1839	/**
<>	154:37f96f9d4de2	1840	* @brief Clear LSI ready interrupt flag
<>	154:37f96f9d4de2	1841	* @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
<>	154:37f96f9d4de2	1842	* @retval None
<>	154:37f96f9d4de2	1843	*/
<>	154:37f96f9d4de2	1844	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
<>	154:37f96f9d4de2	1845	{
<>	154:37f96f9d4de2	1846	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
<>	154:37f96f9d4de2	1847	}
<>	154:37f96f9d4de2	1848
<>	154:37f96f9d4de2	1849	/**
<>	154:37f96f9d4de2	1850	* @brief Clear LSE ready interrupt flag
<>	154:37f96f9d4de2	1851	* @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
<>	154:37f96f9d4de2	1852	* @retval None
<>	154:37f96f9d4de2	1853	*/
<>	154:37f96f9d4de2	1854	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
<>	154:37f96f9d4de2	1855	{
<>	154:37f96f9d4de2	1856	SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
<>	154:37f96f9d4de2	1857	}
<>	154:37f96f9d4de2	1858
<>	154:37f96f9d4de2	1859	/**
<>	154:37f96f9d4de2	1860	* @brief Clear HSI ready interrupt flag
<>	154:37f96f9d4de2	1861	* @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
<>	154:37f96f9d4de2	1862	* @retval None
<>	154:37f96f9d4de2	1863	*/
<>	154:37f96f9d4de2	1864	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
<>	154:37f96f9d4de2	1865	{
<>	154:37f96f9d4de2	1866	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
<>	154:37f96f9d4de2	1867	}
<>	154:37f96f9d4de2	1868
<>	154:37f96f9d4de2	1869	/**
<>	154:37f96f9d4de2	1870	* @brief Clear HSE ready interrupt flag
<>	154:37f96f9d4de2	1871	* @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
<>	154:37f96f9d4de2	1872	* @retval None
<>	154:37f96f9d4de2	1873	*/
<>	154:37f96f9d4de2	1874	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
<>	154:37f96f9d4de2	1875	{
<>	154:37f96f9d4de2	1876	SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
<>	154:37f96f9d4de2	1877	}
<>	154:37f96f9d4de2	1878
<>	154:37f96f9d4de2	1879	/**
<>	154:37f96f9d4de2	1880	* @brief Clear PLL ready interrupt flag
<>	154:37f96f9d4de2	1881	* @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
<>	154:37f96f9d4de2	1882	* @retval None
<>	154:37f96f9d4de2	1883	*/
<>	154:37f96f9d4de2	1884	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
<>	154:37f96f9d4de2	1885	{
<>	154:37f96f9d4de2	1886	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
<>	154:37f96f9d4de2	1887	}
<>	154:37f96f9d4de2	1888
<>	154:37f96f9d4de2	1889	#if defined(RCC_PLLI2S_SUPPORT)
<>	154:37f96f9d4de2	1890	/**
<>	154:37f96f9d4de2	1891	* @brief Clear PLLI2S ready interrupt flag
<>	154:37f96f9d4de2	1892	* @rmtoll CIR PLL3RDYC LL_RCC_ClearFlag_PLLI2SRDY
<>	154:37f96f9d4de2	1893	* @retval None
<>	154:37f96f9d4de2	1894	*/
<>	154:37f96f9d4de2	1895	__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
<>	154:37f96f9d4de2	1896	{
<>	154:37f96f9d4de2	1897	SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYC);
<>	154:37f96f9d4de2	1898	}
<>	154:37f96f9d4de2	1899	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	1900
<>	154:37f96f9d4de2	1901	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	1902	/**
<>	154:37f96f9d4de2	1903	* @brief Clear PLL2 ready interrupt flag
<>	154:37f96f9d4de2	1904	* @rmtoll CIR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
<>	154:37f96f9d4de2	1905	* @retval None
<>	154:37f96f9d4de2	1906	*/
<>	154:37f96f9d4de2	1907	__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
<>	154:37f96f9d4de2	1908	{
<>	154:37f96f9d4de2	1909	SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYC);
<>	154:37f96f9d4de2	1910	}
<>	154:37f96f9d4de2	1911	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	1912
<>	154:37f96f9d4de2	1913	/**
<>	154:37f96f9d4de2	1914	* @brief Clear Clock security system interrupt flag
<>	154:37f96f9d4de2	1915	* @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
<>	154:37f96f9d4de2	1916	* @retval None
<>	154:37f96f9d4de2	1917	*/
<>	154:37f96f9d4de2	1918	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
<>	154:37f96f9d4de2	1919	{
<>	154:37f96f9d4de2	1920	SET_BIT(RCC->CIR, RCC_CIR_CSSC);
<>	154:37f96f9d4de2	1921	}
<>	154:37f96f9d4de2	1922
<>	154:37f96f9d4de2	1923	/**
<>	154:37f96f9d4de2	1924	* @brief Check if LSI ready interrupt occurred or not
<>	154:37f96f9d4de2	1925	* @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
<>	154:37f96f9d4de2	1926	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1927	*/
<>	154:37f96f9d4de2	1928	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
<>	154:37f96f9d4de2	1929	{
<>	154:37f96f9d4de2	1930	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
<>	154:37f96f9d4de2	1931	}
<>	154:37f96f9d4de2	1932
<>	154:37f96f9d4de2	1933	/**
<>	154:37f96f9d4de2	1934	* @brief Check if LSE ready interrupt occurred or not
<>	154:37f96f9d4de2	1935	* @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
<>	154:37f96f9d4de2	1936	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1937	*/
<>	154:37f96f9d4de2	1938	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
<>	154:37f96f9d4de2	1939	{
<>	154:37f96f9d4de2	1940	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
<>	154:37f96f9d4de2	1941	}
<>	154:37f96f9d4de2	1942
<>	154:37f96f9d4de2	1943	/**
<>	154:37f96f9d4de2	1944	* @brief Check if HSI ready interrupt occurred or not
<>	154:37f96f9d4de2	1945	* @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
<>	154:37f96f9d4de2	1946	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1947	*/
<>	154:37f96f9d4de2	1948	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
<>	154:37f96f9d4de2	1949	{
<>	154:37f96f9d4de2	1950	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
<>	154:37f96f9d4de2	1951	}
<>	154:37f96f9d4de2	1952
<>	154:37f96f9d4de2	1953	/**
<>	154:37f96f9d4de2	1954	* @brief Check if HSE ready interrupt occurred or not
<>	154:37f96f9d4de2	1955	* @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
<>	154:37f96f9d4de2	1956	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1957	*/
<>	154:37f96f9d4de2	1958	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
<>	154:37f96f9d4de2	1959	{
<>	154:37f96f9d4de2	1960	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
<>	154:37f96f9d4de2	1961	}
<>	154:37f96f9d4de2	1962
<>	154:37f96f9d4de2	1963	/**
<>	154:37f96f9d4de2	1964	* @brief Check if PLL ready interrupt occurred or not
<>	154:37f96f9d4de2	1965	* @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
<>	154:37f96f9d4de2	1966	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1967	*/
<>	154:37f96f9d4de2	1968	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
<>	154:37f96f9d4de2	1969	{
<>	154:37f96f9d4de2	1970	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
<>	154:37f96f9d4de2	1971	}
<>	154:37f96f9d4de2	1972
<>	154:37f96f9d4de2	1973	#if defined(RCC_PLLI2S_SUPPORT)
<>	154:37f96f9d4de2	1974	/**
<>	154:37f96f9d4de2	1975	* @brief Check if PLLI2S ready interrupt occurred or not
<>	154:37f96f9d4de2	1976	* @rmtoll CIR PLL3RDYF LL_RCC_IsActiveFlag_PLLI2SRDY
<>	154:37f96f9d4de2	1977	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1978	*/
<>	154:37f96f9d4de2	1979	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
<>	154:37f96f9d4de2	1980	{
<>	154:37f96f9d4de2	1981	return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYF) == (RCC_CIR_PLL3RDYF));
<>	154:37f96f9d4de2	1982	}
<>	154:37f96f9d4de2	1983	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	1984
<>	154:37f96f9d4de2	1985	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	1986	/**
<>	154:37f96f9d4de2	1987	* @brief Check if PLL2 ready interrupt occurred or not
<>	154:37f96f9d4de2	1988	* @rmtoll CIR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
<>	154:37f96f9d4de2	1989	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	1990	*/
<>	154:37f96f9d4de2	1991	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
<>	154:37f96f9d4de2	1992	{
<>	154:37f96f9d4de2	1993	return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYF) == (RCC_CIR_PLL2RDYF));
<>	154:37f96f9d4de2	1994	}
<>	154:37f96f9d4de2	1995	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	1996
<>	154:37f96f9d4de2	1997	/**
<>	154:37f96f9d4de2	1998	* @brief Check if Clock security system interrupt occurred or not
<>	154:37f96f9d4de2	1999	* @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
<>	154:37f96f9d4de2	2000	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2001	*/
<>	154:37f96f9d4de2	2002	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
<>	154:37f96f9d4de2	2003	{
<>	154:37f96f9d4de2	2004	return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
<>	154:37f96f9d4de2	2005	}
<>	154:37f96f9d4de2	2006
<>	154:37f96f9d4de2	2007	/**
<>	154:37f96f9d4de2	2008	* @brief Check if RCC flag Independent Watchdog reset is set or not.
<>	154:37f96f9d4de2	2009	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
<>	154:37f96f9d4de2	2010	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2011	*/
<>	154:37f96f9d4de2	2012	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
<>	154:37f96f9d4de2	2013	{
<>	154:37f96f9d4de2	2014	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
<>	154:37f96f9d4de2	2015	}
<>	154:37f96f9d4de2	2016
<>	154:37f96f9d4de2	2017	/**
<>	154:37f96f9d4de2	2018	* @brief Check if RCC flag Low Power reset is set or not.
<>	154:37f96f9d4de2	2019	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
<>	154:37f96f9d4de2	2020	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2021	*/
<>	154:37f96f9d4de2	2022	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
<>	154:37f96f9d4de2	2023	{
<>	154:37f96f9d4de2	2024	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
<>	154:37f96f9d4de2	2025	}
<>	154:37f96f9d4de2	2026
<>	154:37f96f9d4de2	2027	/**
<>	154:37f96f9d4de2	2028	* @brief Check if RCC flag Pin reset is set or not.
<>	154:37f96f9d4de2	2029	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
<>	154:37f96f9d4de2	2030	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2031	*/
<>	154:37f96f9d4de2	2032	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
<>	154:37f96f9d4de2	2033	{
<>	154:37f96f9d4de2	2034	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
<>	154:37f96f9d4de2	2035	}
<>	154:37f96f9d4de2	2036
<>	154:37f96f9d4de2	2037	/**
<>	154:37f96f9d4de2	2038	* @brief Check if RCC flag POR/PDR reset is set or not.
<>	154:37f96f9d4de2	2039	* @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
<>	154:37f96f9d4de2	2040	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2041	*/
<>	154:37f96f9d4de2	2042	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
<>	154:37f96f9d4de2	2043	{
<>	154:37f96f9d4de2	2044	return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
<>	154:37f96f9d4de2	2045	}
<>	154:37f96f9d4de2	2046
<>	154:37f96f9d4de2	2047	/**
<>	154:37f96f9d4de2	2048	* @brief Check if RCC flag Software reset is set or not.
<>	154:37f96f9d4de2	2049	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
<>	154:37f96f9d4de2	2050	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2051	*/
<>	154:37f96f9d4de2	2052	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
<>	154:37f96f9d4de2	2053	{
<>	154:37f96f9d4de2	2054	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
<>	154:37f96f9d4de2	2055	}
<>	154:37f96f9d4de2	2056
<>	154:37f96f9d4de2	2057	/**
<>	154:37f96f9d4de2	2058	* @brief Check if RCC flag Window Watchdog reset is set or not.
<>	154:37f96f9d4de2	2059	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
<>	154:37f96f9d4de2	2060	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2061	*/
<>	154:37f96f9d4de2	2062	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
<>	154:37f96f9d4de2	2063	{
<>	154:37f96f9d4de2	2064	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
<>	154:37f96f9d4de2	2065	}
<>	154:37f96f9d4de2	2066
<>	154:37f96f9d4de2	2067	/**
<>	154:37f96f9d4de2	2068	* @brief Set RMVF bit to clear the reset flags.
<>	154:37f96f9d4de2	2069	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
<>	154:37f96f9d4de2	2070	* @retval None
<>	154:37f96f9d4de2	2071	*/
<>	154:37f96f9d4de2	2072	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
<>	154:37f96f9d4de2	2073	{
<>	154:37f96f9d4de2	2074	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
<>	154:37f96f9d4de2	2075	}
<>	154:37f96f9d4de2	2076
<>	154:37f96f9d4de2	2077	/**
<>	154:37f96f9d4de2	2078	* @}
<>	154:37f96f9d4de2	2079	*/
<>	154:37f96f9d4de2	2080
<>	154:37f96f9d4de2	2081	/** @defgroup RCC_LL_EF_IT_Management IT Management
<>	154:37f96f9d4de2	2082	* @{
<>	154:37f96f9d4de2	2083	*/
<>	154:37f96f9d4de2	2084
<>	154:37f96f9d4de2	2085	/**
<>	154:37f96f9d4de2	2086	* @brief Enable LSI ready interrupt
<>	154:37f96f9d4de2	2087	* @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
<>	154:37f96f9d4de2	2088	* @retval None
<>	154:37f96f9d4de2	2089	*/
<>	154:37f96f9d4de2	2090	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
<>	154:37f96f9d4de2	2091	{
<>	154:37f96f9d4de2	2092	SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<>	154:37f96f9d4de2	2093	}
<>	154:37f96f9d4de2	2094
<>	154:37f96f9d4de2	2095	/**
<>	154:37f96f9d4de2	2096	* @brief Enable LSE ready interrupt
<>	154:37f96f9d4de2	2097	* @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
<>	154:37f96f9d4de2	2098	* @retval None
<>	154:37f96f9d4de2	2099	*/
<>	154:37f96f9d4de2	2100	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
<>	154:37f96f9d4de2	2101	{
<>	154:37f96f9d4de2	2102	SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<>	154:37f96f9d4de2	2103	}
<>	154:37f96f9d4de2	2104
<>	154:37f96f9d4de2	2105	/**
<>	154:37f96f9d4de2	2106	* @brief Enable HSI ready interrupt
<>	154:37f96f9d4de2	2107	* @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
<>	154:37f96f9d4de2	2108	* @retval None
<>	154:37f96f9d4de2	2109	*/
<>	154:37f96f9d4de2	2110	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
<>	154:37f96f9d4de2	2111	{
<>	154:37f96f9d4de2	2112	SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<>	154:37f96f9d4de2	2113	}
<>	154:37f96f9d4de2	2114
<>	154:37f96f9d4de2	2115	/**
<>	154:37f96f9d4de2	2116	* @brief Enable HSE ready interrupt
<>	154:37f96f9d4de2	2117	* @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
<>	154:37f96f9d4de2	2118	* @retval None
<>	154:37f96f9d4de2	2119	*/
<>	154:37f96f9d4de2	2120	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
<>	154:37f96f9d4de2	2121	{
<>	154:37f96f9d4de2	2122	SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<>	154:37f96f9d4de2	2123	}
<>	154:37f96f9d4de2	2124
<>	154:37f96f9d4de2	2125	/**
<>	154:37f96f9d4de2	2126	* @brief Enable PLL ready interrupt
<>	154:37f96f9d4de2	2127	* @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
<>	154:37f96f9d4de2	2128	* @retval None
<>	154:37f96f9d4de2	2129	*/
<>	154:37f96f9d4de2	2130	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
<>	154:37f96f9d4de2	2131	{
<>	154:37f96f9d4de2	2132	SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<>	154:37f96f9d4de2	2133	}
<>	154:37f96f9d4de2	2134
<>	154:37f96f9d4de2	2135	#if defined(RCC_PLLI2S_SUPPORT)
<>	154:37f96f9d4de2	2136	/**
<>	154:37f96f9d4de2	2137	* @brief Enable PLLI2S ready interrupt
<>	154:37f96f9d4de2	2138	* @rmtoll CIR PLL3RDYIE LL_RCC_EnableIT_PLLI2SRDY
<>	154:37f96f9d4de2	2139	* @retval None
<>	154:37f96f9d4de2	2140	*/
<>	154:37f96f9d4de2	2141	__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
<>	154:37f96f9d4de2	2142	{
<>	154:37f96f9d4de2	2143	SET_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
<>	154:37f96f9d4de2	2144	}
<>	154:37f96f9d4de2	2145	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	2146
<>	154:37f96f9d4de2	2147	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	2148	/**
<>	154:37f96f9d4de2	2149	* @brief Enable PLL2 ready interrupt
<>	154:37f96f9d4de2	2150	* @rmtoll CIR PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
<>	154:37f96f9d4de2	2151	* @retval None
<>	154:37f96f9d4de2	2152	*/
<>	154:37f96f9d4de2	2153	__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
<>	154:37f96f9d4de2	2154	{
<>	154:37f96f9d4de2	2155	SET_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
<>	154:37f96f9d4de2	2156	}
<>	154:37f96f9d4de2	2157	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	2158
<>	154:37f96f9d4de2	2159	/**
<>	154:37f96f9d4de2	2160	* @brief Disable LSI ready interrupt
<>	154:37f96f9d4de2	2161	* @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
<>	154:37f96f9d4de2	2162	* @retval None
<>	154:37f96f9d4de2	2163	*/
<>	154:37f96f9d4de2	2164	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
<>	154:37f96f9d4de2	2165	{
<>	154:37f96f9d4de2	2166	CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
<>	154:37f96f9d4de2	2167	}
<>	154:37f96f9d4de2	2168
<>	154:37f96f9d4de2	2169	/**
<>	154:37f96f9d4de2	2170	* @brief Disable LSE ready interrupt
<>	154:37f96f9d4de2	2171	* @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
<>	154:37f96f9d4de2	2172	* @retval None
<>	154:37f96f9d4de2	2173	*/
<>	154:37f96f9d4de2	2174	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
<>	154:37f96f9d4de2	2175	{
<>	154:37f96f9d4de2	2176	CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
<>	154:37f96f9d4de2	2177	}
<>	154:37f96f9d4de2	2178
<>	154:37f96f9d4de2	2179	/**
<>	154:37f96f9d4de2	2180	* @brief Disable HSI ready interrupt
<>	154:37f96f9d4de2	2181	* @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
<>	154:37f96f9d4de2	2182	* @retval None
<>	154:37f96f9d4de2	2183	*/
<>	154:37f96f9d4de2	2184	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
<>	154:37f96f9d4de2	2185	{
<>	154:37f96f9d4de2	2186	CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
<>	154:37f96f9d4de2	2187	}
<>	154:37f96f9d4de2	2188
<>	154:37f96f9d4de2	2189	/**
<>	154:37f96f9d4de2	2190	* @brief Disable HSE ready interrupt
<>	154:37f96f9d4de2	2191	* @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
<>	154:37f96f9d4de2	2192	* @retval None
<>	154:37f96f9d4de2	2193	*/
<>	154:37f96f9d4de2	2194	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
<>	154:37f96f9d4de2	2195	{
<>	154:37f96f9d4de2	2196	CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
<>	154:37f96f9d4de2	2197	}
<>	154:37f96f9d4de2	2198
<>	154:37f96f9d4de2	2199	/**
<>	154:37f96f9d4de2	2200	* @brief Disable PLL ready interrupt
<>	154:37f96f9d4de2	2201	* @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
<>	154:37f96f9d4de2	2202	* @retval None
<>	154:37f96f9d4de2	2203	*/
<>	154:37f96f9d4de2	2204	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
<>	154:37f96f9d4de2	2205	{
<>	154:37f96f9d4de2	2206	CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
<>	154:37f96f9d4de2	2207	}
<>	154:37f96f9d4de2	2208
<>	154:37f96f9d4de2	2209	#if defined(RCC_PLLI2S_SUPPORT)
<>	154:37f96f9d4de2	2210	/**
<>	154:37f96f9d4de2	2211	* @brief Disable PLLI2S ready interrupt
<>	154:37f96f9d4de2	2212	* @rmtoll CIR PLL3RDYIE LL_RCC_DisableIT_PLLI2SRDY
<>	154:37f96f9d4de2	2213	* @retval None
<>	154:37f96f9d4de2	2214	*/
<>	154:37f96f9d4de2	2215	__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
<>	154:37f96f9d4de2	2216	{
<>	154:37f96f9d4de2	2217	CLEAR_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE);
<>	154:37f96f9d4de2	2218	}
<>	154:37f96f9d4de2	2219	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	2220
<>	154:37f96f9d4de2	2221	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	2222	/**
<>	154:37f96f9d4de2	2223	* @brief Disable PLL2 ready interrupt
<>	154:37f96f9d4de2	2224	* @rmtoll CIR PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
<>	154:37f96f9d4de2	2225	* @retval None
<>	154:37f96f9d4de2	2226	*/
<>	154:37f96f9d4de2	2227	__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
<>	154:37f96f9d4de2	2228	{
<>	154:37f96f9d4de2	2229	CLEAR_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE);
<>	154:37f96f9d4de2	2230	}
<>	154:37f96f9d4de2	2231	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	2232
<>	154:37f96f9d4de2	2233	/**
<>	154:37f96f9d4de2	2234	* @brief Checks if LSI ready interrupt source is enabled or disabled.
<>	154:37f96f9d4de2	2235	* @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
<>	154:37f96f9d4de2	2236	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2237	*/
<>	154:37f96f9d4de2	2238	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
<>	154:37f96f9d4de2	2239	{
<>	154:37f96f9d4de2	2240	return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
<>	154:37f96f9d4de2	2241	}
<>	154:37f96f9d4de2	2242
<>	154:37f96f9d4de2	2243	/**
<>	154:37f96f9d4de2	2244	* @brief Checks if LSE ready interrupt source is enabled or disabled.
<>	154:37f96f9d4de2	2245	* @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
<>	154:37f96f9d4de2	2246	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2247	*/
<>	154:37f96f9d4de2	2248	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
<>	154:37f96f9d4de2	2249	{
<>	154:37f96f9d4de2	2250	return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
<>	154:37f96f9d4de2	2251	}
<>	154:37f96f9d4de2	2252
<>	154:37f96f9d4de2	2253	/**
<>	154:37f96f9d4de2	2254	* @brief Checks if HSI ready interrupt source is enabled or disabled.
<>	154:37f96f9d4de2	2255	* @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
<>	154:37f96f9d4de2	2256	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2257	*/
<>	154:37f96f9d4de2	2258	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
<>	154:37f96f9d4de2	2259	{
<>	154:37f96f9d4de2	2260	return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
<>	154:37f96f9d4de2	2261	}
<>	154:37f96f9d4de2	2262
<>	154:37f96f9d4de2	2263	/**
<>	154:37f96f9d4de2	2264	* @brief Checks if HSE ready interrupt source is enabled or disabled.
<>	154:37f96f9d4de2	2265	* @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
<>	154:37f96f9d4de2	2266	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2267	*/
<>	154:37f96f9d4de2	2268	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
<>	154:37f96f9d4de2	2269	{
<>	154:37f96f9d4de2	2270	return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
<>	154:37f96f9d4de2	2271	}
<>	154:37f96f9d4de2	2272
<>	154:37f96f9d4de2	2273	/**
<>	154:37f96f9d4de2	2274	* @brief Checks if PLL ready interrupt source is enabled or disabled.
<>	154:37f96f9d4de2	2275	* @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
<>	154:37f96f9d4de2	2276	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2277	*/
<>	154:37f96f9d4de2	2278	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
<>	154:37f96f9d4de2	2279	{
<>	154:37f96f9d4de2	2280	return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
<>	154:37f96f9d4de2	2281	}
<>	154:37f96f9d4de2	2282
<>	154:37f96f9d4de2	2283	#if defined(RCC_PLLI2S_SUPPORT)
<>	154:37f96f9d4de2	2284	/**
<>	154:37f96f9d4de2	2285	* @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
<>	154:37f96f9d4de2	2286	* @rmtoll CIR PLL3RDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
<>	154:37f96f9d4de2	2287	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2288	*/
<>	154:37f96f9d4de2	2289	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
<>	154:37f96f9d4de2	2290	{
<>	154:37f96f9d4de2	2291	return (READ_BIT(RCC->CIR, RCC_CIR_PLL3RDYIE) == (RCC_CIR_PLL3RDYIE));
<>	154:37f96f9d4de2	2292	}
<>	154:37f96f9d4de2	2293	#endif /* RCC_PLLI2S_SUPPORT */
<>	154:37f96f9d4de2	2294
<>	154:37f96f9d4de2	2295	#if defined(RCC_PLL2_SUPPORT)
<>	154:37f96f9d4de2	2296	/**
<>	154:37f96f9d4de2	2297	* @brief Checks if PLL2 ready interrupt source is enabled or disabled.
<>	154:37f96f9d4de2	2298	* @rmtoll CIR PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY
<>	154:37f96f9d4de2	2299	* @retval State of bit (1 or 0).
<>	154:37f96f9d4de2	2300	*/
<>	154:37f96f9d4de2	2301	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void)
<>	154:37f96f9d4de2	2302	{
<>	154:37f96f9d4de2	2303	return (READ_BIT(RCC->CIR, RCC_CIR_PLL2RDYIE) == (RCC_CIR_PLL2RDYIE));
<>	154:37f96f9d4de2	2304	}
<>	154:37f96f9d4de2	2305	#endif /* RCC_PLL2_SUPPORT */
<>	154:37f96f9d4de2	2306
<>	154:37f96f9d4de2	2307	/**
<>	154:37f96f9d4de2	2308	* @}
<>	154:37f96f9d4de2	2309	*/
<>	154:37f96f9d4de2	2310
<>	154:37f96f9d4de2	2311	#if defined(USE_FULL_LL_DRIVER)
<>	154:37f96f9d4de2	2312	/** @defgroup RCC_LL_EF_Init De-initialization function
<>	154:37f96f9d4de2	2313	* @{
<>	154:37f96f9d4de2	2314	*/
<>	154:37f96f9d4de2	2315	ErrorStatus LL_RCC_DeInit(void);
<>	154:37f96f9d4de2	2316	/**
<>	154:37f96f9d4de2	2317	* @}
<>	154:37f96f9d4de2	2318	*/
<>	154:37f96f9d4de2	2319
<>	154:37f96f9d4de2	2320	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
<>	154:37f96f9d4de2	2321	* @{
<>	154:37f96f9d4de2	2322	*/
<>	154:37f96f9d4de2	2323	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
<>	154:37f96f9d4de2	2324	#if defined(RCC_CFGR2_I2S2SRC)
<>	154:37f96f9d4de2	2325	uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
<>	154:37f96f9d4de2	2326	#endif /* RCC_CFGR2_I2S2SRC */
<>	154:37f96f9d4de2	2327	#if defined(USB_OTG_FS) \|\| defined(USB)
<>	154:37f96f9d4de2	2328	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
<>	154:37f96f9d4de2	2329	#endif /* USB_OTG_FS \|\| USB */
<>	154:37f96f9d4de2	2330	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
<>	154:37f96f9d4de2	2331	/**
<>	154:37f96f9d4de2	2332	* @}
<>	154:37f96f9d4de2	2333	*/
<>	154:37f96f9d4de2	2334	#endif /* USE_FULL_LL_DRIVER */
<>	154:37f96f9d4de2	2335
<>	154:37f96f9d4de2	2336	/**
<>	154:37f96f9d4de2	2337	* @}
<>	154:37f96f9d4de2	2338	*/
<>	154:37f96f9d4de2	2339
<>	154:37f96f9d4de2	2340	/**
<>	154:37f96f9d4de2	2341	* @}
<>	154:37f96f9d4de2	2342	*/
<>	154:37f96f9d4de2	2343
<>	154:37f96f9d4de2	2344	#endif /* RCC */
<>	154:37f96f9d4de2	2345
<>	154:37f96f9d4de2	2346	/**
<>	154:37f96f9d4de2	2347	* @}
<>	154:37f96f9d4de2	2348	*/
<>	154:37f96f9d4de2	2349
<>	154:37f96f9d4de2	2350	#ifdef __cplusplus
<>	154:37f96f9d4de2	2351	}
<>	154:37f96f9d4de2	2352	#endif
<>	154:37f96f9d4de2	2353
<>	154:37f96f9d4de2	2354	#endif /* __STM32F1xx_LL_RCC_H */
<>	154:37f96f9d4de2	2355
<>	154:37f96f9d4de2	2356	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	03 Jul 2017
Imports:	5
Forks:	0
Commits:	168
Dependents:	0
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Followers:	1

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_rcc.h@154:37f96f9d4de2, 2017-01-04 (annotated)

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