Kevin Kadooka / mbed-dev

Fork of mbed-dev build 137, last build before FAT file system appears to be broken. Also reduced HSE timeout time in STM4XX HAL

Fork of mbed-dev by mbed official

targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/hal/TARGET_Freescale/TARGET_KLXX/us_ticker.c@144:ef7eb2e8f9f7
Child:
162:e13f6fdb2ac4
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include <stddef.h>
<> 144:ef7eb2e8f9f7 17 #include "us_ticker_api.h"
<> 144:ef7eb2e8f9f7 18 #include "PeripheralNames.h"
<> 144:ef7eb2e8f9f7 19 #include "clk_freqs.h"
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 static void pit_init(void);
<> 144:ef7eb2e8f9f7 22 static void lptmr_init(void);
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 static int us_ticker_inited = 0;
<> 144:ef7eb2e8f9f7 25
<> 144:ef7eb2e8f9f7 26 void us_ticker_init(void) {
<> 144:ef7eb2e8f9f7 27 if (us_ticker_inited) return;
<> 144:ef7eb2e8f9f7 28 us_ticker_inited = 1;
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 pit_init();
<> 144:ef7eb2e8f9f7 31 lptmr_init();
<> 144:ef7eb2e8f9f7 32 }
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 /******************************************************************************
<> 144:ef7eb2e8f9f7 35 * Timer for us timing.
<> 144:ef7eb2e8f9f7 36 ******************************************************************************/
<> 144:ef7eb2e8f9f7 37 static void pit_init(void) {
<> 144:ef7eb2e8f9f7 38 SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
<> 144:ef7eb2e8f9f7 39 PIT->MCR = 0; // Enable PIT
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 // Channel 1
<> 144:ef7eb2e8f9f7 42 PIT->CHANNEL[1].LDVAL = 0xFFFFFFFF;
<> 144:ef7eb2e8f9f7 43 PIT->CHANNEL[1].TCTRL = PIT_TCTRL_CHN_MASK; // Chain to timer 0, disable Interrupts
<> 144:ef7eb2e8f9f7 44 PIT->CHANNEL[1].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 // Use channel 0 as a prescaler for channel 1
<> 144:ef7eb2e8f9f7 47 PIT->CHANNEL[0].LDVAL = (bus_frequency() + 500000) / 1000000 - 1;
<> 144:ef7eb2e8f9f7 48 PIT->CHANNEL[0].TCTRL = PIT_TCTRL_TEN_MASK; // Start timer 0, disable interrupts
<> 144:ef7eb2e8f9f7 49 }
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 uint32_t us_ticker_read() {
<> 144:ef7eb2e8f9f7 52 if (!us_ticker_inited)
<> 144:ef7eb2e8f9f7 53 us_ticker_init();
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 // The PIT is a countdown timer
<> 144:ef7eb2e8f9f7 56 return ~(PIT->CHANNEL[1].CVAL);
<> 144:ef7eb2e8f9f7 57 }
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 /******************************************************************************
<> 144:ef7eb2e8f9f7 60 * Timer Event
<> 144:ef7eb2e8f9f7 61 *
<> 144:ef7eb2e8f9f7 62 * It schedules interrupts at given (32bit)us interval of time.
<> 144:ef7eb2e8f9f7 63 * It is implemented used the 16bit Low Power Timer that remains powered in all
<> 144:ef7eb2e8f9f7 64 * power modes.
<> 144:ef7eb2e8f9f7 65 ******************************************************************************/
<> 144:ef7eb2e8f9f7 66 static void lptmr_isr(void);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 static void lptmr_init(void) {
<> 144:ef7eb2e8f9f7 69 uint32_t extosc;
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /* Clock the timer */
<> 144:ef7eb2e8f9f7 72 SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 /* Reset */
<> 144:ef7eb2e8f9f7 75 LPTMR0->CSR = 0;
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #if defined(TARGET_KL43Z)
<> 144:ef7eb2e8f9f7 78 /* Set interrupt handler */
<> 144:ef7eb2e8f9f7 79 NVIC_SetVector(LPTMR0_IRQn, (uint32_t)lptmr_isr);
<> 144:ef7eb2e8f9f7 80 NVIC_EnableIRQ(LPTMR0_IRQn);
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 MCG->C1 |= MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 84 extosc = mcgirc_frequency();
<> 144:ef7eb2e8f9f7 85 #else
<> 144:ef7eb2e8f9f7 86 /* Set interrupt handler */
<> 144:ef7eb2e8f9f7 87 NVIC_SetVector(LPTimer_IRQn, (uint32_t)lptmr_isr);
<> 144:ef7eb2e8f9f7 88 NVIC_EnableIRQ(LPTimer_IRQn);
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 /* Clock at (1)MHz -> (1)tick/us */
<> 144:ef7eb2e8f9f7 91 /* Check if the external oscillator can be divided to 1MHz */
<> 144:ef7eb2e8f9f7 92 extosc = extosc_frequency();
<> 144:ef7eb2e8f9f7 93 #endif
<> 144:ef7eb2e8f9f7 94 if (extosc != 0) { //If external oscillator found
<> 144:ef7eb2e8f9f7 95 if (extosc % 1000000u == 0) { //If it is a multiple if 1MHz
<> 144:ef7eb2e8f9f7 96 extosc /= 1000000;
<> 144:ef7eb2e8f9f7 97 if (extosc == 1) { //1MHz, set timerprescaler in bypass mode
<> 144:ef7eb2e8f9f7 98 LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PBYP_MASK;
<> 144:ef7eb2e8f9f7 99 return;
<> 144:ef7eb2e8f9f7 100 } else { //See if we can divide it to 1MHz
<> 144:ef7eb2e8f9f7 101 uint32_t divider = 0;
<> 144:ef7eb2e8f9f7 102 extosc >>= 1;
<> 144:ef7eb2e8f9f7 103 while (1) {
<> 144:ef7eb2e8f9f7 104 if (extosc == 1) {
<> 144:ef7eb2e8f9f7 105 LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PRESCALE(divider);
<> 144:ef7eb2e8f9f7 106 return;
<> 144:ef7eb2e8f9f7 107 }
<> 144:ef7eb2e8f9f7 108 if (extosc % 2 != 0) //If we can't divide by two anymore
<> 144:ef7eb2e8f9f7 109 break;
<> 144:ef7eb2e8f9f7 110 divider++;
<> 144:ef7eb2e8f9f7 111 extosc >>= 1;
<> 144:ef7eb2e8f9f7 112 }
<> 144:ef7eb2e8f9f7 113 }
<> 144:ef7eb2e8f9f7 114 }
<> 144:ef7eb2e8f9f7 115 }
<> 144:ef7eb2e8f9f7 116 #if defined(TARGET_KL43Z)
<> 144:ef7eb2e8f9f7 117 //No suitable actual IRC oscillator clock -> Set it to (8MHz / divider)
<> 144:ef7eb2e8f9f7 118 MCG->SC &= ~MCG_SC_FCRDIV_MASK;
<> 144:ef7eb2e8f9f7 119 MCG->MC &= ~MCG->MC & MCG_MC_LIRC_DIV2_MASK;
<> 144:ef7eb2e8f9f7 120 LPTMR0->PSR = LPTMR_PSR_PCS(0) | LPTMR_PSR_PRESCALE(2);
<> 144:ef7eb2e8f9f7 121 #else
<> 144:ef7eb2e8f9f7 122 //No suitable external oscillator clock -> Use fast internal oscillator (4MHz / divider)
<> 144:ef7eb2e8f9f7 123 MCG->C1 |= MCG_C1_IRCLKEN_MASK;
<> 144:ef7eb2e8f9f7 124 MCG->C2 |= MCG_C2_IRCS_MASK;
<> 144:ef7eb2e8f9f7 125 LPTMR0->PSR = LPTMR_PSR_PCS(0);
<> 144:ef7eb2e8f9f7 126 switch (MCG->SC & MCG_SC_FCRDIV_MASK) {
<> 144:ef7eb2e8f9f7 127 case MCG_SC_FCRDIV(0): //4MHz
<> 144:ef7eb2e8f9f7 128 LPTMR0->PSR |= LPTMR_PSR_PRESCALE(1);
<> 144:ef7eb2e8f9f7 129 break;
<> 144:ef7eb2e8f9f7 130 case MCG_SC_FCRDIV(1): //2MHz
<> 144:ef7eb2e8f9f7 131 LPTMR0->PSR |= LPTMR_PSR_PRESCALE(0);
<> 144:ef7eb2e8f9f7 132 break;
<> 144:ef7eb2e8f9f7 133 default: //1MHz or anything else, in which case we put it on 1MHz
<> 144:ef7eb2e8f9f7 134 MCG->SC &= ~MCG_SC_FCRDIV_MASK;
<> 144:ef7eb2e8f9f7 135 MCG->SC |= MCG_SC_FCRDIV(2);
<> 144:ef7eb2e8f9f7 136 LPTMR0->PSR |= LPTMR_PSR_PBYP_MASK;
<> 144:ef7eb2e8f9f7 137 }
<> 144:ef7eb2e8f9f7 138 #endif
<> 144:ef7eb2e8f9f7 139 }
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 void us_ticker_disable_interrupt(void) {
<> 144:ef7eb2e8f9f7 142 LPTMR0->CSR &= ~LPTMR_CSR_TIE_MASK;
<> 144:ef7eb2e8f9f7 143 }
<> 144:ef7eb2e8f9f7 144
<> 144:ef7eb2e8f9f7 145 void us_ticker_clear_interrupt(void) {
<> 144:ef7eb2e8f9f7 146 // we already clear interrupt in lptmr_isr
<> 144:ef7eb2e8f9f7 147 }
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 static uint32_t us_ticker_int_counter = 0;
<> 144:ef7eb2e8f9f7 150 static uint16_t us_ticker_int_remainder = 0;
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 static void lptmr_set(unsigned short count) {
<> 144:ef7eb2e8f9f7 153 /* Reset */
<> 144:ef7eb2e8f9f7 154 LPTMR0->CSR = 0;
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /* Set the compare register */
<> 144:ef7eb2e8f9f7 157 LPTMR0->CMR = count;
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 /* Enable interrupt */
<> 144:ef7eb2e8f9f7 160 LPTMR0->CSR |= LPTMR_CSR_TIE_MASK;
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 /* Start the timer */
<> 144:ef7eb2e8f9f7 163 LPTMR0->CSR |= LPTMR_CSR_TEN_MASK;
<> 144:ef7eb2e8f9f7 164 }
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 static void lptmr_isr(void) {
<> 144:ef7eb2e8f9f7 167 // write 1 to TCF to clear the LPT timer compare flag
<> 144:ef7eb2e8f9f7 168 LPTMR0->CSR |= LPTMR_CSR_TCF_MASK;
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 if (us_ticker_int_counter > 0) {
<> 144:ef7eb2e8f9f7 171 lptmr_set(0xFFFF);
<> 144:ef7eb2e8f9f7 172 us_ticker_int_counter--;
<> 144:ef7eb2e8f9f7 173
<> 144:ef7eb2e8f9f7 174 } else {
<> 144:ef7eb2e8f9f7 175 if (us_ticker_int_remainder > 0) {
<> 144:ef7eb2e8f9f7 176 lptmr_set(us_ticker_int_remainder);
<> 144:ef7eb2e8f9f7 177 us_ticker_int_remainder = 0;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 } else {
<> 144:ef7eb2e8f9f7 180 // This function is going to disable the interrupts if there are
<> 144:ef7eb2e8f9f7 181 // no other events in the queue
<> 144:ef7eb2e8f9f7 182 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 183 }
<> 144:ef7eb2e8f9f7 184 }
<> 144:ef7eb2e8f9f7 185 }
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 void us_ticker_set_interrupt(timestamp_t timestamp) {
<> 144:ef7eb2e8f9f7 188 int delta = (int)((uint32_t)timestamp - us_ticker_read());
<> 144:ef7eb2e8f9f7 189 if (delta <= 0) {
<> 144:ef7eb2e8f9f7 190 // This event was in the past:
<> 144:ef7eb2e8f9f7 191 us_ticker_irq_handler();
<> 144:ef7eb2e8f9f7 192 return;
<> 144:ef7eb2e8f9f7 193 }
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195 us_ticker_int_counter = (uint32_t)(delta >> 16);
<> 144:ef7eb2e8f9f7 196 us_ticker_int_remainder = (uint16_t)(0xFFFF & delta);
<> 144:ef7eb2e8f9f7 197 if (us_ticker_int_counter > 0) {
<> 144:ef7eb2e8f9f7 198 lptmr_set(0xFFFF);
<> 144:ef7eb2e8f9f7 199 us_ticker_int_counter--;
<> 144:ef7eb2e8f9f7 200 } else {
<> 144:ef7eb2e8f9f7 201 lptmr_set(us_ticker_int_remainder);
<> 144:ef7eb2e8f9f7 202 us_ticker_int_remainder = 0;
<> 144:ef7eb2e8f9f7 203 }
<> 144:ef7eb2e8f9f7 204 }