Kevin Kadooka / mbed-dev

Fork of mbed-dev build 137, last build before FAT file system appears to be broken. Also reduced HSE timeout time in STM4XX HAL

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32625/mxc/gpio.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /**
<> 150:02e0a0aed4ec 2 * @file gpio.h
<> 150:02e0a0aed4ec 3 * @brief General-Purpose Input/Output (GPIO) function prototypes and data types.
<> 150:02e0a0aed4ec 4 */
<> 150:02e0a0aed4ec 5
<> 150:02e0a0aed4ec 6 /* ****************************************************************************
<> 150:02e0a0aed4ec 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 8 *
<> 150:02e0a0aed4ec 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 10 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 11 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 14 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 15 *
<> 150:02e0a0aed4ec 16 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 17 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 18 *
<> 150:02e0a0aed4ec 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 26 *
<> 150:02e0a0aed4ec 27 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 29 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 30 *
<> 150:02e0a0aed4ec 31 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 33 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 35 * ownership rights.
<> 150:02e0a0aed4ec 36 *
<> 150:02e0a0aed4ec 37 * $Date: 2016-08-15 20:04:11 -0500 (Mon, 15 Aug 2016) $
<> 150:02e0a0aed4ec 38 * $Revision: 24085 $
<> 150:02e0a0aed4ec 39 *
<> 150:02e0a0aed4ec 40 *************************************************************************** */
<> 150:02e0a0aed4ec 41
<> 150:02e0a0aed4ec 42 /* Define to prevent redundant inclusion */
<> 150:02e0a0aed4ec 43 #ifndef _GPIO_H_
<> 150:02e0a0aed4ec 44 #define _GPIO_H_
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 /* **** Includes **** */
<> 150:02e0a0aed4ec 47 #include "mxc_config.h"
<> 150:02e0a0aed4ec 48 #include "gpio_regs.h"
<> 150:02e0a0aed4ec 49
<> 150:02e0a0aed4ec 50 #ifdef __cplusplus
<> 150:02e0a0aed4ec 51 extern "C" {
<> 150:02e0a0aed4ec 52 #endif
<> 150:02e0a0aed4ec 53
<> 150:02e0a0aed4ec 54 // Doxy group definition for this peripheral module
<> 150:02e0a0aed4ec 55 /**
<> 150:02e0a0aed4ec 56 * @defgroup gpio General-Purpose Input/Output (GPIO)
<> 150:02e0a0aed4ec 57 * @ingroup periphlibs
<> 150:02e0a0aed4ec 58 * @{
<> 150:02e0a0aed4ec 59 */
<> 150:02e0a0aed4ec 60
<> 150:02e0a0aed4ec 61 /* **** Definitions **** */
<> 150:02e0a0aed4ec 62 /**
<> 150:02e0a0aed4ec 63 * @defgroup gpio_port_pin Port and Pin Definitions
<> 150:02e0a0aed4ec 64 * @ingroup gpio
<> 150:02e0a0aed4ec 65 * @{
<> 150:02e0a0aed4ec 66 * @defgroup gpio_port Port Definitions
<> 150:02e0a0aed4ec 67 * @ingroup gpio_port_pin
<> 150:02e0a0aed4ec 68 * @{
<> 150:02e0a0aed4ec 69 */
<> 150:02e0a0aed4ec 70 #define PORT_0 (0) /**< Port 0 Define*/
<> 150:02e0a0aed4ec 71 #define PORT_1 (1) /**< Port 1 Define*/
<> 150:02e0a0aed4ec 72 #define PORT_2 (2) /**< Port 2 Define*/
<> 150:02e0a0aed4ec 73 #define PORT_3 (3) /**< Port 3 Define*/
<> 150:02e0a0aed4ec 74 #define PORT_4 (4) /**< Port 4 Define*/
<> 150:02e0a0aed4ec 75 #define PORT_5 (5) /**< Port 5 Define*/
<> 150:02e0a0aed4ec 76 #define PORT_6 (6) /**< Port 6 Define*/
<> 150:02e0a0aed4ec 77 #define PORT_7 (7) /**< Port 7 Define*/
<> 150:02e0a0aed4ec 78 #define PORT_8 (8) /**< Port 8 Define*/
<> 150:02e0a0aed4ec 79 #define PORT_9 (9) /**< Port 9 Define*/
<> 150:02e0a0aed4ec 80 #define PORT_10 (10) /**< Port 10 Define*/
<> 150:02e0a0aed4ec 81 #define PORT_11 (11) /**< Port 11 Define*/
<> 150:02e0a0aed4ec 82 #define PORT_12 (12) /**< Port 12 Define*/
<> 150:02e0a0aed4ec 83 #define PORT_13 (13) /**< Port 13 Define*/
<> 150:02e0a0aed4ec 84 #define PORT_14 (14) /**< Port 14 Define*/
<> 150:02e0a0aed4ec 85 #define PORT_15 (15) /**< Port 15 Define*/
<> 150:02e0a0aed4ec 86 /**@} end of gpio_port group*/
<> 150:02e0a0aed4ec 87 /**
<> 150:02e0a0aed4ec 88 * @defgroup gpio_pin Pin Definitions
<> 150:02e0a0aed4ec 89 * @ingroup gpio_port_pin
<> 150:02e0a0aed4ec 90 * @{
<> 150:02e0a0aed4ec 91 */
<> 150:02e0a0aed4ec 92 #define PIN_0 (1 << 0) /**< Pin 0 Define */
<> 150:02e0a0aed4ec 93 #define PIN_1 (1 << 1) /**< Pin 1 Define */
<> 150:02e0a0aed4ec 94 #define PIN_2 (1 << 2) /**< Pin 2 Define */
<> 150:02e0a0aed4ec 95 #define PIN_3 (1 << 3) /**< Pin 3 Define */
<> 150:02e0a0aed4ec 96 #define PIN_4 (1 << 4) /**< Pin 4 Define */
<> 150:02e0a0aed4ec 97 #define PIN_5 (1 << 5) /**< Pin 5 Define */
<> 150:02e0a0aed4ec 98 #define PIN_6 (1 << 6) /**< Pin 6 Define */
<> 150:02e0a0aed4ec 99 #define PIN_7 (1 << 7) /**< Pin 7 Define */
<> 150:02e0a0aed4ec 100 /**@} end of gpio_pin group */
<> 150:02e0a0aed4ec 101 /**@} end of gpio_port_pin group */
<> 150:02e0a0aed4ec 102
<> 150:02e0a0aed4ec 103 /**
<> 150:02e0a0aed4ec 104 * Enumeration type for the GPIO Function Type
<> 150:02e0a0aed4ec 105 */
<> 150:02e0a0aed4ec 106 typedef enum {
<> 150:02e0a0aed4ec 107 GPIO_FUNC_GPIO = MXC_V_GPIO_FUNC_SEL_MODE_GPIO, /**< GPIO Function Selection */
<> 150:02e0a0aed4ec 108 GPIO_FUNC_PT = MXC_V_GPIO_FUNC_SEL_MODE_PT, /**< Pulse Train Function Selection */
<> 150:02e0a0aed4ec 109 GPIO_FUNC_TMR = MXC_V_GPIO_FUNC_SEL_MODE_TMR /**< Timer Function Selection */
<> 150:02e0a0aed4ec 110 }
<> 150:02e0a0aed4ec 111 gpio_func_t;
<> 150:02e0a0aed4ec 112
<> 150:02e0a0aed4ec 113 /**
<> 150:02e0a0aed4ec 114 * Enumeration type for the type of GPIO pad on a given pin.
<> 150:02e0a0aed4ec 115 */
<> 150:02e0a0aed4ec 116 typedef enum {
<> 150:02e0a0aed4ec 117 GPIO_PAD_INPUT_PULLUP = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP, /**< Set pad to high impedance, weak pull-up */
<> 150:02e0a0aed4ec 118 GPIO_PAD_OPEN_DRAIN = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN, /**< Set pad to open-drain with high impedance with input buffer */
<> 150:02e0a0aed4ec 119 GPIO_PAD_OPEN_DRAIN_PULLUP = MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP, /**< Set pad to open-drain with weak pull-up */
<> 150:02e0a0aed4ec 120 GPIO_PAD_INPUT = MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z, /**< Set pad to high impednace, input buffer enabled */
<> 150:02e0a0aed4ec 121 GPIO_PAD_NORMAL = MXC_V_GPIO_OUT_MODE_NORMAL, /**< Set pad to normal drive mode for high an low output */
<> 150:02e0a0aed4ec 122 GPIO_PAD_SLOW = MXC_V_GPIO_OUT_MODE_SLOW_DRIVE, /**< Set pad to slow drive mode, which is normal mode with negative feedback to slow edge transitions */
<> 150:02e0a0aed4ec 123 GPIO_PAD_FAST = MXC_V_GPIO_OUT_MODE_FAST_DRIVE, /**< Set pad to fash drive mode, which is normal mode with a transistor drive to drive fast high and low */
<> 150:02e0a0aed4ec 124 GPIO_PAD_INPUT_PULLDOWN = MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN, /**< Set pad to weak pulldown mode */
<> 150:02e0a0aed4ec 125 GPIO_PAD_OPEN_SOURCE = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE, /**< Set pad to open source mode, transistor drive to high */
<> 150:02e0a0aed4ec 126 GPIO_PAD_OPEN_SOURCE_PULLDOWN = MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN /**< Set pad to open source with weak pulldown mode, transistor drive to high, weak pulldown to GND for low */
<> 150:02e0a0aed4ec 127 } gpio_pad_t;
<> 150:02e0a0aed4ec 128
<> 150:02e0a0aed4ec 129 /**
<> 150:02e0a0aed4ec 130 * Structure type for configuring a GPIO port.
<> 150:02e0a0aed4ec 131 */
<> 150:02e0a0aed4ec 132 typedef struct {
<> 150:02e0a0aed4ec 133 uint32_t port; /// Index of GPIO port
<> 150:02e0a0aed4ec 134 uint32_t mask; /// Pin mask. Multiple bits can be set.
<> 150:02e0a0aed4ec 135 gpio_func_t func; /// Function type
<> 150:02e0a0aed4ec 136 gpio_pad_t pad; /// Pad type
<> 150:02e0a0aed4ec 137 } gpio_cfg_t;
<> 150:02e0a0aed4ec 138
<> 150:02e0a0aed4ec 139 /**
<> 150:02e0a0aed4ec 140 * Enumeration type for the interrupt type on a GPIO port.
<> 150:02e0a0aed4ec 141 */
<> 150:02e0a0aed4ec 142 typedef enum {
<> 150:02e0a0aed4ec 143 GPIO_INT_DISABLE = MXC_V_GPIO_INT_MODE_DISABLE, /**< Disable interrupts */
<> 150:02e0a0aed4ec 144 GPIO_INT_FALLING_EDGE = MXC_V_GPIO_INT_MODE_FALLING_EDGE, /**< Interrupt on Falling Edge */
<> 150:02e0a0aed4ec 145 GPIO_INT_RISING_EDGE = MXC_V_GPIO_INT_MODE_RISING_EDGE, /**< Interrupt on Rising Edge */
<> 150:02e0a0aed4ec 146 GPIO_INT_ANY_EDGE = MXC_V_GPIO_INT_MODE_ANY_EDGE, /**< Interrupt on Falling or Rising Edge */
<> 150:02e0a0aed4ec 147 GPIO_INT_LOW_LEVEL = MXC_V_GPIO_INT_MODE_LOW_LVL, /**< Interrupt on a low level input detection */
<> 150:02e0a0aed4ec 148 GPIO_INT_HIGH_LEVEL = MXC_V_GPIO_INT_MODE_HIGH_LVL /**< Interrupt on a high level input detection */
<> 150:02e0a0aed4ec 149 } gpio_int_mode_t;
<> 150:02e0a0aed4ec 150
<> 150:02e0a0aed4ec 151 /* **** Function Prototypes **** */
<> 150:02e0a0aed4ec 152
<> 150:02e0a0aed4ec 153 /**
<> 150:02e0a0aed4ec 154 * @brief Configure GPIO pin(s).
<> 150:02e0a0aed4ec 155 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 156 *
<> 150:02e0a0aed4ec 157 * @return #E_NO_ERROR if everything is successful.
<> 150:02e0a0aed4ec 158 *
<> 150:02e0a0aed4ec 159 */
<> 150:02e0a0aed4ec 160 int GPIO_Config(const gpio_cfg_t *cfg);
<> 150:02e0a0aed4ec 161
<> 150:02e0a0aed4ec 162 /**
<> 150:02e0a0aed4ec 163 * @brief Gets the pin(s) input state.
<> 150:02e0a0aed4ec 164 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 165 *
<> 150:02e0a0aed4ec 166 * @return The requested pin state.
<> 150:02e0a0aed4ec 167 *
<> 150:02e0a0aed4ec 168 */
<> 150:02e0a0aed4ec 169 __STATIC_INLINE uint32_t GPIO_InGet(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 170 {
<> 150:02e0a0aed4ec 171 return (MXC_GPIO->in_val[cfg->port] & cfg->mask);
<> 150:02e0a0aed4ec 172 }
<> 150:02e0a0aed4ec 173
<> 150:02e0a0aed4ec 174 /**
<> 150:02e0a0aed4ec 175 * @brief Sets the pin(s) to a high level output.
<> 150:02e0a0aed4ec 176 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 177 *
<> 150:02e0a0aed4ec 178 */
<> 150:02e0a0aed4ec 179 __STATIC_INLINE void GPIO_OutSet(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 180 {
<> 150:02e0a0aed4ec 181 MXC_GPIO->out_val[cfg->port] |= cfg->mask;
<> 150:02e0a0aed4ec 182 }
<> 150:02e0a0aed4ec 183
<> 150:02e0a0aed4ec 184 /**
<> 150:02e0a0aed4ec 185 * @brief Clears the pin(s) to a low level output.
<> 150:02e0a0aed4ec 186 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 187 *
<> 150:02e0a0aed4ec 188 */
<> 150:02e0a0aed4ec 189 __STATIC_INLINE void GPIO_OutClr(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 190 {
<> 150:02e0a0aed4ec 191 MXC_GPIO->out_val[cfg->port] &= ~(cfg->mask);
<> 150:02e0a0aed4ec 192 }
<> 150:02e0a0aed4ec 193
<> 150:02e0a0aed4ec 194 /**
<> 150:02e0a0aed4ec 195 * @brief Gets the pin(s) output state.
<> 150:02e0a0aed4ec 196 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 197 *
<> 150:02e0a0aed4ec 198 * @return The state of the requested pin.
<> 150:02e0a0aed4ec 199 *
<> 150:02e0a0aed4ec 200 */
<> 150:02e0a0aed4ec 201 __STATIC_INLINE uint32_t GPIO_OutGet(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 202 {
<> 150:02e0a0aed4ec 203 return (MXC_GPIO->out_val[cfg->port] & cfg->mask);
<> 150:02e0a0aed4ec 204 }
<> 150:02e0a0aed4ec 205
<> 150:02e0a0aed4ec 206 /**
<> 150:02e0a0aed4ec 207 * @brief Write the pin(s) to a desired output level.
<> 150:02e0a0aed4ec 208 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 209 * @param val Desired output level of the pin(s). This will be masked
<> 150:02e0a0aed4ec 210 * with the configuration mask.
<> 150:02e0a0aed4ec 211 *
<> 150:02e0a0aed4ec 212 */
<> 150:02e0a0aed4ec 213 __STATIC_INLINE void GPIO_OutPut(const gpio_cfg_t *cfg, uint32_t val)
<> 150:02e0a0aed4ec 214 {
<> 150:02e0a0aed4ec 215 MXC_GPIO->out_val[cfg->port] = (MXC_GPIO->out_val[cfg->port] & ~cfg->mask) | (val & cfg->mask);
<> 150:02e0a0aed4ec 216 }
<> 150:02e0a0aed4ec 217
<> 150:02e0a0aed4ec 218 /**
<> 150:02e0a0aed4ec 219 * @brief Toggles the the pin(s) output level.
<> 150:02e0a0aed4ec 220 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 221 *
<> 150:02e0a0aed4ec 222 */
<> 150:02e0a0aed4ec 223 __STATIC_INLINE void GPIO_OutToggle(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 224 {
<> 150:02e0a0aed4ec 225 MXC_GPIO->out_val[cfg->port] ^= cfg->mask;
<> 150:02e0a0aed4ec 226 }
<> 150:02e0a0aed4ec 227
<> 150:02e0a0aed4ec 228 /**
<> 150:02e0a0aed4ec 229 * @brief Configure GPIO interrupt(s)
<> 150:02e0a0aed4ec 230 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 231 * @param mode Requested interrupt mode.
<> 150:02e0a0aed4ec 232 *
<> 150:02e0a0aed4ec 233 */
<> 150:02e0a0aed4ec 234 void GPIO_IntConfig(const gpio_cfg_t *cfg, gpio_int_mode_t mode);
<> 150:02e0a0aed4ec 235
<> 150:02e0a0aed4ec 236 /**
<> 150:02e0a0aed4ec 237 * @brief Enables the specified GPIO interrupt
<> 150:02e0a0aed4ec 238 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 239 *
<> 150:02e0a0aed4ec 240 */
<> 150:02e0a0aed4ec 241 __STATIC_INLINE void GPIO_IntEnable(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 242 {
<> 150:02e0a0aed4ec 243 MXC_GPIO->inten[cfg->port] |= cfg->mask;
<> 150:02e0a0aed4ec 244 }
<> 150:02e0a0aed4ec 245
<> 150:02e0a0aed4ec 246 /**
<> 150:02e0a0aed4ec 247 * @brief Disables the specified GPIO interrupt.
<> 150:02e0a0aed4ec 248 * @param cfg Pointer to configuration structure describing the pin.
<> 150:02e0a0aed4ec 249 *
<> 150:02e0a0aed4ec 250 */
<> 150:02e0a0aed4ec 251 __STATIC_INLINE void GPIO_IntDisable(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 252 {
<> 150:02e0a0aed4ec 253 MXC_GPIO->inten[cfg->port] &= ~cfg->mask;
<> 150:02e0a0aed4ec 254 }
<> 150:02e0a0aed4ec 255
<> 150:02e0a0aed4ec 256 /**
<> 150:02e0a0aed4ec 257 * @brief Gets the interrupt(s) status on a GPIO pin.
<> 150:02e0a0aed4ec 258 * @param cfg Pointer to configuration structure describing the pin
<> 150:02e0a0aed4ec 259 * for which the status is being requested.
<> 150:02e0a0aed4ec 260 *
<> 150:02e0a0aed4ec 261 * @return The requested interrupt status.
<> 150:02e0a0aed4ec 262 *
<> 150:02e0a0aed4ec 263 */
<> 150:02e0a0aed4ec 264 __STATIC_INLINE uint32_t GPIO_IntStatus(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 265 {
<> 150:02e0a0aed4ec 266 return (MXC_GPIO->intfl[cfg->port] & cfg->mask);
<> 150:02e0a0aed4ec 267 }
<> 150:02e0a0aed4ec 268
<> 150:02e0a0aed4ec 269 /**
<> 150:02e0a0aed4ec 270 * @brief Clears the interrupt(s) status on a GPIO pin.
<> 150:02e0a0aed4ec 271 * @param cfg Pointer to configuration structure describing the pin
<> 150:02e0a0aed4ec 272 * to clear the interrupt state of.
<> 150:02e0a0aed4ec 273 *
<> 150:02e0a0aed4ec 274 */
<> 150:02e0a0aed4ec 275 __STATIC_INLINE void GPIO_IntClr(const gpio_cfg_t *cfg)
<> 150:02e0a0aed4ec 276 {
<> 150:02e0a0aed4ec 277 MXC_GPIO->intfl[cfg->port] = cfg->mask;
<> 150:02e0a0aed4ec 278 }
<> 150:02e0a0aed4ec 279
<> 150:02e0a0aed4ec 280 /**
<> 150:02e0a0aed4ec 281 * @brief Type alias for a GPIO callback function with prototype:
<> 150:02e0a0aed4ec 282 * @code
<> 150:02e0a0aed4ec 283 * void callback_fn(void *cbdata);
<> 150:02e0a0aed4ec 284 * @endcode
<> 150:02e0a0aed4ec 285 * @param cbdata A void pointer to the data type as registered when
<> 150:02e0a0aed4ec 286 * @c GPIO_RegisterCallback() was called.
<> 150:02e0a0aed4ec 287 *
<> 150:02e0a0aed4ec 288 */
<> 150:02e0a0aed4ec 289 typedef void (*gpio_callback_fn)(void *cbdata);
<> 150:02e0a0aed4ec 290
<> 150:02e0a0aed4ec 291 /**
<> 150:02e0a0aed4ec 292 * @brief Registers a callback for the interrupt on a given port and pin.
<> 150:02e0a0aed4ec 293 * @param cfg Pointer to configuration structure describing the pin
<> 150:02e0a0aed4ec 294 * @param callback A pointer to a function of type #callback_fn.
<> 150:02e0a0aed4ec 295 * @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs.
<> 150:02e0a0aed4ec 296 *
<> 150:02e0a0aed4ec 297 */
<> 150:02e0a0aed4ec 298 void GPIO_RegisterCallback(const gpio_cfg_t *cfg, gpio_callback_fn callback, void *cbdata);
<> 150:02e0a0aed4ec 299
<> 150:02e0a0aed4ec 300 /**
<> 150:02e0a0aed4ec 301 * @brief GPIO IRQ Handler. @note If a callback is registered for a given
<> 150:02e0a0aed4ec 302 * interrupt, the callback function will be called.
<> 150:02e0a0aed4ec 303 *
<> 150:02e0a0aed4ec 304 * @param port number of the port that generated the interrupt service routine.
<> 150:02e0a0aed4ec 305 *
<> 150:02e0a0aed4ec 306 */
<> 150:02e0a0aed4ec 307 void GPIO_Handler(unsigned int port);
<> 150:02e0a0aed4ec 308
<> 150:02e0a0aed4ec 309 /**@} end of group gpio */
<> 150:02e0a0aed4ec 310
<> 150:02e0a0aed4ec 311 #ifdef __cplusplus
<> 150:02e0a0aed4ec 312 }
<> 150:02e0a0aed4ec 313 #endif
<> 150:02e0a0aed4ec 314
<> 150:02e0a0aed4ec 315 #endif /* _GPIO_H_ */