Kev Mann / mbed-dev-OS5_10_4

RTC auf true

rtos/TARGET_CORTEX/TARGET_CORTEX_M/TOOLCHAIN_ARM/except.S@0:38ceb79fef03, 2018-11-28 (annotated)

Committer:
kevman
Date:
Wed Nov 28 15:10:15 2018 +0000
Revision:
0:38ceb79fef03
RTC modified

Who changed what in which revision?

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kevman 0:38ceb79fef03 1 ;/*
kevman 0:38ceb79fef03 2 ; * Copyright (c) 2014-2018 ARM Limited. All rights reserved.
kevman 0:38ceb79fef03 3 ; *
kevman 0:38ceb79fef03 4 ; * SPDX-License-Identifier: Apache-2.0
kevman 0:38ceb79fef03 5 ; *
kevman 0:38ceb79fef03 6 ; * Licensed under the Apache License, Version 2.0 (the License); you may
kevman 0:38ceb79fef03 7 ; * not use this file except in compliance with the License.
kevman 0:38ceb79fef03 8 ; * You may obtain a copy of the License at
kevman 0:38ceb79fef03 9 ; *
kevman 0:38ceb79fef03 10 ; * www.apache.org/licenses/LICENSE-2.0
kevman 0:38ceb79fef03 11 ; *
kevman 0:38ceb79fef03 12 ; * Unless required by applicable law or agreed to in writing, software
kevman 0:38ceb79fef03 13 ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
kevman 0:38ceb79fef03 14 ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kevman 0:38ceb79fef03 15 ; * See the License for the specific language governing permissions and
kevman 0:38ceb79fef03 16 ; * limitations under the License.
kevman 0:38ceb79fef03 17 ; *
kevman 0:38ceb79fef03 18 ; * -----------------------------------------------------------------------------
kevman 0:38ceb79fef03 19 ; *
kevman 0:38ceb79fef03 20 ; * Title: Cortex-M Fault Exception handlers ( Common for both ARMv7M and ARMV6M )
kevman 0:38ceb79fef03 21 ; *
kevman 0:38ceb79fef03 22 ; * -----------------------------------------------------------------------------
kevman 0:38ceb79fef03 23 ; */
kevman 0:38ceb79fef03 24 #ifndef MBED_FAULT_HANDLER_DISABLED
kevman 0:38ceb79fef03 25
kevman 0:38ceb79fef03 26 #ifndef DOMAIN_NS
kevman 0:38ceb79fef03 27 #define DOMAIN_NS 1
kevman 0:38ceb79fef03 28 #endif
kevman 0:38ceb79fef03 29
kevman 0:38ceb79fef03 30 FAULT_TYPE_HARD_FAULT EQU 0x10
kevman 0:38ceb79fef03 31 FAULT_TYPE_MEMMANAGE_FAULT EQU 0x20
kevman 0:38ceb79fef03 32 FAULT_TYPE_BUS_FAULT EQU 0x30
kevman 0:38ceb79fef03 33 FAULT_TYPE_USAGE_FAULT EQU 0x40
kevman 0:38ceb79fef03 34
kevman 0:38ceb79fef03 35 PRESERVE8
kevman 0:38ceb79fef03 36 THUMB
kevman 0:38ceb79fef03 37
kevman 0:38ceb79fef03 38 AREA |.text|, CODE, READONLY
kevman 0:38ceb79fef03 39
kevman 0:38ceb79fef03 40 HardFault_Handler\
kevman 0:38ceb79fef03 41 PROC
kevman 0:38ceb79fef03 42 EXPORT HardFault_Handler
kevman 0:38ceb79fef03 43 LDR R3,=FAULT_TYPE_HARD_FAULT
kevman 0:38ceb79fef03 44 B Fault_Handler
kevman 0:38ceb79fef03 45 ENDP
kevman 0:38ceb79fef03 46
kevman 0:38ceb79fef03 47 MemManage_Handler\
kevman 0:38ceb79fef03 48 PROC
kevman 0:38ceb79fef03 49 EXPORT MemManage_Handler
kevman 0:38ceb79fef03 50 LDR R3,=FAULT_TYPE_MEMMANAGE_FAULT
kevman 0:38ceb79fef03 51 B Fault_Handler
kevman 0:38ceb79fef03 52 ENDP
kevman 0:38ceb79fef03 53
kevman 0:38ceb79fef03 54 BusFault_Handler\
kevman 0:38ceb79fef03 55 PROC
kevman 0:38ceb79fef03 56 EXPORT BusFault_Handler
kevman 0:38ceb79fef03 57 LDR R3,=FAULT_TYPE_BUS_FAULT
kevman 0:38ceb79fef03 58 B Fault_Handler
kevman 0:38ceb79fef03 59 ENDP
kevman 0:38ceb79fef03 60
kevman 0:38ceb79fef03 61 UsageFault_Handler\
kevman 0:38ceb79fef03 62 PROC
kevman 0:38ceb79fef03 63 EXPORT UsageFault_Handler
kevman 0:38ceb79fef03 64 LDR R3,=FAULT_TYPE_USAGE_FAULT
kevman 0:38ceb79fef03 65 B Fault_Handler
kevman 0:38ceb79fef03 66 ENDP
kevman 0:38ceb79fef03 67
kevman 0:38ceb79fef03 68 Fault_Handler PROC
kevman 0:38ceb79fef03 69 EXPORT Fault_Handler
kevman 0:38ceb79fef03 70 #if (DOMAIN_NS == 1)
kevman 0:38ceb79fef03 71 IMPORT osRtxInfo
kevman 0:38ceb79fef03 72 IMPORT mbed_fault_handler
kevman 0:38ceb79fef03 73 IMPORT mbed_fault_context
kevman 0:38ceb79fef03 74
kevman 0:38ceb79fef03 75 MRS R0,MSP
kevman 0:38ceb79fef03 76 LDR R1,=0x4
kevman 0:38ceb79fef03 77 MOV R2,LR
kevman 0:38ceb79fef03 78 TST R2,R1 ; Check EXC_RETURN for bit 2
kevman 0:38ceb79fef03 79 BEQ Fault_Handler_Continue
kevman 0:38ceb79fef03 80 MRS R0,PSP
kevman 0:38ceb79fef03 81
kevman 0:38ceb79fef03 82 Fault_Handler_Continue
kevman 0:38ceb79fef03 83 MOV R12,R3
kevman 0:38ceb79fef03 84 LDR R1,=mbed_fault_context
kevman 0:38ceb79fef03 85 LDR R2,[R0] ; Capture R0
kevman 0:38ceb79fef03 86 STR R2,[R1]
kevman 0:38ceb79fef03 87 ADDS R1,#4
kevman 0:38ceb79fef03 88 LDR R2,[R0,#4] ; Capture R1
kevman 0:38ceb79fef03 89 STR R2,[R1]
kevman 0:38ceb79fef03 90 ADDS R1,#4
kevman 0:38ceb79fef03 91 LDR R2,[R0,#8] ; Capture R2
kevman 0:38ceb79fef03 92 STR R2,[R1]
kevman 0:38ceb79fef03 93 ADDS R1,#4
kevman 0:38ceb79fef03 94 LDR R2,[R0,#12] ; Capture R3
kevman 0:38ceb79fef03 95 STR R2,[R1]
kevman 0:38ceb79fef03 96 ADDS R1,#4
kevman 0:38ceb79fef03 97 STMIA R1!,{R4-R7} ; Capture R4..R7
kevman 0:38ceb79fef03 98 MOV R7,R8 ; Capture R8
kevman 0:38ceb79fef03 99 STR R7,[R1]
kevman 0:38ceb79fef03 100 ADDS R1,#4
kevman 0:38ceb79fef03 101 MOV R7,R9 ; Capture R9
kevman 0:38ceb79fef03 102 STR R7,[R1]
kevman 0:38ceb79fef03 103 ADDS R1,#4
kevman 0:38ceb79fef03 104 MOV R7,R10 ; Capture R10
kevman 0:38ceb79fef03 105 STR R7,[R1]
kevman 0:38ceb79fef03 106 ADDS R1,#4
kevman 0:38ceb79fef03 107 MOV R7,R11 ; Capture R11
kevman 0:38ceb79fef03 108 STR R7,[R1]
kevman 0:38ceb79fef03 109 ADDS R1,#4
kevman 0:38ceb79fef03 110 LDR R2,[R0,#16] ; Capture R12
kevman 0:38ceb79fef03 111 STR R2,[R1]
kevman 0:38ceb79fef03 112 ADDS R1,#8 ; Add 8 here to capture LR next, we will capture SP later
kevman 0:38ceb79fef03 113 LDR R2,[R0,#20] ; Capture LR
kevman 0:38ceb79fef03 114 STR R2,[R1]
kevman 0:38ceb79fef03 115 ADDS R1,#4
kevman 0:38ceb79fef03 116 LDR R2,[R0,#24] ; Capture PC
kevman 0:38ceb79fef03 117 STR R2,[R1]
kevman 0:38ceb79fef03 118 ADDS R1,#4
kevman 0:38ceb79fef03 119 LDR R2,[R0,#28] ; Capture xPSR
kevman 0:38ceb79fef03 120 STR R2,[R1]
kevman 0:38ceb79fef03 121 ADDS R1,#4
kevman 0:38ceb79fef03 122 ; Adjust stack pointer to its original value and capture it
kevman 0:38ceb79fef03 123 MOV R3,R0
kevman 0:38ceb79fef03 124 ADDS R3,#0x20 ; Add 0x20 to get the SP value prior to exception
kevman 0:38ceb79fef03 125 LDR R6,=0x200
kevman 0:38ceb79fef03 126 TST R2,R6 ; Check for if STK was aligned by checking bit-9 in xPSR value
kevman 0:38ceb79fef03 127 BEQ Fault_Handler_Continue1
kevman 0:38ceb79fef03 128 ADDS R3,#0x4
kevman 0:38ceb79fef03 129
kevman 0:38ceb79fef03 130 Fault_Handler_Continue1
kevman 0:38ceb79fef03 131 MOV R5,LR
kevman 0:38ceb79fef03 132 LDR R6,=0x10 ; Check for bit-4 to see if FP context was saved
kevman 0:38ceb79fef03 133 TST R5,R6
kevman 0:38ceb79fef03 134 BNE Fault_Handler_Continue2
kevman 0:38ceb79fef03 135 ADDS R3,#0x48 ; 16 FP regs + FPCSR + 1 Reserved
kevman 0:38ceb79fef03 136
kevman 0:38ceb79fef03 137 Fault_Handler_Continue2
kevman 0:38ceb79fef03 138 MOV R4,R1
kevman 0:38ceb79fef03 139 SUBS R4,#0x10 ; Set the location of SP in ctx
kevman 0:38ceb79fef03 140 STR R3,[R4] ; Capture the adjusted SP
kevman 0:38ceb79fef03 141 MRS R2,PSP ; Get PSP
kevman 0:38ceb79fef03 142 STR R2,[R1]
kevman 0:38ceb79fef03 143 ADDS R1,#4
kevman 0:38ceb79fef03 144 MRS R2,MSP ; Get MSP
kevman 0:38ceb79fef03 145 STR R2,[R1]
kevman 0:38ceb79fef03 146 ADDS R1,#4
kevman 0:38ceb79fef03 147 MOV R2,LR ; Get current LR(EXC_RETURN)
kevman 0:38ceb79fef03 148 STR R2,[R1]
kevman 0:38ceb79fef03 149 ADDS R1,#4
kevman 0:38ceb79fef03 150 MRS R2,CONTROL ; Get CONTROL Reg
kevman 0:38ceb79fef03 151 STR R2,[R1]
kevman 0:38ceb79fef03 152 LDR R3,=mbed_fault_handler ; Load address of mbedFaultHandler
kevman 0:38ceb79fef03 153 MOV R0,R12
kevman 0:38ceb79fef03 154 LDR R1,=mbed_fault_context
kevman 0:38ceb79fef03 155 LDR R2,=osRtxInfo
kevman 0:38ceb79fef03 156 BLX R3
kevman 0:38ceb79fef03 157 #endif
kevman 0:38ceb79fef03 158 B . ; Just in case we come back here
kevman 0:38ceb79fef03 159 ENDP
kevman 0:38ceb79fef03 160
kevman 0:38ceb79fef03 161 #endif
kevman 0:38ceb79fef03 162
kevman 0:38ceb79fef03 163 END