RTC auf true
cmsis/TARGET_CORTEX_M/core_cm23.h@0:38ceb79fef03, 2018-11-28 (annotated)
- Committer:
- kevman
- Date:
- Wed Nov 28 15:10:15 2018 +0000
- Revision:
- 0:38ceb79fef03
RTC modified
Who changed what in which revision?
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kevman | 0:38ceb79fef03 | 1 | /**************************************************************************//** |
kevman | 0:38ceb79fef03 | 2 | * @file core_cm23.h |
kevman | 0:38ceb79fef03 | 3 | * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File |
kevman | 0:38ceb79fef03 | 4 | * @version V5.0.7 |
kevman | 0:38ceb79fef03 | 5 | * @date 22. June 2018 |
kevman | 0:38ceb79fef03 | 6 | ******************************************************************************/ |
kevman | 0:38ceb79fef03 | 7 | /* |
kevman | 0:38ceb79fef03 | 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. |
kevman | 0:38ceb79fef03 | 9 | * |
kevman | 0:38ceb79fef03 | 10 | * SPDX-License-Identifier: Apache-2.0 |
kevman | 0:38ceb79fef03 | 11 | * |
kevman | 0:38ceb79fef03 | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
kevman | 0:38ceb79fef03 | 13 | * not use this file except in compliance with the License. |
kevman | 0:38ceb79fef03 | 14 | * You may obtain a copy of the License at |
kevman | 0:38ceb79fef03 | 15 | * |
kevman | 0:38ceb79fef03 | 16 | * www.apache.org/licenses/LICENSE-2.0 |
kevman | 0:38ceb79fef03 | 17 | * |
kevman | 0:38ceb79fef03 | 18 | * Unless required by applicable law or agreed to in writing, software |
kevman | 0:38ceb79fef03 | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
kevman | 0:38ceb79fef03 | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
kevman | 0:38ceb79fef03 | 21 | * See the License for the specific language governing permissions and |
kevman | 0:38ceb79fef03 | 22 | * limitations under the License. |
kevman | 0:38ceb79fef03 | 23 | */ |
kevman | 0:38ceb79fef03 | 24 | |
kevman | 0:38ceb79fef03 | 25 | #if defined ( __ICCARM__ ) |
kevman | 0:38ceb79fef03 | 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
kevman | 0:38ceb79fef03 | 27 | #elif defined (__clang__) |
kevman | 0:38ceb79fef03 | 28 | #pragma clang system_header /* treat file as system include file */ |
kevman | 0:38ceb79fef03 | 29 | #endif |
kevman | 0:38ceb79fef03 | 30 | |
kevman | 0:38ceb79fef03 | 31 | #ifndef __CORE_CM23_H_GENERIC |
kevman | 0:38ceb79fef03 | 32 | #define __CORE_CM23_H_GENERIC |
kevman | 0:38ceb79fef03 | 33 | |
kevman | 0:38ceb79fef03 | 34 | #include <stdint.h> |
kevman | 0:38ceb79fef03 | 35 | |
kevman | 0:38ceb79fef03 | 36 | #ifdef __cplusplus |
kevman | 0:38ceb79fef03 | 37 | extern "C" { |
kevman | 0:38ceb79fef03 | 38 | #endif |
kevman | 0:38ceb79fef03 | 39 | |
kevman | 0:38ceb79fef03 | 40 | /** |
kevman | 0:38ceb79fef03 | 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
kevman | 0:38ceb79fef03 | 42 | CMSIS violates the following MISRA-C:2004 rules: |
kevman | 0:38ceb79fef03 | 43 | |
kevman | 0:38ceb79fef03 | 44 | \li Required Rule 8.5, object/function definition in header file.<br> |
kevman | 0:38ceb79fef03 | 45 | Function definitions in header files are used to allow 'inlining'. |
kevman | 0:38ceb79fef03 | 46 | |
kevman | 0:38ceb79fef03 | 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
kevman | 0:38ceb79fef03 | 48 | Unions are used for effective representation of core registers. |
kevman | 0:38ceb79fef03 | 49 | |
kevman | 0:38ceb79fef03 | 50 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
kevman | 0:38ceb79fef03 | 51 | Function-like macros are used to allow more efficient code. |
kevman | 0:38ceb79fef03 | 52 | */ |
kevman | 0:38ceb79fef03 | 53 | |
kevman | 0:38ceb79fef03 | 54 | |
kevman | 0:38ceb79fef03 | 55 | /******************************************************************************* |
kevman | 0:38ceb79fef03 | 56 | * CMSIS definitions |
kevman | 0:38ceb79fef03 | 57 | ******************************************************************************/ |
kevman | 0:38ceb79fef03 | 58 | /** |
kevman | 0:38ceb79fef03 | 59 | \ingroup Cortex_M23 |
kevman | 0:38ceb79fef03 | 60 | @{ |
kevman | 0:38ceb79fef03 | 61 | */ |
kevman | 0:38ceb79fef03 | 62 | |
kevman | 0:38ceb79fef03 | 63 | #include "cmsis_version.h" |
kevman | 0:38ceb79fef03 | 64 | |
kevman | 0:38ceb79fef03 | 65 | /* CMSIS definitions */ |
kevman | 0:38ceb79fef03 | 66 | #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ |
kevman | 0:38ceb79fef03 | 67 | #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ |
kevman | 0:38ceb79fef03 | 68 | #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ |
kevman | 0:38ceb79fef03 | 69 | __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ |
kevman | 0:38ceb79fef03 | 70 | |
kevman | 0:38ceb79fef03 | 71 | #define __CORTEX_M (23U) /*!< Cortex-M Core */ |
kevman | 0:38ceb79fef03 | 72 | |
kevman | 0:38ceb79fef03 | 73 | /** __FPU_USED indicates whether an FPU is used or not. |
kevman | 0:38ceb79fef03 | 74 | This core does not support an FPU at all |
kevman | 0:38ceb79fef03 | 75 | */ |
kevman | 0:38ceb79fef03 | 76 | #define __FPU_USED 0U |
kevman | 0:38ceb79fef03 | 77 | |
kevman | 0:38ceb79fef03 | 78 | #if defined ( __CC_ARM ) |
kevman | 0:38ceb79fef03 | 79 | #if defined __TARGET_FPU_VFP |
kevman | 0:38ceb79fef03 | 80 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kevman | 0:38ceb79fef03 | 81 | #endif |
kevman | 0:38ceb79fef03 | 82 | |
kevman | 0:38ceb79fef03 | 83 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
kevman | 0:38ceb79fef03 | 84 | #if defined __ARM_PCS_VFP |
kevman | 0:38ceb79fef03 | 85 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kevman | 0:38ceb79fef03 | 86 | #endif |
kevman | 0:38ceb79fef03 | 87 | |
kevman | 0:38ceb79fef03 | 88 | #elif defined ( __GNUC__ ) |
kevman | 0:38ceb79fef03 | 89 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
kevman | 0:38ceb79fef03 | 90 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kevman | 0:38ceb79fef03 | 91 | #endif |
kevman | 0:38ceb79fef03 | 92 | |
kevman | 0:38ceb79fef03 | 93 | #elif defined ( __ICCARM__ ) |
kevman | 0:38ceb79fef03 | 94 | #if defined __ARMVFP__ |
kevman | 0:38ceb79fef03 | 95 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kevman | 0:38ceb79fef03 | 96 | #endif |
kevman | 0:38ceb79fef03 | 97 | |
kevman | 0:38ceb79fef03 | 98 | #elif defined ( __TI_ARM__ ) |
kevman | 0:38ceb79fef03 | 99 | #if defined __TI_VFP_SUPPORT__ |
kevman | 0:38ceb79fef03 | 100 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kevman | 0:38ceb79fef03 | 101 | #endif |
kevman | 0:38ceb79fef03 | 102 | |
kevman | 0:38ceb79fef03 | 103 | #elif defined ( __TASKING__ ) |
kevman | 0:38ceb79fef03 | 104 | #if defined __FPU_VFP__ |
kevman | 0:38ceb79fef03 | 105 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kevman | 0:38ceb79fef03 | 106 | #endif |
kevman | 0:38ceb79fef03 | 107 | |
kevman | 0:38ceb79fef03 | 108 | #elif defined ( __CSMC__ ) |
kevman | 0:38ceb79fef03 | 109 | #if ( __CSMC__ & 0x400U) |
kevman | 0:38ceb79fef03 | 110 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
kevman | 0:38ceb79fef03 | 111 | #endif |
kevman | 0:38ceb79fef03 | 112 | |
kevman | 0:38ceb79fef03 | 113 | #endif |
kevman | 0:38ceb79fef03 | 114 | |
kevman | 0:38ceb79fef03 | 115 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
kevman | 0:38ceb79fef03 | 116 | |
kevman | 0:38ceb79fef03 | 117 | |
kevman | 0:38ceb79fef03 | 118 | #ifdef __cplusplus |
kevman | 0:38ceb79fef03 | 119 | } |
kevman | 0:38ceb79fef03 | 120 | #endif |
kevman | 0:38ceb79fef03 | 121 | |
kevman | 0:38ceb79fef03 | 122 | #endif /* __CORE_CM23_H_GENERIC */ |
kevman | 0:38ceb79fef03 | 123 | |
kevman | 0:38ceb79fef03 | 124 | #ifndef __CMSIS_GENERIC |
kevman | 0:38ceb79fef03 | 125 | |
kevman | 0:38ceb79fef03 | 126 | #ifndef __CORE_CM23_H_DEPENDANT |
kevman | 0:38ceb79fef03 | 127 | #define __CORE_CM23_H_DEPENDANT |
kevman | 0:38ceb79fef03 | 128 | |
kevman | 0:38ceb79fef03 | 129 | #ifdef __cplusplus |
kevman | 0:38ceb79fef03 | 130 | extern "C" { |
kevman | 0:38ceb79fef03 | 131 | #endif |
kevman | 0:38ceb79fef03 | 132 | |
kevman | 0:38ceb79fef03 | 133 | /* check device defines and use defaults */ |
kevman | 0:38ceb79fef03 | 134 | #if defined __CHECK_DEVICE_DEFINES |
kevman | 0:38ceb79fef03 | 135 | #ifndef __CM23_REV |
kevman | 0:38ceb79fef03 | 136 | #define __CM23_REV 0x0000U |
kevman | 0:38ceb79fef03 | 137 | #warning "__CM23_REV not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 138 | #endif |
kevman | 0:38ceb79fef03 | 139 | |
kevman | 0:38ceb79fef03 | 140 | #ifndef __FPU_PRESENT |
kevman | 0:38ceb79fef03 | 141 | #define __FPU_PRESENT 0U |
kevman | 0:38ceb79fef03 | 142 | #warning "__FPU_PRESENT not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 143 | #endif |
kevman | 0:38ceb79fef03 | 144 | |
kevman | 0:38ceb79fef03 | 145 | #ifndef __MPU_PRESENT |
kevman | 0:38ceb79fef03 | 146 | #define __MPU_PRESENT 0U |
kevman | 0:38ceb79fef03 | 147 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 148 | #endif |
kevman | 0:38ceb79fef03 | 149 | |
kevman | 0:38ceb79fef03 | 150 | #ifndef __SAUREGION_PRESENT |
kevman | 0:38ceb79fef03 | 151 | #define __SAUREGION_PRESENT 0U |
kevman | 0:38ceb79fef03 | 152 | #warning "__SAUREGION_PRESENT not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 153 | #endif |
kevman | 0:38ceb79fef03 | 154 | |
kevman | 0:38ceb79fef03 | 155 | #ifndef __VTOR_PRESENT |
kevman | 0:38ceb79fef03 | 156 | #define __VTOR_PRESENT 0U |
kevman | 0:38ceb79fef03 | 157 | #warning "__VTOR_PRESENT not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 158 | #endif |
kevman | 0:38ceb79fef03 | 159 | |
kevman | 0:38ceb79fef03 | 160 | #ifndef __NVIC_PRIO_BITS |
kevman | 0:38ceb79fef03 | 161 | #define __NVIC_PRIO_BITS 2U |
kevman | 0:38ceb79fef03 | 162 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 163 | #endif |
kevman | 0:38ceb79fef03 | 164 | |
kevman | 0:38ceb79fef03 | 165 | #ifndef __Vendor_SysTickConfig |
kevman | 0:38ceb79fef03 | 166 | #define __Vendor_SysTickConfig 0U |
kevman | 0:38ceb79fef03 | 167 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 168 | #endif |
kevman | 0:38ceb79fef03 | 169 | |
kevman | 0:38ceb79fef03 | 170 | #ifndef __ETM_PRESENT |
kevman | 0:38ceb79fef03 | 171 | #define __ETM_PRESENT 0U |
kevman | 0:38ceb79fef03 | 172 | #warning "__ETM_PRESENT not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 173 | #endif |
kevman | 0:38ceb79fef03 | 174 | |
kevman | 0:38ceb79fef03 | 175 | #ifndef __MTB_PRESENT |
kevman | 0:38ceb79fef03 | 176 | #define __MTB_PRESENT 0U |
kevman | 0:38ceb79fef03 | 177 | #warning "__MTB_PRESENT not defined in device header file; using default!" |
kevman | 0:38ceb79fef03 | 178 | #endif |
kevman | 0:38ceb79fef03 | 179 | |
kevman | 0:38ceb79fef03 | 180 | #endif |
kevman | 0:38ceb79fef03 | 181 | |
kevman | 0:38ceb79fef03 | 182 | /* IO definitions (access restrictions to peripheral registers) */ |
kevman | 0:38ceb79fef03 | 183 | /** |
kevman | 0:38ceb79fef03 | 184 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
kevman | 0:38ceb79fef03 | 185 | |
kevman | 0:38ceb79fef03 | 186 | <strong>IO Type Qualifiers</strong> are used |
kevman | 0:38ceb79fef03 | 187 | \li to specify the access to peripheral variables. |
kevman | 0:38ceb79fef03 | 188 | \li for automatic generation of peripheral register debug information. |
kevman | 0:38ceb79fef03 | 189 | */ |
kevman | 0:38ceb79fef03 | 190 | #ifdef __cplusplus |
kevman | 0:38ceb79fef03 | 191 | #define __I volatile /*!< Defines 'read only' permissions */ |
kevman | 0:38ceb79fef03 | 192 | #else |
kevman | 0:38ceb79fef03 | 193 | #define __I volatile const /*!< Defines 'read only' permissions */ |
kevman | 0:38ceb79fef03 | 194 | #endif |
kevman | 0:38ceb79fef03 | 195 | #define __O volatile /*!< Defines 'write only' permissions */ |
kevman | 0:38ceb79fef03 | 196 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
kevman | 0:38ceb79fef03 | 197 | |
kevman | 0:38ceb79fef03 | 198 | /* following defines should be used for structure members */ |
kevman | 0:38ceb79fef03 | 199 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
kevman | 0:38ceb79fef03 | 200 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
kevman | 0:38ceb79fef03 | 201 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
kevman | 0:38ceb79fef03 | 202 | |
kevman | 0:38ceb79fef03 | 203 | /*@} end of group Cortex_M23 */ |
kevman | 0:38ceb79fef03 | 204 | |
kevman | 0:38ceb79fef03 | 205 | |
kevman | 0:38ceb79fef03 | 206 | |
kevman | 0:38ceb79fef03 | 207 | /******************************************************************************* |
kevman | 0:38ceb79fef03 | 208 | * Register Abstraction |
kevman | 0:38ceb79fef03 | 209 | Core Register contain: |
kevman | 0:38ceb79fef03 | 210 | - Core Register |
kevman | 0:38ceb79fef03 | 211 | - Core NVIC Register |
kevman | 0:38ceb79fef03 | 212 | - Core SCB Register |
kevman | 0:38ceb79fef03 | 213 | - Core SysTick Register |
kevman | 0:38ceb79fef03 | 214 | - Core Debug Register |
kevman | 0:38ceb79fef03 | 215 | - Core MPU Register |
kevman | 0:38ceb79fef03 | 216 | - Core SAU Register |
kevman | 0:38ceb79fef03 | 217 | ******************************************************************************/ |
kevman | 0:38ceb79fef03 | 218 | /** |
kevman | 0:38ceb79fef03 | 219 | \defgroup CMSIS_core_register Defines and Type Definitions |
kevman | 0:38ceb79fef03 | 220 | \brief Type definitions and defines for Cortex-M processor based devices. |
kevman | 0:38ceb79fef03 | 221 | */ |
kevman | 0:38ceb79fef03 | 222 | |
kevman | 0:38ceb79fef03 | 223 | /** |
kevman | 0:38ceb79fef03 | 224 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 225 | \defgroup CMSIS_CORE Status and Control Registers |
kevman | 0:38ceb79fef03 | 226 | \brief Core Register type definitions. |
kevman | 0:38ceb79fef03 | 227 | @{ |
kevman | 0:38ceb79fef03 | 228 | */ |
kevman | 0:38ceb79fef03 | 229 | |
kevman | 0:38ceb79fef03 | 230 | /** |
kevman | 0:38ceb79fef03 | 231 | \brief Union type to access the Application Program Status Register (APSR). |
kevman | 0:38ceb79fef03 | 232 | */ |
kevman | 0:38ceb79fef03 | 233 | typedef union |
kevman | 0:38ceb79fef03 | 234 | { |
kevman | 0:38ceb79fef03 | 235 | struct |
kevman | 0:38ceb79fef03 | 236 | { |
kevman | 0:38ceb79fef03 | 237 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
kevman | 0:38ceb79fef03 | 238 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
kevman | 0:38ceb79fef03 | 239 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
kevman | 0:38ceb79fef03 | 240 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
kevman | 0:38ceb79fef03 | 241 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
kevman | 0:38ceb79fef03 | 242 | } b; /*!< Structure used for bit access */ |
kevman | 0:38ceb79fef03 | 243 | uint32_t w; /*!< Type used for word access */ |
kevman | 0:38ceb79fef03 | 244 | } APSR_Type; |
kevman | 0:38ceb79fef03 | 245 | |
kevman | 0:38ceb79fef03 | 246 | /* APSR Register Definitions */ |
kevman | 0:38ceb79fef03 | 247 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
kevman | 0:38ceb79fef03 | 248 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
kevman | 0:38ceb79fef03 | 249 | |
kevman | 0:38ceb79fef03 | 250 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
kevman | 0:38ceb79fef03 | 251 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
kevman | 0:38ceb79fef03 | 252 | |
kevman | 0:38ceb79fef03 | 253 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
kevman | 0:38ceb79fef03 | 254 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
kevman | 0:38ceb79fef03 | 255 | |
kevman | 0:38ceb79fef03 | 256 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
kevman | 0:38ceb79fef03 | 257 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
kevman | 0:38ceb79fef03 | 258 | |
kevman | 0:38ceb79fef03 | 259 | |
kevman | 0:38ceb79fef03 | 260 | /** |
kevman | 0:38ceb79fef03 | 261 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
kevman | 0:38ceb79fef03 | 262 | */ |
kevman | 0:38ceb79fef03 | 263 | typedef union |
kevman | 0:38ceb79fef03 | 264 | { |
kevman | 0:38ceb79fef03 | 265 | struct |
kevman | 0:38ceb79fef03 | 266 | { |
kevman | 0:38ceb79fef03 | 267 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
kevman | 0:38ceb79fef03 | 268 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
kevman | 0:38ceb79fef03 | 269 | } b; /*!< Structure used for bit access */ |
kevman | 0:38ceb79fef03 | 270 | uint32_t w; /*!< Type used for word access */ |
kevman | 0:38ceb79fef03 | 271 | } IPSR_Type; |
kevman | 0:38ceb79fef03 | 272 | |
kevman | 0:38ceb79fef03 | 273 | /* IPSR Register Definitions */ |
kevman | 0:38ceb79fef03 | 274 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
kevman | 0:38ceb79fef03 | 275 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
kevman | 0:38ceb79fef03 | 276 | |
kevman | 0:38ceb79fef03 | 277 | |
kevman | 0:38ceb79fef03 | 278 | /** |
kevman | 0:38ceb79fef03 | 279 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
kevman | 0:38ceb79fef03 | 280 | */ |
kevman | 0:38ceb79fef03 | 281 | typedef union |
kevman | 0:38ceb79fef03 | 282 | { |
kevman | 0:38ceb79fef03 | 283 | struct |
kevman | 0:38ceb79fef03 | 284 | { |
kevman | 0:38ceb79fef03 | 285 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
kevman | 0:38ceb79fef03 | 286 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
kevman | 0:38ceb79fef03 | 287 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
kevman | 0:38ceb79fef03 | 288 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
kevman | 0:38ceb79fef03 | 289 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
kevman | 0:38ceb79fef03 | 290 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
kevman | 0:38ceb79fef03 | 291 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
kevman | 0:38ceb79fef03 | 292 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
kevman | 0:38ceb79fef03 | 293 | } b; /*!< Structure used for bit access */ |
kevman | 0:38ceb79fef03 | 294 | uint32_t w; /*!< Type used for word access */ |
kevman | 0:38ceb79fef03 | 295 | } xPSR_Type; |
kevman | 0:38ceb79fef03 | 296 | |
kevman | 0:38ceb79fef03 | 297 | /* xPSR Register Definitions */ |
kevman | 0:38ceb79fef03 | 298 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
kevman | 0:38ceb79fef03 | 299 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
kevman | 0:38ceb79fef03 | 300 | |
kevman | 0:38ceb79fef03 | 301 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
kevman | 0:38ceb79fef03 | 302 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
kevman | 0:38ceb79fef03 | 303 | |
kevman | 0:38ceb79fef03 | 304 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
kevman | 0:38ceb79fef03 | 305 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
kevman | 0:38ceb79fef03 | 306 | |
kevman | 0:38ceb79fef03 | 307 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
kevman | 0:38ceb79fef03 | 308 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
kevman | 0:38ceb79fef03 | 309 | |
kevman | 0:38ceb79fef03 | 310 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
kevman | 0:38ceb79fef03 | 311 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
kevman | 0:38ceb79fef03 | 312 | |
kevman | 0:38ceb79fef03 | 313 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
kevman | 0:38ceb79fef03 | 314 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
kevman | 0:38ceb79fef03 | 315 | |
kevman | 0:38ceb79fef03 | 316 | |
kevman | 0:38ceb79fef03 | 317 | /** |
kevman | 0:38ceb79fef03 | 318 | \brief Union type to access the Control Registers (CONTROL). |
kevman | 0:38ceb79fef03 | 319 | */ |
kevman | 0:38ceb79fef03 | 320 | typedef union |
kevman | 0:38ceb79fef03 | 321 | { |
kevman | 0:38ceb79fef03 | 322 | struct |
kevman | 0:38ceb79fef03 | 323 | { |
kevman | 0:38ceb79fef03 | 324 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
kevman | 0:38ceb79fef03 | 325 | uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ |
kevman | 0:38ceb79fef03 | 326 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
kevman | 0:38ceb79fef03 | 327 | } b; /*!< Structure used for bit access */ |
kevman | 0:38ceb79fef03 | 328 | uint32_t w; /*!< Type used for word access */ |
kevman | 0:38ceb79fef03 | 329 | } CONTROL_Type; |
kevman | 0:38ceb79fef03 | 330 | |
kevman | 0:38ceb79fef03 | 331 | /* CONTROL Register Definitions */ |
kevman | 0:38ceb79fef03 | 332 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
kevman | 0:38ceb79fef03 | 333 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
kevman | 0:38ceb79fef03 | 334 | |
kevman | 0:38ceb79fef03 | 335 | #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
kevman | 0:38ceb79fef03 | 336 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
kevman | 0:38ceb79fef03 | 337 | |
kevman | 0:38ceb79fef03 | 338 | /*@} end of group CMSIS_CORE */ |
kevman | 0:38ceb79fef03 | 339 | |
kevman | 0:38ceb79fef03 | 340 | |
kevman | 0:38ceb79fef03 | 341 | /** |
kevman | 0:38ceb79fef03 | 342 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 343 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
kevman | 0:38ceb79fef03 | 344 | \brief Type definitions for the NVIC Registers |
kevman | 0:38ceb79fef03 | 345 | @{ |
kevman | 0:38ceb79fef03 | 346 | */ |
kevman | 0:38ceb79fef03 | 347 | |
kevman | 0:38ceb79fef03 | 348 | /** |
kevman | 0:38ceb79fef03 | 349 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
kevman | 0:38ceb79fef03 | 350 | */ |
kevman | 0:38ceb79fef03 | 351 | typedef struct |
kevman | 0:38ceb79fef03 | 352 | { |
kevman | 0:38ceb79fef03 | 353 | __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
kevman | 0:38ceb79fef03 | 354 | uint32_t RESERVED0[16U]; |
kevman | 0:38ceb79fef03 | 355 | __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
kevman | 0:38ceb79fef03 | 356 | uint32_t RSERVED1[16U]; |
kevman | 0:38ceb79fef03 | 357 | __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
kevman | 0:38ceb79fef03 | 358 | uint32_t RESERVED2[16U]; |
kevman | 0:38ceb79fef03 | 359 | __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
kevman | 0:38ceb79fef03 | 360 | uint32_t RESERVED3[16U]; |
kevman | 0:38ceb79fef03 | 361 | __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
kevman | 0:38ceb79fef03 | 362 | uint32_t RESERVED4[16U]; |
kevman | 0:38ceb79fef03 | 363 | __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ |
kevman | 0:38ceb79fef03 | 364 | uint32_t RESERVED5[16U]; |
kevman | 0:38ceb79fef03 | 365 | __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
kevman | 0:38ceb79fef03 | 366 | } NVIC_Type; |
kevman | 0:38ceb79fef03 | 367 | |
kevman | 0:38ceb79fef03 | 368 | /*@} end of group CMSIS_NVIC */ |
kevman | 0:38ceb79fef03 | 369 | |
kevman | 0:38ceb79fef03 | 370 | |
kevman | 0:38ceb79fef03 | 371 | /** |
kevman | 0:38ceb79fef03 | 372 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 373 | \defgroup CMSIS_SCB System Control Block (SCB) |
kevman | 0:38ceb79fef03 | 374 | \brief Type definitions for the System Control Block Registers |
kevman | 0:38ceb79fef03 | 375 | @{ |
kevman | 0:38ceb79fef03 | 376 | */ |
kevman | 0:38ceb79fef03 | 377 | |
kevman | 0:38ceb79fef03 | 378 | /** |
kevman | 0:38ceb79fef03 | 379 | \brief Structure type to access the System Control Block (SCB). |
kevman | 0:38ceb79fef03 | 380 | */ |
kevman | 0:38ceb79fef03 | 381 | typedef struct |
kevman | 0:38ceb79fef03 | 382 | { |
kevman | 0:38ceb79fef03 | 383 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
kevman | 0:38ceb79fef03 | 384 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
kevman | 0:38ceb79fef03 | 385 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 386 | __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
kevman | 0:38ceb79fef03 | 387 | #else |
kevman | 0:38ceb79fef03 | 388 | uint32_t RESERVED0; |
kevman | 0:38ceb79fef03 | 389 | #endif |
kevman | 0:38ceb79fef03 | 390 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
kevman | 0:38ceb79fef03 | 391 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
kevman | 0:38ceb79fef03 | 392 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
kevman | 0:38ceb79fef03 | 393 | uint32_t RESERVED1; |
kevman | 0:38ceb79fef03 | 394 | __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
kevman | 0:38ceb79fef03 | 395 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
kevman | 0:38ceb79fef03 | 396 | } SCB_Type; |
kevman | 0:38ceb79fef03 | 397 | |
kevman | 0:38ceb79fef03 | 398 | /* SCB CPUID Register Definitions */ |
kevman | 0:38ceb79fef03 | 399 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
kevman | 0:38ceb79fef03 | 400 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
kevman | 0:38ceb79fef03 | 401 | |
kevman | 0:38ceb79fef03 | 402 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
kevman | 0:38ceb79fef03 | 403 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
kevman | 0:38ceb79fef03 | 404 | |
kevman | 0:38ceb79fef03 | 405 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
kevman | 0:38ceb79fef03 | 406 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
kevman | 0:38ceb79fef03 | 407 | |
kevman | 0:38ceb79fef03 | 408 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
kevman | 0:38ceb79fef03 | 409 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
kevman | 0:38ceb79fef03 | 410 | |
kevman | 0:38ceb79fef03 | 411 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
kevman | 0:38ceb79fef03 | 412 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
kevman | 0:38ceb79fef03 | 413 | |
kevman | 0:38ceb79fef03 | 414 | /* SCB Interrupt Control State Register Definitions */ |
kevman | 0:38ceb79fef03 | 415 | #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ |
kevman | 0:38ceb79fef03 | 416 | #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ |
kevman | 0:38ceb79fef03 | 417 | |
kevman | 0:38ceb79fef03 | 418 | #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ |
kevman | 0:38ceb79fef03 | 419 | #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ |
kevman | 0:38ceb79fef03 | 420 | |
kevman | 0:38ceb79fef03 | 421 | #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ |
kevman | 0:38ceb79fef03 | 422 | #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ |
kevman | 0:38ceb79fef03 | 423 | |
kevman | 0:38ceb79fef03 | 424 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
kevman | 0:38ceb79fef03 | 425 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
kevman | 0:38ceb79fef03 | 426 | |
kevman | 0:38ceb79fef03 | 427 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
kevman | 0:38ceb79fef03 | 428 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
kevman | 0:38ceb79fef03 | 429 | |
kevman | 0:38ceb79fef03 | 430 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
kevman | 0:38ceb79fef03 | 431 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
kevman | 0:38ceb79fef03 | 432 | |
kevman | 0:38ceb79fef03 | 433 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
kevman | 0:38ceb79fef03 | 434 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
kevman | 0:38ceb79fef03 | 435 | |
kevman | 0:38ceb79fef03 | 436 | #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ |
kevman | 0:38ceb79fef03 | 437 | #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ |
kevman | 0:38ceb79fef03 | 438 | |
kevman | 0:38ceb79fef03 | 439 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
kevman | 0:38ceb79fef03 | 440 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
kevman | 0:38ceb79fef03 | 441 | |
kevman | 0:38ceb79fef03 | 442 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
kevman | 0:38ceb79fef03 | 443 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
kevman | 0:38ceb79fef03 | 444 | |
kevman | 0:38ceb79fef03 | 445 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
kevman | 0:38ceb79fef03 | 446 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
kevman | 0:38ceb79fef03 | 447 | |
kevman | 0:38ceb79fef03 | 448 | #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ |
kevman | 0:38ceb79fef03 | 449 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
kevman | 0:38ceb79fef03 | 450 | |
kevman | 0:38ceb79fef03 | 451 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
kevman | 0:38ceb79fef03 | 452 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
kevman | 0:38ceb79fef03 | 453 | |
kevman | 0:38ceb79fef03 | 454 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 455 | /* SCB Vector Table Offset Register Definitions */ |
kevman | 0:38ceb79fef03 | 456 | #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
kevman | 0:38ceb79fef03 | 457 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
kevman | 0:38ceb79fef03 | 458 | #endif |
kevman | 0:38ceb79fef03 | 459 | |
kevman | 0:38ceb79fef03 | 460 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 461 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
kevman | 0:38ceb79fef03 | 462 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
kevman | 0:38ceb79fef03 | 463 | |
kevman | 0:38ceb79fef03 | 464 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
kevman | 0:38ceb79fef03 | 465 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
kevman | 0:38ceb79fef03 | 466 | |
kevman | 0:38ceb79fef03 | 467 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
kevman | 0:38ceb79fef03 | 468 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
kevman | 0:38ceb79fef03 | 469 | |
kevman | 0:38ceb79fef03 | 470 | #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ |
kevman | 0:38ceb79fef03 | 471 | #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ |
kevman | 0:38ceb79fef03 | 472 | |
kevman | 0:38ceb79fef03 | 473 | #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ |
kevman | 0:38ceb79fef03 | 474 | #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ |
kevman | 0:38ceb79fef03 | 475 | |
kevman | 0:38ceb79fef03 | 476 | #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ |
kevman | 0:38ceb79fef03 | 477 | #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ |
kevman | 0:38ceb79fef03 | 478 | |
kevman | 0:38ceb79fef03 | 479 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
kevman | 0:38ceb79fef03 | 480 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
kevman | 0:38ceb79fef03 | 481 | |
kevman | 0:38ceb79fef03 | 482 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
kevman | 0:38ceb79fef03 | 483 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
kevman | 0:38ceb79fef03 | 484 | |
kevman | 0:38ceb79fef03 | 485 | /* SCB System Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 486 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
kevman | 0:38ceb79fef03 | 487 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
kevman | 0:38ceb79fef03 | 488 | |
kevman | 0:38ceb79fef03 | 489 | #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ |
kevman | 0:38ceb79fef03 | 490 | #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ |
kevman | 0:38ceb79fef03 | 491 | |
kevman | 0:38ceb79fef03 | 492 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
kevman | 0:38ceb79fef03 | 493 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
kevman | 0:38ceb79fef03 | 494 | |
kevman | 0:38ceb79fef03 | 495 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
kevman | 0:38ceb79fef03 | 496 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
kevman | 0:38ceb79fef03 | 497 | |
kevman | 0:38ceb79fef03 | 498 | /* SCB Configuration Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 499 | #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ |
kevman | 0:38ceb79fef03 | 500 | #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ |
kevman | 0:38ceb79fef03 | 501 | |
kevman | 0:38ceb79fef03 | 502 | #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ |
kevman | 0:38ceb79fef03 | 503 | #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ |
kevman | 0:38ceb79fef03 | 504 | |
kevman | 0:38ceb79fef03 | 505 | #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ |
kevman | 0:38ceb79fef03 | 506 | #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ |
kevman | 0:38ceb79fef03 | 507 | |
kevman | 0:38ceb79fef03 | 508 | #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ |
kevman | 0:38ceb79fef03 | 509 | #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ |
kevman | 0:38ceb79fef03 | 510 | |
kevman | 0:38ceb79fef03 | 511 | #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ |
kevman | 0:38ceb79fef03 | 512 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
kevman | 0:38ceb79fef03 | 513 | |
kevman | 0:38ceb79fef03 | 514 | #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ |
kevman | 0:38ceb79fef03 | 515 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
kevman | 0:38ceb79fef03 | 516 | |
kevman | 0:38ceb79fef03 | 517 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
kevman | 0:38ceb79fef03 | 518 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
kevman | 0:38ceb79fef03 | 519 | |
kevman | 0:38ceb79fef03 | 520 | #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ |
kevman | 0:38ceb79fef03 | 521 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
kevman | 0:38ceb79fef03 | 522 | |
kevman | 0:38ceb79fef03 | 523 | /* SCB System Handler Control and State Register Definitions */ |
kevman | 0:38ceb79fef03 | 524 | #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ |
kevman | 0:38ceb79fef03 | 525 | #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ |
kevman | 0:38ceb79fef03 | 526 | |
kevman | 0:38ceb79fef03 | 527 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
kevman | 0:38ceb79fef03 | 528 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
kevman | 0:38ceb79fef03 | 529 | |
kevman | 0:38ceb79fef03 | 530 | #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ |
kevman | 0:38ceb79fef03 | 531 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
kevman | 0:38ceb79fef03 | 532 | |
kevman | 0:38ceb79fef03 | 533 | #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ |
kevman | 0:38ceb79fef03 | 534 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
kevman | 0:38ceb79fef03 | 535 | |
kevman | 0:38ceb79fef03 | 536 | #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ |
kevman | 0:38ceb79fef03 | 537 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
kevman | 0:38ceb79fef03 | 538 | |
kevman | 0:38ceb79fef03 | 539 | #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ |
kevman | 0:38ceb79fef03 | 540 | #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ |
kevman | 0:38ceb79fef03 | 541 | |
kevman | 0:38ceb79fef03 | 542 | #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ |
kevman | 0:38ceb79fef03 | 543 | #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ |
kevman | 0:38ceb79fef03 | 544 | |
kevman | 0:38ceb79fef03 | 545 | /*@} end of group CMSIS_SCB */ |
kevman | 0:38ceb79fef03 | 546 | |
kevman | 0:38ceb79fef03 | 547 | |
kevman | 0:38ceb79fef03 | 548 | /** |
kevman | 0:38ceb79fef03 | 549 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 550 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
kevman | 0:38ceb79fef03 | 551 | \brief Type definitions for the System Timer Registers. |
kevman | 0:38ceb79fef03 | 552 | @{ |
kevman | 0:38ceb79fef03 | 553 | */ |
kevman | 0:38ceb79fef03 | 554 | |
kevman | 0:38ceb79fef03 | 555 | /** |
kevman | 0:38ceb79fef03 | 556 | \brief Structure type to access the System Timer (SysTick). |
kevman | 0:38ceb79fef03 | 557 | */ |
kevman | 0:38ceb79fef03 | 558 | typedef struct |
kevman | 0:38ceb79fef03 | 559 | { |
kevman | 0:38ceb79fef03 | 560 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
kevman | 0:38ceb79fef03 | 561 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
kevman | 0:38ceb79fef03 | 562 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
kevman | 0:38ceb79fef03 | 563 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
kevman | 0:38ceb79fef03 | 564 | } SysTick_Type; |
kevman | 0:38ceb79fef03 | 565 | |
kevman | 0:38ceb79fef03 | 566 | /* SysTick Control / Status Register Definitions */ |
kevman | 0:38ceb79fef03 | 567 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
kevman | 0:38ceb79fef03 | 568 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
kevman | 0:38ceb79fef03 | 569 | |
kevman | 0:38ceb79fef03 | 570 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
kevman | 0:38ceb79fef03 | 571 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
kevman | 0:38ceb79fef03 | 572 | |
kevman | 0:38ceb79fef03 | 573 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
kevman | 0:38ceb79fef03 | 574 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
kevman | 0:38ceb79fef03 | 575 | |
kevman | 0:38ceb79fef03 | 576 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
kevman | 0:38ceb79fef03 | 577 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
kevman | 0:38ceb79fef03 | 578 | |
kevman | 0:38ceb79fef03 | 579 | /* SysTick Reload Register Definitions */ |
kevman | 0:38ceb79fef03 | 580 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
kevman | 0:38ceb79fef03 | 581 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
kevman | 0:38ceb79fef03 | 582 | |
kevman | 0:38ceb79fef03 | 583 | /* SysTick Current Register Definitions */ |
kevman | 0:38ceb79fef03 | 584 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
kevman | 0:38ceb79fef03 | 585 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
kevman | 0:38ceb79fef03 | 586 | |
kevman | 0:38ceb79fef03 | 587 | /* SysTick Calibration Register Definitions */ |
kevman | 0:38ceb79fef03 | 588 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
kevman | 0:38ceb79fef03 | 589 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
kevman | 0:38ceb79fef03 | 590 | |
kevman | 0:38ceb79fef03 | 591 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
kevman | 0:38ceb79fef03 | 592 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
kevman | 0:38ceb79fef03 | 593 | |
kevman | 0:38ceb79fef03 | 594 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
kevman | 0:38ceb79fef03 | 595 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
kevman | 0:38ceb79fef03 | 596 | |
kevman | 0:38ceb79fef03 | 597 | /*@} end of group CMSIS_SysTick */ |
kevman | 0:38ceb79fef03 | 598 | |
kevman | 0:38ceb79fef03 | 599 | |
kevman | 0:38ceb79fef03 | 600 | /** |
kevman | 0:38ceb79fef03 | 601 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 602 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
kevman | 0:38ceb79fef03 | 603 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
kevman | 0:38ceb79fef03 | 604 | @{ |
kevman | 0:38ceb79fef03 | 605 | */ |
kevman | 0:38ceb79fef03 | 606 | |
kevman | 0:38ceb79fef03 | 607 | /** |
kevman | 0:38ceb79fef03 | 608 | \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
kevman | 0:38ceb79fef03 | 609 | */ |
kevman | 0:38ceb79fef03 | 610 | typedef struct |
kevman | 0:38ceb79fef03 | 611 | { |
kevman | 0:38ceb79fef03 | 612 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
kevman | 0:38ceb79fef03 | 613 | uint32_t RESERVED0[6U]; |
kevman | 0:38ceb79fef03 | 614 | __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
kevman | 0:38ceb79fef03 | 615 | __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
kevman | 0:38ceb79fef03 | 616 | uint32_t RESERVED1[1U]; |
kevman | 0:38ceb79fef03 | 617 | __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
kevman | 0:38ceb79fef03 | 618 | uint32_t RESERVED2[1U]; |
kevman | 0:38ceb79fef03 | 619 | __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
kevman | 0:38ceb79fef03 | 620 | uint32_t RESERVED3[1U]; |
kevman | 0:38ceb79fef03 | 621 | __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
kevman | 0:38ceb79fef03 | 622 | uint32_t RESERVED4[1U]; |
kevman | 0:38ceb79fef03 | 623 | __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
kevman | 0:38ceb79fef03 | 624 | uint32_t RESERVED5[1U]; |
kevman | 0:38ceb79fef03 | 625 | __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
kevman | 0:38ceb79fef03 | 626 | uint32_t RESERVED6[1U]; |
kevman | 0:38ceb79fef03 | 627 | __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
kevman | 0:38ceb79fef03 | 628 | uint32_t RESERVED7[1U]; |
kevman | 0:38ceb79fef03 | 629 | __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
kevman | 0:38ceb79fef03 | 630 | uint32_t RESERVED8[1U]; |
kevman | 0:38ceb79fef03 | 631 | __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ |
kevman | 0:38ceb79fef03 | 632 | uint32_t RESERVED9[1U]; |
kevman | 0:38ceb79fef03 | 633 | __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ |
kevman | 0:38ceb79fef03 | 634 | uint32_t RESERVED10[1U]; |
kevman | 0:38ceb79fef03 | 635 | __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ |
kevman | 0:38ceb79fef03 | 636 | uint32_t RESERVED11[1U]; |
kevman | 0:38ceb79fef03 | 637 | __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ |
kevman | 0:38ceb79fef03 | 638 | uint32_t RESERVED12[1U]; |
kevman | 0:38ceb79fef03 | 639 | __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ |
kevman | 0:38ceb79fef03 | 640 | uint32_t RESERVED13[1U]; |
kevman | 0:38ceb79fef03 | 641 | __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ |
kevman | 0:38ceb79fef03 | 642 | uint32_t RESERVED14[1U]; |
kevman | 0:38ceb79fef03 | 643 | __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ |
kevman | 0:38ceb79fef03 | 644 | uint32_t RESERVED15[1U]; |
kevman | 0:38ceb79fef03 | 645 | __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ |
kevman | 0:38ceb79fef03 | 646 | uint32_t RESERVED16[1U]; |
kevman | 0:38ceb79fef03 | 647 | __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ |
kevman | 0:38ceb79fef03 | 648 | uint32_t RESERVED17[1U]; |
kevman | 0:38ceb79fef03 | 649 | __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ |
kevman | 0:38ceb79fef03 | 650 | uint32_t RESERVED18[1U]; |
kevman | 0:38ceb79fef03 | 651 | __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ |
kevman | 0:38ceb79fef03 | 652 | uint32_t RESERVED19[1U]; |
kevman | 0:38ceb79fef03 | 653 | __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ |
kevman | 0:38ceb79fef03 | 654 | uint32_t RESERVED20[1U]; |
kevman | 0:38ceb79fef03 | 655 | __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ |
kevman | 0:38ceb79fef03 | 656 | uint32_t RESERVED21[1U]; |
kevman | 0:38ceb79fef03 | 657 | __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ |
kevman | 0:38ceb79fef03 | 658 | uint32_t RESERVED22[1U]; |
kevman | 0:38ceb79fef03 | 659 | __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ |
kevman | 0:38ceb79fef03 | 660 | uint32_t RESERVED23[1U]; |
kevman | 0:38ceb79fef03 | 661 | __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ |
kevman | 0:38ceb79fef03 | 662 | uint32_t RESERVED24[1U]; |
kevman | 0:38ceb79fef03 | 663 | __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ |
kevman | 0:38ceb79fef03 | 664 | uint32_t RESERVED25[1U]; |
kevman | 0:38ceb79fef03 | 665 | __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ |
kevman | 0:38ceb79fef03 | 666 | uint32_t RESERVED26[1U]; |
kevman | 0:38ceb79fef03 | 667 | __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ |
kevman | 0:38ceb79fef03 | 668 | uint32_t RESERVED27[1U]; |
kevman | 0:38ceb79fef03 | 669 | __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ |
kevman | 0:38ceb79fef03 | 670 | uint32_t RESERVED28[1U]; |
kevman | 0:38ceb79fef03 | 671 | __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ |
kevman | 0:38ceb79fef03 | 672 | uint32_t RESERVED29[1U]; |
kevman | 0:38ceb79fef03 | 673 | __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ |
kevman | 0:38ceb79fef03 | 674 | uint32_t RESERVED30[1U]; |
kevman | 0:38ceb79fef03 | 675 | __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ |
kevman | 0:38ceb79fef03 | 676 | uint32_t RESERVED31[1U]; |
kevman | 0:38ceb79fef03 | 677 | __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ |
kevman | 0:38ceb79fef03 | 678 | } DWT_Type; |
kevman | 0:38ceb79fef03 | 679 | |
kevman | 0:38ceb79fef03 | 680 | /* DWT Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 681 | #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ |
kevman | 0:38ceb79fef03 | 682 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
kevman | 0:38ceb79fef03 | 683 | |
kevman | 0:38ceb79fef03 | 684 | #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ |
kevman | 0:38ceb79fef03 | 685 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
kevman | 0:38ceb79fef03 | 686 | |
kevman | 0:38ceb79fef03 | 687 | #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ |
kevman | 0:38ceb79fef03 | 688 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
kevman | 0:38ceb79fef03 | 689 | |
kevman | 0:38ceb79fef03 | 690 | #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ |
kevman | 0:38ceb79fef03 | 691 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
kevman | 0:38ceb79fef03 | 692 | |
kevman | 0:38ceb79fef03 | 693 | #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ |
kevman | 0:38ceb79fef03 | 694 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
kevman | 0:38ceb79fef03 | 695 | |
kevman | 0:38ceb79fef03 | 696 | /* DWT Comparator Function Register Definitions */ |
kevman | 0:38ceb79fef03 | 697 | #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ |
kevman | 0:38ceb79fef03 | 698 | #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ |
kevman | 0:38ceb79fef03 | 699 | |
kevman | 0:38ceb79fef03 | 700 | #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ |
kevman | 0:38ceb79fef03 | 701 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
kevman | 0:38ceb79fef03 | 702 | |
kevman | 0:38ceb79fef03 | 703 | #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ |
kevman | 0:38ceb79fef03 | 704 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
kevman | 0:38ceb79fef03 | 705 | |
kevman | 0:38ceb79fef03 | 706 | #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ |
kevman | 0:38ceb79fef03 | 707 | #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ |
kevman | 0:38ceb79fef03 | 708 | |
kevman | 0:38ceb79fef03 | 709 | #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ |
kevman | 0:38ceb79fef03 | 710 | #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ |
kevman | 0:38ceb79fef03 | 711 | |
kevman | 0:38ceb79fef03 | 712 | /*@}*/ /* end of group CMSIS_DWT */ |
kevman | 0:38ceb79fef03 | 713 | |
kevman | 0:38ceb79fef03 | 714 | |
kevman | 0:38ceb79fef03 | 715 | /** |
kevman | 0:38ceb79fef03 | 716 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 717 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
kevman | 0:38ceb79fef03 | 718 | \brief Type definitions for the Trace Port Interface (TPI) |
kevman | 0:38ceb79fef03 | 719 | @{ |
kevman | 0:38ceb79fef03 | 720 | */ |
kevman | 0:38ceb79fef03 | 721 | |
kevman | 0:38ceb79fef03 | 722 | /** |
kevman | 0:38ceb79fef03 | 723 | \brief Structure type to access the Trace Port Interface Register (TPI). |
kevman | 0:38ceb79fef03 | 724 | */ |
kevman | 0:38ceb79fef03 | 725 | typedef struct |
kevman | 0:38ceb79fef03 | 726 | { |
kevman | 0:38ceb79fef03 | 727 | __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
kevman | 0:38ceb79fef03 | 728 | __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
kevman | 0:38ceb79fef03 | 729 | uint32_t RESERVED0[2U]; |
kevman | 0:38ceb79fef03 | 730 | __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
kevman | 0:38ceb79fef03 | 731 | uint32_t RESERVED1[55U]; |
kevman | 0:38ceb79fef03 | 732 | __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
kevman | 0:38ceb79fef03 | 733 | uint32_t RESERVED2[131U]; |
kevman | 0:38ceb79fef03 | 734 | __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
kevman | 0:38ceb79fef03 | 735 | __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
kevman | 0:38ceb79fef03 | 736 | __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ |
kevman | 0:38ceb79fef03 | 737 | uint32_t RESERVED3[759U]; |
kevman | 0:38ceb79fef03 | 738 | __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ |
kevman | 0:38ceb79fef03 | 739 | __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ |
kevman | 0:38ceb79fef03 | 740 | __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ |
kevman | 0:38ceb79fef03 | 741 | uint32_t RESERVED4[1U]; |
kevman | 0:38ceb79fef03 | 742 | __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ |
kevman | 0:38ceb79fef03 | 743 | __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ |
kevman | 0:38ceb79fef03 | 744 | __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
kevman | 0:38ceb79fef03 | 745 | uint32_t RESERVED5[39U]; |
kevman | 0:38ceb79fef03 | 746 | __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
kevman | 0:38ceb79fef03 | 747 | __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
kevman | 0:38ceb79fef03 | 748 | uint32_t RESERVED7[8U]; |
kevman | 0:38ceb79fef03 | 749 | __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ |
kevman | 0:38ceb79fef03 | 750 | __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ |
kevman | 0:38ceb79fef03 | 751 | } TPI_Type; |
kevman | 0:38ceb79fef03 | 752 | |
kevman | 0:38ceb79fef03 | 753 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
kevman | 0:38ceb79fef03 | 754 | #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ |
kevman | 0:38ceb79fef03 | 755 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ |
kevman | 0:38ceb79fef03 | 756 | |
kevman | 0:38ceb79fef03 | 757 | /* TPI Selected Pin Protocol Register Definitions */ |
kevman | 0:38ceb79fef03 | 758 | #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ |
kevman | 0:38ceb79fef03 | 759 | #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ |
kevman | 0:38ceb79fef03 | 760 | |
kevman | 0:38ceb79fef03 | 761 | /* TPI Formatter and Flush Status Register Definitions */ |
kevman | 0:38ceb79fef03 | 762 | #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ |
kevman | 0:38ceb79fef03 | 763 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
kevman | 0:38ceb79fef03 | 764 | |
kevman | 0:38ceb79fef03 | 765 | #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ |
kevman | 0:38ceb79fef03 | 766 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
kevman | 0:38ceb79fef03 | 767 | |
kevman | 0:38ceb79fef03 | 768 | #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ |
kevman | 0:38ceb79fef03 | 769 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
kevman | 0:38ceb79fef03 | 770 | |
kevman | 0:38ceb79fef03 | 771 | #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ |
kevman | 0:38ceb79fef03 | 772 | #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ |
kevman | 0:38ceb79fef03 | 773 | |
kevman | 0:38ceb79fef03 | 774 | /* TPI Formatter and Flush Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 775 | #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ |
kevman | 0:38ceb79fef03 | 776 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
kevman | 0:38ceb79fef03 | 777 | |
kevman | 0:38ceb79fef03 | 778 | #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ |
kevman | 0:38ceb79fef03 | 779 | #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ |
kevman | 0:38ceb79fef03 | 780 | |
kevman | 0:38ceb79fef03 | 781 | #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ |
kevman | 0:38ceb79fef03 | 782 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
kevman | 0:38ceb79fef03 | 783 | |
kevman | 0:38ceb79fef03 | 784 | /* TPI TRIGGER Register Definitions */ |
kevman | 0:38ceb79fef03 | 785 | #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ |
kevman | 0:38ceb79fef03 | 786 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ |
kevman | 0:38ceb79fef03 | 787 | |
kevman | 0:38ceb79fef03 | 788 | /* TPI Integration Test FIFO Test Data 0 Register Definitions */ |
kevman | 0:38ceb79fef03 | 789 | #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ |
kevman | 0:38ceb79fef03 | 790 | #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ |
kevman | 0:38ceb79fef03 | 791 | |
kevman | 0:38ceb79fef03 | 792 | #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ |
kevman | 0:38ceb79fef03 | 793 | #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ |
kevman | 0:38ceb79fef03 | 794 | |
kevman | 0:38ceb79fef03 | 795 | #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ |
kevman | 0:38ceb79fef03 | 796 | #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ |
kevman | 0:38ceb79fef03 | 797 | |
kevman | 0:38ceb79fef03 | 798 | #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ |
kevman | 0:38ceb79fef03 | 799 | #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ |
kevman | 0:38ceb79fef03 | 800 | |
kevman | 0:38ceb79fef03 | 801 | #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ |
kevman | 0:38ceb79fef03 | 802 | #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ |
kevman | 0:38ceb79fef03 | 803 | |
kevman | 0:38ceb79fef03 | 804 | #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ |
kevman | 0:38ceb79fef03 | 805 | #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ |
kevman | 0:38ceb79fef03 | 806 | |
kevman | 0:38ceb79fef03 | 807 | #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ |
kevman | 0:38ceb79fef03 | 808 | #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ |
kevman | 0:38ceb79fef03 | 809 | |
kevman | 0:38ceb79fef03 | 810 | /* TPI Integration Test ATB Control Register 2 Register Definitions */ |
kevman | 0:38ceb79fef03 | 811 | #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ |
kevman | 0:38ceb79fef03 | 812 | #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ |
kevman | 0:38ceb79fef03 | 813 | |
kevman | 0:38ceb79fef03 | 814 | #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ |
kevman | 0:38ceb79fef03 | 815 | #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ |
kevman | 0:38ceb79fef03 | 816 | |
kevman | 0:38ceb79fef03 | 817 | #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ |
kevman | 0:38ceb79fef03 | 818 | #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ |
kevman | 0:38ceb79fef03 | 819 | |
kevman | 0:38ceb79fef03 | 820 | #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ |
kevman | 0:38ceb79fef03 | 821 | #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ |
kevman | 0:38ceb79fef03 | 822 | |
kevman | 0:38ceb79fef03 | 823 | /* TPI Integration Test FIFO Test Data 1 Register Definitions */ |
kevman | 0:38ceb79fef03 | 824 | #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ |
kevman | 0:38ceb79fef03 | 825 | #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ |
kevman | 0:38ceb79fef03 | 826 | |
kevman | 0:38ceb79fef03 | 827 | #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ |
kevman | 0:38ceb79fef03 | 828 | #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ |
kevman | 0:38ceb79fef03 | 829 | |
kevman | 0:38ceb79fef03 | 830 | #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ |
kevman | 0:38ceb79fef03 | 831 | #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ |
kevman | 0:38ceb79fef03 | 832 | |
kevman | 0:38ceb79fef03 | 833 | #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ |
kevman | 0:38ceb79fef03 | 834 | #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ |
kevman | 0:38ceb79fef03 | 835 | |
kevman | 0:38ceb79fef03 | 836 | #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ |
kevman | 0:38ceb79fef03 | 837 | #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ |
kevman | 0:38ceb79fef03 | 838 | |
kevman | 0:38ceb79fef03 | 839 | #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ |
kevman | 0:38ceb79fef03 | 840 | #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ |
kevman | 0:38ceb79fef03 | 841 | |
kevman | 0:38ceb79fef03 | 842 | #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ |
kevman | 0:38ceb79fef03 | 843 | #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ |
kevman | 0:38ceb79fef03 | 844 | |
kevman | 0:38ceb79fef03 | 845 | /* TPI Integration Test ATB Control Register 0 Definitions */ |
kevman | 0:38ceb79fef03 | 846 | #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ |
kevman | 0:38ceb79fef03 | 847 | #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ |
kevman | 0:38ceb79fef03 | 848 | |
kevman | 0:38ceb79fef03 | 849 | #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ |
kevman | 0:38ceb79fef03 | 850 | #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ |
kevman | 0:38ceb79fef03 | 851 | |
kevman | 0:38ceb79fef03 | 852 | #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ |
kevman | 0:38ceb79fef03 | 853 | #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ |
kevman | 0:38ceb79fef03 | 854 | |
kevman | 0:38ceb79fef03 | 855 | #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ |
kevman | 0:38ceb79fef03 | 856 | #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ |
kevman | 0:38ceb79fef03 | 857 | |
kevman | 0:38ceb79fef03 | 858 | /* TPI Integration Mode Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 859 | #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ |
kevman | 0:38ceb79fef03 | 860 | #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ |
kevman | 0:38ceb79fef03 | 861 | |
kevman | 0:38ceb79fef03 | 862 | /* TPI DEVID Register Definitions */ |
kevman | 0:38ceb79fef03 | 863 | #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ |
kevman | 0:38ceb79fef03 | 864 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
kevman | 0:38ceb79fef03 | 865 | |
kevman | 0:38ceb79fef03 | 866 | #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ |
kevman | 0:38ceb79fef03 | 867 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
kevman | 0:38ceb79fef03 | 868 | |
kevman | 0:38ceb79fef03 | 869 | #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ |
kevman | 0:38ceb79fef03 | 870 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
kevman | 0:38ceb79fef03 | 871 | |
kevman | 0:38ceb79fef03 | 872 | #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ |
kevman | 0:38ceb79fef03 | 873 | #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ |
kevman | 0:38ceb79fef03 | 874 | |
kevman | 0:38ceb79fef03 | 875 | #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ |
kevman | 0:38ceb79fef03 | 876 | #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ |
kevman | 0:38ceb79fef03 | 877 | |
kevman | 0:38ceb79fef03 | 878 | /* TPI DEVTYPE Register Definitions */ |
kevman | 0:38ceb79fef03 | 879 | #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ |
kevman | 0:38ceb79fef03 | 880 | #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ |
kevman | 0:38ceb79fef03 | 881 | |
kevman | 0:38ceb79fef03 | 882 | #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ |
kevman | 0:38ceb79fef03 | 883 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
kevman | 0:38ceb79fef03 | 884 | |
kevman | 0:38ceb79fef03 | 885 | /*@}*/ /* end of group CMSIS_TPI */ |
kevman | 0:38ceb79fef03 | 886 | |
kevman | 0:38ceb79fef03 | 887 | |
kevman | 0:38ceb79fef03 | 888 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 889 | /** |
kevman | 0:38ceb79fef03 | 890 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 891 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
kevman | 0:38ceb79fef03 | 892 | \brief Type definitions for the Memory Protection Unit (MPU) |
kevman | 0:38ceb79fef03 | 893 | @{ |
kevman | 0:38ceb79fef03 | 894 | */ |
kevman | 0:38ceb79fef03 | 895 | |
kevman | 0:38ceb79fef03 | 896 | /** |
kevman | 0:38ceb79fef03 | 897 | \brief Structure type to access the Memory Protection Unit (MPU). |
kevman | 0:38ceb79fef03 | 898 | */ |
kevman | 0:38ceb79fef03 | 899 | typedef struct |
kevman | 0:38ceb79fef03 | 900 | { |
kevman | 0:38ceb79fef03 | 901 | __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
kevman | 0:38ceb79fef03 | 902 | __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
kevman | 0:38ceb79fef03 | 903 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ |
kevman | 0:38ceb79fef03 | 904 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
kevman | 0:38ceb79fef03 | 905 | __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ |
kevman | 0:38ceb79fef03 | 906 | uint32_t RESERVED0[7U]; |
kevman | 0:38ceb79fef03 | 907 | union { |
kevman | 0:38ceb79fef03 | 908 | __IOM uint32_t MAIR[2]; |
kevman | 0:38ceb79fef03 | 909 | struct { |
kevman | 0:38ceb79fef03 | 910 | __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ |
kevman | 0:38ceb79fef03 | 911 | __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ |
kevman | 0:38ceb79fef03 | 912 | }; |
kevman | 0:38ceb79fef03 | 913 | }; |
kevman | 0:38ceb79fef03 | 914 | } MPU_Type; |
kevman | 0:38ceb79fef03 | 915 | |
kevman | 0:38ceb79fef03 | 916 | #define MPU_TYPE_RALIASES 1U |
kevman | 0:38ceb79fef03 | 917 | |
kevman | 0:38ceb79fef03 | 918 | /* MPU Type Register Definitions */ |
kevman | 0:38ceb79fef03 | 919 | #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
kevman | 0:38ceb79fef03 | 920 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
kevman | 0:38ceb79fef03 | 921 | |
kevman | 0:38ceb79fef03 | 922 | #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
kevman | 0:38ceb79fef03 | 923 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
kevman | 0:38ceb79fef03 | 924 | |
kevman | 0:38ceb79fef03 | 925 | #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
kevman | 0:38ceb79fef03 | 926 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
kevman | 0:38ceb79fef03 | 927 | |
kevman | 0:38ceb79fef03 | 928 | /* MPU Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 929 | #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
kevman | 0:38ceb79fef03 | 930 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
kevman | 0:38ceb79fef03 | 931 | |
kevman | 0:38ceb79fef03 | 932 | #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
kevman | 0:38ceb79fef03 | 933 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
kevman | 0:38ceb79fef03 | 934 | |
kevman | 0:38ceb79fef03 | 935 | #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
kevman | 0:38ceb79fef03 | 936 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
kevman | 0:38ceb79fef03 | 937 | |
kevman | 0:38ceb79fef03 | 938 | /* MPU Region Number Register Definitions */ |
kevman | 0:38ceb79fef03 | 939 | #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
kevman | 0:38ceb79fef03 | 940 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
kevman | 0:38ceb79fef03 | 941 | |
kevman | 0:38ceb79fef03 | 942 | /* MPU Region Base Address Register Definitions */ |
kevman | 0:38ceb79fef03 | 943 | #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ |
kevman | 0:38ceb79fef03 | 944 | #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ |
kevman | 0:38ceb79fef03 | 945 | |
kevman | 0:38ceb79fef03 | 946 | #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ |
kevman | 0:38ceb79fef03 | 947 | #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ |
kevman | 0:38ceb79fef03 | 948 | |
kevman | 0:38ceb79fef03 | 949 | #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ |
kevman | 0:38ceb79fef03 | 950 | #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ |
kevman | 0:38ceb79fef03 | 951 | |
kevman | 0:38ceb79fef03 | 952 | #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ |
kevman | 0:38ceb79fef03 | 953 | #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ |
kevman | 0:38ceb79fef03 | 954 | |
kevman | 0:38ceb79fef03 | 955 | /* MPU Region Limit Address Register Definitions */ |
kevman | 0:38ceb79fef03 | 956 | #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ |
kevman | 0:38ceb79fef03 | 957 | #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ |
kevman | 0:38ceb79fef03 | 958 | |
kevman | 0:38ceb79fef03 | 959 | #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ |
kevman | 0:38ceb79fef03 | 960 | #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ |
kevman | 0:38ceb79fef03 | 961 | |
kevman | 0:38ceb79fef03 | 962 | #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ |
kevman | 0:38ceb79fef03 | 963 | #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ |
kevman | 0:38ceb79fef03 | 964 | |
kevman | 0:38ceb79fef03 | 965 | /* MPU Memory Attribute Indirection Register 0 Definitions */ |
kevman | 0:38ceb79fef03 | 966 | #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ |
kevman | 0:38ceb79fef03 | 967 | #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ |
kevman | 0:38ceb79fef03 | 968 | |
kevman | 0:38ceb79fef03 | 969 | #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ |
kevman | 0:38ceb79fef03 | 970 | #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ |
kevman | 0:38ceb79fef03 | 971 | |
kevman | 0:38ceb79fef03 | 972 | #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ |
kevman | 0:38ceb79fef03 | 973 | #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ |
kevman | 0:38ceb79fef03 | 974 | |
kevman | 0:38ceb79fef03 | 975 | #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ |
kevman | 0:38ceb79fef03 | 976 | #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ |
kevman | 0:38ceb79fef03 | 977 | |
kevman | 0:38ceb79fef03 | 978 | /* MPU Memory Attribute Indirection Register 1 Definitions */ |
kevman | 0:38ceb79fef03 | 979 | #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ |
kevman | 0:38ceb79fef03 | 980 | #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ |
kevman | 0:38ceb79fef03 | 981 | |
kevman | 0:38ceb79fef03 | 982 | #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ |
kevman | 0:38ceb79fef03 | 983 | #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ |
kevman | 0:38ceb79fef03 | 984 | |
kevman | 0:38ceb79fef03 | 985 | #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ |
kevman | 0:38ceb79fef03 | 986 | #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ |
kevman | 0:38ceb79fef03 | 987 | |
kevman | 0:38ceb79fef03 | 988 | #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ |
kevman | 0:38ceb79fef03 | 989 | #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ |
kevman | 0:38ceb79fef03 | 990 | |
kevman | 0:38ceb79fef03 | 991 | /*@} end of group CMSIS_MPU */ |
kevman | 0:38ceb79fef03 | 992 | #endif |
kevman | 0:38ceb79fef03 | 993 | |
kevman | 0:38ceb79fef03 | 994 | |
kevman | 0:38ceb79fef03 | 995 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
kevman | 0:38ceb79fef03 | 996 | /** |
kevman | 0:38ceb79fef03 | 997 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 998 | \defgroup CMSIS_SAU Security Attribution Unit (SAU) |
kevman | 0:38ceb79fef03 | 999 | \brief Type definitions for the Security Attribution Unit (SAU) |
kevman | 0:38ceb79fef03 | 1000 | @{ |
kevman | 0:38ceb79fef03 | 1001 | */ |
kevman | 0:38ceb79fef03 | 1002 | |
kevman | 0:38ceb79fef03 | 1003 | /** |
kevman | 0:38ceb79fef03 | 1004 | \brief Structure type to access the Security Attribution Unit (SAU). |
kevman | 0:38ceb79fef03 | 1005 | */ |
kevman | 0:38ceb79fef03 | 1006 | typedef struct |
kevman | 0:38ceb79fef03 | 1007 | { |
kevman | 0:38ceb79fef03 | 1008 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ |
kevman | 0:38ceb79fef03 | 1009 | __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ |
kevman | 0:38ceb79fef03 | 1010 | #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 1011 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ |
kevman | 0:38ceb79fef03 | 1012 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ |
kevman | 0:38ceb79fef03 | 1013 | __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ |
kevman | 0:38ceb79fef03 | 1014 | #endif |
kevman | 0:38ceb79fef03 | 1015 | } SAU_Type; |
kevman | 0:38ceb79fef03 | 1016 | |
kevman | 0:38ceb79fef03 | 1017 | /* SAU Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 1018 | #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ |
kevman | 0:38ceb79fef03 | 1019 | #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ |
kevman | 0:38ceb79fef03 | 1020 | |
kevman | 0:38ceb79fef03 | 1021 | #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ |
kevman | 0:38ceb79fef03 | 1022 | #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ |
kevman | 0:38ceb79fef03 | 1023 | |
kevman | 0:38ceb79fef03 | 1024 | /* SAU Type Register Definitions */ |
kevman | 0:38ceb79fef03 | 1025 | #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ |
kevman | 0:38ceb79fef03 | 1026 | #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ |
kevman | 0:38ceb79fef03 | 1027 | |
kevman | 0:38ceb79fef03 | 1028 | #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 1029 | /* SAU Region Number Register Definitions */ |
kevman | 0:38ceb79fef03 | 1030 | #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ |
kevman | 0:38ceb79fef03 | 1031 | #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ |
kevman | 0:38ceb79fef03 | 1032 | |
kevman | 0:38ceb79fef03 | 1033 | /* SAU Region Base Address Register Definitions */ |
kevman | 0:38ceb79fef03 | 1034 | #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ |
kevman | 0:38ceb79fef03 | 1035 | #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ |
kevman | 0:38ceb79fef03 | 1036 | |
kevman | 0:38ceb79fef03 | 1037 | /* SAU Region Limit Address Register Definitions */ |
kevman | 0:38ceb79fef03 | 1038 | #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ |
kevman | 0:38ceb79fef03 | 1039 | #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ |
kevman | 0:38ceb79fef03 | 1040 | |
kevman | 0:38ceb79fef03 | 1041 | #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ |
kevman | 0:38ceb79fef03 | 1042 | #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ |
kevman | 0:38ceb79fef03 | 1043 | |
kevman | 0:38ceb79fef03 | 1044 | #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ |
kevman | 0:38ceb79fef03 | 1045 | #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ |
kevman | 0:38ceb79fef03 | 1046 | |
kevman | 0:38ceb79fef03 | 1047 | #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ |
kevman | 0:38ceb79fef03 | 1048 | |
kevman | 0:38ceb79fef03 | 1049 | /*@} end of group CMSIS_SAU */ |
kevman | 0:38ceb79fef03 | 1050 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
kevman | 0:38ceb79fef03 | 1051 | |
kevman | 0:38ceb79fef03 | 1052 | |
kevman | 0:38ceb79fef03 | 1053 | /** |
kevman | 0:38ceb79fef03 | 1054 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 1055 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
kevman | 0:38ceb79fef03 | 1056 | \brief Type definitions for the Core Debug Registers |
kevman | 0:38ceb79fef03 | 1057 | @{ |
kevman | 0:38ceb79fef03 | 1058 | */ |
kevman | 0:38ceb79fef03 | 1059 | |
kevman | 0:38ceb79fef03 | 1060 | /** |
kevman | 0:38ceb79fef03 | 1061 | \brief Structure type to access the Core Debug Register (CoreDebug). |
kevman | 0:38ceb79fef03 | 1062 | */ |
kevman | 0:38ceb79fef03 | 1063 | typedef struct |
kevman | 0:38ceb79fef03 | 1064 | { |
kevman | 0:38ceb79fef03 | 1065 | __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
kevman | 0:38ceb79fef03 | 1066 | __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
kevman | 0:38ceb79fef03 | 1067 | __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
kevman | 0:38ceb79fef03 | 1068 | __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
kevman | 0:38ceb79fef03 | 1069 | uint32_t RESERVED4[1U]; |
kevman | 0:38ceb79fef03 | 1070 | __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ |
kevman | 0:38ceb79fef03 | 1071 | __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ |
kevman | 0:38ceb79fef03 | 1072 | } CoreDebug_Type; |
kevman | 0:38ceb79fef03 | 1073 | |
kevman | 0:38ceb79fef03 | 1074 | /* Debug Halting Control and Status Register Definitions */ |
kevman | 0:38ceb79fef03 | 1075 | #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ |
kevman | 0:38ceb79fef03 | 1076 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
kevman | 0:38ceb79fef03 | 1077 | |
kevman | 0:38ceb79fef03 | 1078 | #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ |
kevman | 0:38ceb79fef03 | 1079 | #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ |
kevman | 0:38ceb79fef03 | 1080 | |
kevman | 0:38ceb79fef03 | 1081 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
kevman | 0:38ceb79fef03 | 1082 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
kevman | 0:38ceb79fef03 | 1083 | |
kevman | 0:38ceb79fef03 | 1084 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
kevman | 0:38ceb79fef03 | 1085 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
kevman | 0:38ceb79fef03 | 1086 | |
kevman | 0:38ceb79fef03 | 1087 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
kevman | 0:38ceb79fef03 | 1088 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
kevman | 0:38ceb79fef03 | 1089 | |
kevman | 0:38ceb79fef03 | 1090 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ |
kevman | 0:38ceb79fef03 | 1091 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
kevman | 0:38ceb79fef03 | 1092 | |
kevman | 0:38ceb79fef03 | 1093 | #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ |
kevman | 0:38ceb79fef03 | 1094 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
kevman | 0:38ceb79fef03 | 1095 | |
kevman | 0:38ceb79fef03 | 1096 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ |
kevman | 0:38ceb79fef03 | 1097 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
kevman | 0:38ceb79fef03 | 1098 | |
kevman | 0:38ceb79fef03 | 1099 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
kevman | 0:38ceb79fef03 | 1100 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
kevman | 0:38ceb79fef03 | 1101 | |
kevman | 0:38ceb79fef03 | 1102 | #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ |
kevman | 0:38ceb79fef03 | 1103 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
kevman | 0:38ceb79fef03 | 1104 | |
kevman | 0:38ceb79fef03 | 1105 | #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ |
kevman | 0:38ceb79fef03 | 1106 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
kevman | 0:38ceb79fef03 | 1107 | |
kevman | 0:38ceb79fef03 | 1108 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
kevman | 0:38ceb79fef03 | 1109 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
kevman | 0:38ceb79fef03 | 1110 | |
kevman | 0:38ceb79fef03 | 1111 | /* Debug Core Register Selector Register Definitions */ |
kevman | 0:38ceb79fef03 | 1112 | #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ |
kevman | 0:38ceb79fef03 | 1113 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
kevman | 0:38ceb79fef03 | 1114 | |
kevman | 0:38ceb79fef03 | 1115 | #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ |
kevman | 0:38ceb79fef03 | 1116 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ |
kevman | 0:38ceb79fef03 | 1117 | |
kevman | 0:38ceb79fef03 | 1118 | /* Debug Exception and Monitor Control Register */ |
kevman | 0:38ceb79fef03 | 1119 | #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ |
kevman | 0:38ceb79fef03 | 1120 | #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ |
kevman | 0:38ceb79fef03 | 1121 | |
kevman | 0:38ceb79fef03 | 1122 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
kevman | 0:38ceb79fef03 | 1123 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
kevman | 0:38ceb79fef03 | 1124 | |
kevman | 0:38ceb79fef03 | 1125 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
kevman | 0:38ceb79fef03 | 1126 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
kevman | 0:38ceb79fef03 | 1127 | |
kevman | 0:38ceb79fef03 | 1128 | /* Debug Authentication Control Register Definitions */ |
kevman | 0:38ceb79fef03 | 1129 | #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ |
kevman | 0:38ceb79fef03 | 1130 | #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ |
kevman | 0:38ceb79fef03 | 1131 | |
kevman | 0:38ceb79fef03 | 1132 | #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ |
kevman | 0:38ceb79fef03 | 1133 | #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ |
kevman | 0:38ceb79fef03 | 1134 | |
kevman | 0:38ceb79fef03 | 1135 | #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ |
kevman | 0:38ceb79fef03 | 1136 | #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ |
kevman | 0:38ceb79fef03 | 1137 | |
kevman | 0:38ceb79fef03 | 1138 | #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ |
kevman | 0:38ceb79fef03 | 1139 | #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ |
kevman | 0:38ceb79fef03 | 1140 | |
kevman | 0:38ceb79fef03 | 1141 | /* Debug Security Control and Status Register Definitions */ |
kevman | 0:38ceb79fef03 | 1142 | #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ |
kevman | 0:38ceb79fef03 | 1143 | #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ |
kevman | 0:38ceb79fef03 | 1144 | |
kevman | 0:38ceb79fef03 | 1145 | #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ |
kevman | 0:38ceb79fef03 | 1146 | #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ |
kevman | 0:38ceb79fef03 | 1147 | |
kevman | 0:38ceb79fef03 | 1148 | #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ |
kevman | 0:38ceb79fef03 | 1149 | #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ |
kevman | 0:38ceb79fef03 | 1150 | |
kevman | 0:38ceb79fef03 | 1151 | /*@} end of group CMSIS_CoreDebug */ |
kevman | 0:38ceb79fef03 | 1152 | |
kevman | 0:38ceb79fef03 | 1153 | |
kevman | 0:38ceb79fef03 | 1154 | /** |
kevman | 0:38ceb79fef03 | 1155 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 1156 | \defgroup CMSIS_core_bitfield Core register bit field macros |
kevman | 0:38ceb79fef03 | 1157 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
kevman | 0:38ceb79fef03 | 1158 | @{ |
kevman | 0:38ceb79fef03 | 1159 | */ |
kevman | 0:38ceb79fef03 | 1160 | |
kevman | 0:38ceb79fef03 | 1161 | /** |
kevman | 0:38ceb79fef03 | 1162 | \brief Mask and shift a bit field value for use in a register bit range. |
kevman | 0:38ceb79fef03 | 1163 | \param[in] field Name of the register bit field. |
kevman | 0:38ceb79fef03 | 1164 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
kevman | 0:38ceb79fef03 | 1165 | \return Masked and shifted value. |
kevman | 0:38ceb79fef03 | 1166 | */ |
kevman | 0:38ceb79fef03 | 1167 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
kevman | 0:38ceb79fef03 | 1168 | |
kevman | 0:38ceb79fef03 | 1169 | /** |
kevman | 0:38ceb79fef03 | 1170 | \brief Mask and shift a register value to extract a bit filed value. |
kevman | 0:38ceb79fef03 | 1171 | \param[in] field Name of the register bit field. |
kevman | 0:38ceb79fef03 | 1172 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
kevman | 0:38ceb79fef03 | 1173 | \return Masked and shifted bit field value. |
kevman | 0:38ceb79fef03 | 1174 | */ |
kevman | 0:38ceb79fef03 | 1175 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
kevman | 0:38ceb79fef03 | 1176 | |
kevman | 0:38ceb79fef03 | 1177 | /*@} end of group CMSIS_core_bitfield */ |
kevman | 0:38ceb79fef03 | 1178 | |
kevman | 0:38ceb79fef03 | 1179 | |
kevman | 0:38ceb79fef03 | 1180 | /** |
kevman | 0:38ceb79fef03 | 1181 | \ingroup CMSIS_core_register |
kevman | 0:38ceb79fef03 | 1182 | \defgroup CMSIS_core_base Core Definitions |
kevman | 0:38ceb79fef03 | 1183 | \brief Definitions for base addresses, unions, and structures. |
kevman | 0:38ceb79fef03 | 1184 | @{ |
kevman | 0:38ceb79fef03 | 1185 | */ |
kevman | 0:38ceb79fef03 | 1186 | |
kevman | 0:38ceb79fef03 | 1187 | /* Memory mapping of Core Hardware */ |
kevman | 0:38ceb79fef03 | 1188 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
kevman | 0:38ceb79fef03 | 1189 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
kevman | 0:38ceb79fef03 | 1190 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
kevman | 0:38ceb79fef03 | 1191 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
kevman | 0:38ceb79fef03 | 1192 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
kevman | 0:38ceb79fef03 | 1193 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
kevman | 0:38ceb79fef03 | 1194 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
kevman | 0:38ceb79fef03 | 1195 | |
kevman | 0:38ceb79fef03 | 1196 | |
kevman | 0:38ceb79fef03 | 1197 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
kevman | 0:38ceb79fef03 | 1198 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
kevman | 0:38ceb79fef03 | 1199 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
kevman | 0:38ceb79fef03 | 1200 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
kevman | 0:38ceb79fef03 | 1201 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
kevman | 0:38ceb79fef03 | 1202 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ |
kevman | 0:38ceb79fef03 | 1203 | |
kevman | 0:38ceb79fef03 | 1204 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 1205 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
kevman | 0:38ceb79fef03 | 1206 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
kevman | 0:38ceb79fef03 | 1207 | #endif |
kevman | 0:38ceb79fef03 | 1208 | |
kevman | 0:38ceb79fef03 | 1209 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
kevman | 0:38ceb79fef03 | 1210 | #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ |
kevman | 0:38ceb79fef03 | 1211 | #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ |
kevman | 0:38ceb79fef03 | 1212 | #endif |
kevman | 0:38ceb79fef03 | 1213 | |
kevman | 0:38ceb79fef03 | 1214 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
kevman | 0:38ceb79fef03 | 1215 | #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1216 | #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1217 | #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1218 | #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1219 | #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1220 | |
kevman | 0:38ceb79fef03 | 1221 | #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1222 | #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1223 | #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1224 | #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1225 | |
kevman | 0:38ceb79fef03 | 1226 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 1227 | #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1228 | #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ |
kevman | 0:38ceb79fef03 | 1229 | #endif |
kevman | 0:38ceb79fef03 | 1230 | |
kevman | 0:38ceb79fef03 | 1231 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
kevman | 0:38ceb79fef03 | 1232 | /*@} */ |
kevman | 0:38ceb79fef03 | 1233 | |
kevman | 0:38ceb79fef03 | 1234 | |
kevman | 0:38ceb79fef03 | 1235 | |
kevman | 0:38ceb79fef03 | 1236 | /******************************************************************************* |
kevman | 0:38ceb79fef03 | 1237 | * Hardware Abstraction Layer |
kevman | 0:38ceb79fef03 | 1238 | Core Function Interface contains: |
kevman | 0:38ceb79fef03 | 1239 | - Core NVIC Functions |
kevman | 0:38ceb79fef03 | 1240 | - Core SysTick Functions |
kevman | 0:38ceb79fef03 | 1241 | - Core Register Access Functions |
kevman | 0:38ceb79fef03 | 1242 | ******************************************************************************/ |
kevman | 0:38ceb79fef03 | 1243 | /** |
kevman | 0:38ceb79fef03 | 1244 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
kevman | 0:38ceb79fef03 | 1245 | */ |
kevman | 0:38ceb79fef03 | 1246 | |
kevman | 0:38ceb79fef03 | 1247 | |
kevman | 0:38ceb79fef03 | 1248 | |
kevman | 0:38ceb79fef03 | 1249 | /* ########################## NVIC functions #################################### */ |
kevman | 0:38ceb79fef03 | 1250 | /** |
kevman | 0:38ceb79fef03 | 1251 | \ingroup CMSIS_Core_FunctionInterface |
kevman | 0:38ceb79fef03 | 1252 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
kevman | 0:38ceb79fef03 | 1253 | \brief Functions that manage interrupts and exceptions via the NVIC. |
kevman | 0:38ceb79fef03 | 1254 | @{ |
kevman | 0:38ceb79fef03 | 1255 | */ |
kevman | 0:38ceb79fef03 | 1256 | |
kevman | 0:38ceb79fef03 | 1257 | #ifdef CMSIS_NVIC_VIRTUAL |
kevman | 0:38ceb79fef03 | 1258 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
kevman | 0:38ceb79fef03 | 1259 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
kevman | 0:38ceb79fef03 | 1260 | #endif |
kevman | 0:38ceb79fef03 | 1261 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
kevman | 0:38ceb79fef03 | 1262 | #else |
kevman | 0:38ceb79fef03 | 1263 | /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ |
kevman | 0:38ceb79fef03 | 1264 | /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ |
kevman | 0:38ceb79fef03 | 1265 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
kevman | 0:38ceb79fef03 | 1266 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
kevman | 0:38ceb79fef03 | 1267 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
kevman | 0:38ceb79fef03 | 1268 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
kevman | 0:38ceb79fef03 | 1269 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
kevman | 0:38ceb79fef03 | 1270 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
kevman | 0:38ceb79fef03 | 1271 | #define NVIC_GetActive __NVIC_GetActive |
kevman | 0:38ceb79fef03 | 1272 | #define NVIC_SetPriority __NVIC_SetPriority |
kevman | 0:38ceb79fef03 | 1273 | #define NVIC_GetPriority __NVIC_GetPriority |
kevman | 0:38ceb79fef03 | 1274 | #define NVIC_SystemReset __NVIC_SystemReset |
kevman | 0:38ceb79fef03 | 1275 | #endif /* CMSIS_NVIC_VIRTUAL */ |
kevman | 0:38ceb79fef03 | 1276 | |
kevman | 0:38ceb79fef03 | 1277 | #ifdef CMSIS_VECTAB_VIRTUAL |
kevman | 0:38ceb79fef03 | 1278 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
kevman | 0:38ceb79fef03 | 1279 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
kevman | 0:38ceb79fef03 | 1280 | #endif |
kevman | 0:38ceb79fef03 | 1281 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
kevman | 0:38ceb79fef03 | 1282 | #else |
kevman | 0:38ceb79fef03 | 1283 | #define NVIC_SetVector __NVIC_SetVector |
kevman | 0:38ceb79fef03 | 1284 | #define NVIC_GetVector __NVIC_GetVector |
kevman | 0:38ceb79fef03 | 1285 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
kevman | 0:38ceb79fef03 | 1286 | |
kevman | 0:38ceb79fef03 | 1287 | #define NVIC_USER_IRQ_OFFSET 16 |
kevman | 0:38ceb79fef03 | 1288 | |
kevman | 0:38ceb79fef03 | 1289 | |
kevman | 0:38ceb79fef03 | 1290 | /* Special LR values for Secure/Non-Secure call handling and exception handling */ |
kevman | 0:38ceb79fef03 | 1291 | |
kevman | 0:38ceb79fef03 | 1292 | /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ |
kevman | 0:38ceb79fef03 | 1293 | #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ |
kevman | 0:38ceb79fef03 | 1294 | |
kevman | 0:38ceb79fef03 | 1295 | /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ |
kevman | 0:38ceb79fef03 | 1296 | #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ |
kevman | 0:38ceb79fef03 | 1297 | #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ |
kevman | 0:38ceb79fef03 | 1298 | #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ |
kevman | 0:38ceb79fef03 | 1299 | #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ |
kevman | 0:38ceb79fef03 | 1300 | #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ |
kevman | 0:38ceb79fef03 | 1301 | #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */ |
kevman | 0:38ceb79fef03 | 1302 | #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ |
kevman | 0:38ceb79fef03 | 1303 | |
kevman | 0:38ceb79fef03 | 1304 | /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ |
kevman | 0:38ceb79fef03 | 1305 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ |
kevman | 0:38ceb79fef03 | 1306 | #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ |
kevman | 0:38ceb79fef03 | 1307 | #else |
kevman | 0:38ceb79fef03 | 1308 | #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ |
kevman | 0:38ceb79fef03 | 1309 | #endif |
kevman | 0:38ceb79fef03 | 1310 | |
kevman | 0:38ceb79fef03 | 1311 | |
kevman | 0:38ceb79fef03 | 1312 | /* Interrupt Priorities are WORD accessible only under Armv6-M */ |
kevman | 0:38ceb79fef03 | 1313 | /* The following MACROS handle generation of the register offset and byte masks */ |
kevman | 0:38ceb79fef03 | 1314 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
kevman | 0:38ceb79fef03 | 1315 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
kevman | 0:38ceb79fef03 | 1316 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
kevman | 0:38ceb79fef03 | 1317 | |
kevman | 0:38ceb79fef03 | 1318 | #define __NVIC_SetPriorityGrouping(X) (void)(X) |
kevman | 0:38ceb79fef03 | 1319 | #define __NVIC_GetPriorityGrouping() (0U) |
kevman | 0:38ceb79fef03 | 1320 | |
kevman | 0:38ceb79fef03 | 1321 | /** |
kevman | 0:38ceb79fef03 | 1322 | \brief Enable Interrupt |
kevman | 0:38ceb79fef03 | 1323 | \details Enables a device specific interrupt in the NVIC interrupt controller. |
kevman | 0:38ceb79fef03 | 1324 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1325 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1326 | */ |
kevman | 0:38ceb79fef03 | 1327 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1328 | { |
kevman | 0:38ceb79fef03 | 1329 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1330 | { |
kevman | 0:38ceb79fef03 | 1331 | NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kevman | 0:38ceb79fef03 | 1332 | } |
kevman | 0:38ceb79fef03 | 1333 | } |
kevman | 0:38ceb79fef03 | 1334 | |
kevman | 0:38ceb79fef03 | 1335 | |
kevman | 0:38ceb79fef03 | 1336 | /** |
kevman | 0:38ceb79fef03 | 1337 | \brief Get Interrupt Enable status |
kevman | 0:38ceb79fef03 | 1338 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
kevman | 0:38ceb79fef03 | 1339 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1340 | \return 0 Interrupt is not enabled. |
kevman | 0:38ceb79fef03 | 1341 | \return 1 Interrupt is enabled. |
kevman | 0:38ceb79fef03 | 1342 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1343 | */ |
kevman | 0:38ceb79fef03 | 1344 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1345 | { |
kevman | 0:38ceb79fef03 | 1346 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1347 | { |
kevman | 0:38ceb79fef03 | 1348 | return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1349 | } |
kevman | 0:38ceb79fef03 | 1350 | else |
kevman | 0:38ceb79fef03 | 1351 | { |
kevman | 0:38ceb79fef03 | 1352 | return(0U); |
kevman | 0:38ceb79fef03 | 1353 | } |
kevman | 0:38ceb79fef03 | 1354 | } |
kevman | 0:38ceb79fef03 | 1355 | |
kevman | 0:38ceb79fef03 | 1356 | |
kevman | 0:38ceb79fef03 | 1357 | /** |
kevman | 0:38ceb79fef03 | 1358 | \brief Disable Interrupt |
kevman | 0:38ceb79fef03 | 1359 | \details Disables a device specific interrupt in the NVIC interrupt controller. |
kevman | 0:38ceb79fef03 | 1360 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1361 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1362 | */ |
kevman | 0:38ceb79fef03 | 1363 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1364 | { |
kevman | 0:38ceb79fef03 | 1365 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1366 | { |
kevman | 0:38ceb79fef03 | 1367 | NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kevman | 0:38ceb79fef03 | 1368 | __DSB(); |
kevman | 0:38ceb79fef03 | 1369 | __ISB(); |
kevman | 0:38ceb79fef03 | 1370 | } |
kevman | 0:38ceb79fef03 | 1371 | } |
kevman | 0:38ceb79fef03 | 1372 | |
kevman | 0:38ceb79fef03 | 1373 | |
kevman | 0:38ceb79fef03 | 1374 | /** |
kevman | 0:38ceb79fef03 | 1375 | \brief Get Pending Interrupt |
kevman | 0:38ceb79fef03 | 1376 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
kevman | 0:38ceb79fef03 | 1377 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1378 | \return 0 Interrupt status is not pending. |
kevman | 0:38ceb79fef03 | 1379 | \return 1 Interrupt status is pending. |
kevman | 0:38ceb79fef03 | 1380 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1381 | */ |
kevman | 0:38ceb79fef03 | 1382 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1383 | { |
kevman | 0:38ceb79fef03 | 1384 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1385 | { |
kevman | 0:38ceb79fef03 | 1386 | return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1387 | } |
kevman | 0:38ceb79fef03 | 1388 | else |
kevman | 0:38ceb79fef03 | 1389 | { |
kevman | 0:38ceb79fef03 | 1390 | return(0U); |
kevman | 0:38ceb79fef03 | 1391 | } |
kevman | 0:38ceb79fef03 | 1392 | } |
kevman | 0:38ceb79fef03 | 1393 | |
kevman | 0:38ceb79fef03 | 1394 | |
kevman | 0:38ceb79fef03 | 1395 | /** |
kevman | 0:38ceb79fef03 | 1396 | \brief Set Pending Interrupt |
kevman | 0:38ceb79fef03 | 1397 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
kevman | 0:38ceb79fef03 | 1398 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1399 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1400 | */ |
kevman | 0:38ceb79fef03 | 1401 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1402 | { |
kevman | 0:38ceb79fef03 | 1403 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1404 | { |
kevman | 0:38ceb79fef03 | 1405 | NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kevman | 0:38ceb79fef03 | 1406 | } |
kevman | 0:38ceb79fef03 | 1407 | } |
kevman | 0:38ceb79fef03 | 1408 | |
kevman | 0:38ceb79fef03 | 1409 | |
kevman | 0:38ceb79fef03 | 1410 | /** |
kevman | 0:38ceb79fef03 | 1411 | \brief Clear Pending Interrupt |
kevman | 0:38ceb79fef03 | 1412 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
kevman | 0:38ceb79fef03 | 1413 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1414 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1415 | */ |
kevman | 0:38ceb79fef03 | 1416 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1417 | { |
kevman | 0:38ceb79fef03 | 1418 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1419 | { |
kevman | 0:38ceb79fef03 | 1420 | NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kevman | 0:38ceb79fef03 | 1421 | } |
kevman | 0:38ceb79fef03 | 1422 | } |
kevman | 0:38ceb79fef03 | 1423 | |
kevman | 0:38ceb79fef03 | 1424 | |
kevman | 0:38ceb79fef03 | 1425 | /** |
kevman | 0:38ceb79fef03 | 1426 | \brief Get Active Interrupt |
kevman | 0:38ceb79fef03 | 1427 | \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. |
kevman | 0:38ceb79fef03 | 1428 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1429 | \return 0 Interrupt status is not active. |
kevman | 0:38ceb79fef03 | 1430 | \return 1 Interrupt status is active. |
kevman | 0:38ceb79fef03 | 1431 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1432 | */ |
kevman | 0:38ceb79fef03 | 1433 | __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1434 | { |
kevman | 0:38ceb79fef03 | 1435 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1436 | { |
kevman | 0:38ceb79fef03 | 1437 | return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1438 | } |
kevman | 0:38ceb79fef03 | 1439 | else |
kevman | 0:38ceb79fef03 | 1440 | { |
kevman | 0:38ceb79fef03 | 1441 | return(0U); |
kevman | 0:38ceb79fef03 | 1442 | } |
kevman | 0:38ceb79fef03 | 1443 | } |
kevman | 0:38ceb79fef03 | 1444 | |
kevman | 0:38ceb79fef03 | 1445 | |
kevman | 0:38ceb79fef03 | 1446 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
kevman | 0:38ceb79fef03 | 1447 | /** |
kevman | 0:38ceb79fef03 | 1448 | \brief Get Interrupt Target State |
kevman | 0:38ceb79fef03 | 1449 | \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
kevman | 0:38ceb79fef03 | 1450 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1451 | \return 0 if interrupt is assigned to Secure |
kevman | 0:38ceb79fef03 | 1452 | \return 1 if interrupt is assigned to Non Secure |
kevman | 0:38ceb79fef03 | 1453 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1454 | */ |
kevman | 0:38ceb79fef03 | 1455 | __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1456 | { |
kevman | 0:38ceb79fef03 | 1457 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1458 | { |
kevman | 0:38ceb79fef03 | 1459 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1460 | } |
kevman | 0:38ceb79fef03 | 1461 | else |
kevman | 0:38ceb79fef03 | 1462 | { |
kevman | 0:38ceb79fef03 | 1463 | return(0U); |
kevman | 0:38ceb79fef03 | 1464 | } |
kevman | 0:38ceb79fef03 | 1465 | } |
kevman | 0:38ceb79fef03 | 1466 | |
kevman | 0:38ceb79fef03 | 1467 | |
kevman | 0:38ceb79fef03 | 1468 | /** |
kevman | 0:38ceb79fef03 | 1469 | \brief Set Interrupt Target State |
kevman | 0:38ceb79fef03 | 1470 | \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
kevman | 0:38ceb79fef03 | 1471 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1472 | \return 0 if interrupt is assigned to Secure |
kevman | 0:38ceb79fef03 | 1473 | 1 if interrupt is assigned to Non Secure |
kevman | 0:38ceb79fef03 | 1474 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1475 | */ |
kevman | 0:38ceb79fef03 | 1476 | __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1477 | { |
kevman | 0:38ceb79fef03 | 1478 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1479 | { |
kevman | 0:38ceb79fef03 | 1480 | NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); |
kevman | 0:38ceb79fef03 | 1481 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1482 | } |
kevman | 0:38ceb79fef03 | 1483 | else |
kevman | 0:38ceb79fef03 | 1484 | { |
kevman | 0:38ceb79fef03 | 1485 | return(0U); |
kevman | 0:38ceb79fef03 | 1486 | } |
kevman | 0:38ceb79fef03 | 1487 | } |
kevman | 0:38ceb79fef03 | 1488 | |
kevman | 0:38ceb79fef03 | 1489 | |
kevman | 0:38ceb79fef03 | 1490 | /** |
kevman | 0:38ceb79fef03 | 1491 | \brief Clear Interrupt Target State |
kevman | 0:38ceb79fef03 | 1492 | \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
kevman | 0:38ceb79fef03 | 1493 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1494 | \return 0 if interrupt is assigned to Secure |
kevman | 0:38ceb79fef03 | 1495 | 1 if interrupt is assigned to Non Secure |
kevman | 0:38ceb79fef03 | 1496 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1497 | */ |
kevman | 0:38ceb79fef03 | 1498 | __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1499 | { |
kevman | 0:38ceb79fef03 | 1500 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1501 | { |
kevman | 0:38ceb79fef03 | 1502 | NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); |
kevman | 0:38ceb79fef03 | 1503 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1504 | } |
kevman | 0:38ceb79fef03 | 1505 | else |
kevman | 0:38ceb79fef03 | 1506 | { |
kevman | 0:38ceb79fef03 | 1507 | return(0U); |
kevman | 0:38ceb79fef03 | 1508 | } |
kevman | 0:38ceb79fef03 | 1509 | } |
kevman | 0:38ceb79fef03 | 1510 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
kevman | 0:38ceb79fef03 | 1511 | |
kevman | 0:38ceb79fef03 | 1512 | |
kevman | 0:38ceb79fef03 | 1513 | /** |
kevman | 0:38ceb79fef03 | 1514 | \brief Set Interrupt Priority |
kevman | 0:38ceb79fef03 | 1515 | \details Sets the priority of a device specific interrupt or a processor exception. |
kevman | 0:38ceb79fef03 | 1516 | The interrupt number can be positive to specify a device specific interrupt, |
kevman | 0:38ceb79fef03 | 1517 | or negative to specify a processor exception. |
kevman | 0:38ceb79fef03 | 1518 | \param [in] IRQn Interrupt number. |
kevman | 0:38ceb79fef03 | 1519 | \param [in] priority Priority to set. |
kevman | 0:38ceb79fef03 | 1520 | \note The priority cannot be set for every processor exception. |
kevman | 0:38ceb79fef03 | 1521 | */ |
kevman | 0:38ceb79fef03 | 1522 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
kevman | 0:38ceb79fef03 | 1523 | { |
kevman | 0:38ceb79fef03 | 1524 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1525 | { |
kevman | 0:38ceb79fef03 | 1526 | NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
kevman | 0:38ceb79fef03 | 1527 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
kevman | 0:38ceb79fef03 | 1528 | } |
kevman | 0:38ceb79fef03 | 1529 | else |
kevman | 0:38ceb79fef03 | 1530 | { |
kevman | 0:38ceb79fef03 | 1531 | SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
kevman | 0:38ceb79fef03 | 1532 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
kevman | 0:38ceb79fef03 | 1533 | } |
kevman | 0:38ceb79fef03 | 1534 | } |
kevman | 0:38ceb79fef03 | 1535 | |
kevman | 0:38ceb79fef03 | 1536 | |
kevman | 0:38ceb79fef03 | 1537 | /** |
kevman | 0:38ceb79fef03 | 1538 | \brief Get Interrupt Priority |
kevman | 0:38ceb79fef03 | 1539 | \details Reads the priority of a device specific interrupt or a processor exception. |
kevman | 0:38ceb79fef03 | 1540 | The interrupt number can be positive to specify a device specific interrupt, |
kevman | 0:38ceb79fef03 | 1541 | or negative to specify a processor exception. |
kevman | 0:38ceb79fef03 | 1542 | \param [in] IRQn Interrupt number. |
kevman | 0:38ceb79fef03 | 1543 | \return Interrupt Priority. |
kevman | 0:38ceb79fef03 | 1544 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
kevman | 0:38ceb79fef03 | 1545 | */ |
kevman | 0:38ceb79fef03 | 1546 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1547 | { |
kevman | 0:38ceb79fef03 | 1548 | |
kevman | 0:38ceb79fef03 | 1549 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1550 | { |
kevman | 0:38ceb79fef03 | 1551 | return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
kevman | 0:38ceb79fef03 | 1552 | } |
kevman | 0:38ceb79fef03 | 1553 | else |
kevman | 0:38ceb79fef03 | 1554 | { |
kevman | 0:38ceb79fef03 | 1555 | return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
kevman | 0:38ceb79fef03 | 1556 | } |
kevman | 0:38ceb79fef03 | 1557 | } |
kevman | 0:38ceb79fef03 | 1558 | |
kevman | 0:38ceb79fef03 | 1559 | |
kevman | 0:38ceb79fef03 | 1560 | /** |
kevman | 0:38ceb79fef03 | 1561 | \brief Encode Priority |
kevman | 0:38ceb79fef03 | 1562 | \details Encodes the priority for an interrupt with the given priority group, |
kevman | 0:38ceb79fef03 | 1563 | preemptive priority value, and subpriority value. |
kevman | 0:38ceb79fef03 | 1564 | In case of a conflict between priority grouping and available |
kevman | 0:38ceb79fef03 | 1565 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
kevman | 0:38ceb79fef03 | 1566 | \param [in] PriorityGroup Used priority group. |
kevman | 0:38ceb79fef03 | 1567 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
kevman | 0:38ceb79fef03 | 1568 | \param [in] SubPriority Subpriority value (starting from 0). |
kevman | 0:38ceb79fef03 | 1569 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
kevman | 0:38ceb79fef03 | 1570 | */ |
kevman | 0:38ceb79fef03 | 1571 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
kevman | 0:38ceb79fef03 | 1572 | { |
kevman | 0:38ceb79fef03 | 1573 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
kevman | 0:38ceb79fef03 | 1574 | uint32_t PreemptPriorityBits; |
kevman | 0:38ceb79fef03 | 1575 | uint32_t SubPriorityBits; |
kevman | 0:38ceb79fef03 | 1576 | |
kevman | 0:38ceb79fef03 | 1577 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
kevman | 0:38ceb79fef03 | 1578 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
kevman | 0:38ceb79fef03 | 1579 | |
kevman | 0:38ceb79fef03 | 1580 | return ( |
kevman | 0:38ceb79fef03 | 1581 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
kevman | 0:38ceb79fef03 | 1582 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
kevman | 0:38ceb79fef03 | 1583 | ); |
kevman | 0:38ceb79fef03 | 1584 | } |
kevman | 0:38ceb79fef03 | 1585 | |
kevman | 0:38ceb79fef03 | 1586 | |
kevman | 0:38ceb79fef03 | 1587 | /** |
kevman | 0:38ceb79fef03 | 1588 | \brief Decode Priority |
kevman | 0:38ceb79fef03 | 1589 | \details Decodes an interrupt priority value with a given priority group to |
kevman | 0:38ceb79fef03 | 1590 | preemptive priority value and subpriority value. |
kevman | 0:38ceb79fef03 | 1591 | In case of a conflict between priority grouping and available |
kevman | 0:38ceb79fef03 | 1592 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
kevman | 0:38ceb79fef03 | 1593 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
kevman | 0:38ceb79fef03 | 1594 | \param [in] PriorityGroup Used priority group. |
kevman | 0:38ceb79fef03 | 1595 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
kevman | 0:38ceb79fef03 | 1596 | \param [out] pSubPriority Subpriority value (starting from 0). |
kevman | 0:38ceb79fef03 | 1597 | */ |
kevman | 0:38ceb79fef03 | 1598 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
kevman | 0:38ceb79fef03 | 1599 | { |
kevman | 0:38ceb79fef03 | 1600 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
kevman | 0:38ceb79fef03 | 1601 | uint32_t PreemptPriorityBits; |
kevman | 0:38ceb79fef03 | 1602 | uint32_t SubPriorityBits; |
kevman | 0:38ceb79fef03 | 1603 | |
kevman | 0:38ceb79fef03 | 1604 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
kevman | 0:38ceb79fef03 | 1605 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
kevman | 0:38ceb79fef03 | 1606 | |
kevman | 0:38ceb79fef03 | 1607 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
kevman | 0:38ceb79fef03 | 1608 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
kevman | 0:38ceb79fef03 | 1609 | } |
kevman | 0:38ceb79fef03 | 1610 | |
kevman | 0:38ceb79fef03 | 1611 | |
kevman | 0:38ceb79fef03 | 1612 | /** |
kevman | 0:38ceb79fef03 | 1613 | \brief Set Interrupt Vector |
kevman | 0:38ceb79fef03 | 1614 | \details Sets an interrupt vector in SRAM based interrupt vector table. |
kevman | 0:38ceb79fef03 | 1615 | The interrupt number can be positive to specify a device specific interrupt, |
kevman | 0:38ceb79fef03 | 1616 | or negative to specify a processor exception. |
kevman | 0:38ceb79fef03 | 1617 | VTOR must been relocated to SRAM before. |
kevman | 0:38ceb79fef03 | 1618 | If VTOR is not present address 0 must be mapped to SRAM. |
kevman | 0:38ceb79fef03 | 1619 | \param [in] IRQn Interrupt number |
kevman | 0:38ceb79fef03 | 1620 | \param [in] vector Address of interrupt handler function |
kevman | 0:38ceb79fef03 | 1621 | */ |
kevman | 0:38ceb79fef03 | 1622 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
kevman | 0:38ceb79fef03 | 1623 | { |
kevman | 0:38ceb79fef03 | 1624 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 1625 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
kevman | 0:38ceb79fef03 | 1626 | #else |
kevman | 0:38ceb79fef03 | 1627 | uint32_t *vectors = (uint32_t *)0x0U; |
kevman | 0:38ceb79fef03 | 1628 | #endif |
kevman | 0:38ceb79fef03 | 1629 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
kevman | 0:38ceb79fef03 | 1630 | } |
kevman | 0:38ceb79fef03 | 1631 | |
kevman | 0:38ceb79fef03 | 1632 | |
kevman | 0:38ceb79fef03 | 1633 | /** |
kevman | 0:38ceb79fef03 | 1634 | \brief Get Interrupt Vector |
kevman | 0:38ceb79fef03 | 1635 | \details Reads an interrupt vector from interrupt vector table. |
kevman | 0:38ceb79fef03 | 1636 | The interrupt number can be positive to specify a device specific interrupt, |
kevman | 0:38ceb79fef03 | 1637 | or negative to specify a processor exception. |
kevman | 0:38ceb79fef03 | 1638 | \param [in] IRQn Interrupt number. |
kevman | 0:38ceb79fef03 | 1639 | \return Address of interrupt handler function |
kevman | 0:38ceb79fef03 | 1640 | */ |
kevman | 0:38ceb79fef03 | 1641 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1642 | { |
kevman | 0:38ceb79fef03 | 1643 | #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 1644 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
kevman | 0:38ceb79fef03 | 1645 | #else |
kevman | 0:38ceb79fef03 | 1646 | uint32_t *vectors = (uint32_t *)0x0U; |
kevman | 0:38ceb79fef03 | 1647 | #endif |
kevman | 0:38ceb79fef03 | 1648 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
kevman | 0:38ceb79fef03 | 1649 | } |
kevman | 0:38ceb79fef03 | 1650 | |
kevman | 0:38ceb79fef03 | 1651 | |
kevman | 0:38ceb79fef03 | 1652 | /** |
kevman | 0:38ceb79fef03 | 1653 | \brief System Reset |
kevman | 0:38ceb79fef03 | 1654 | \details Initiates a system reset request to reset the MCU. |
kevman | 0:38ceb79fef03 | 1655 | */ |
kevman | 0:38ceb79fef03 | 1656 | __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) |
kevman | 0:38ceb79fef03 | 1657 | { |
kevman | 0:38ceb79fef03 | 1658 | __DSB(); /* Ensure all outstanding memory accesses included |
kevman | 0:38ceb79fef03 | 1659 | buffered write are completed before reset */ |
kevman | 0:38ceb79fef03 | 1660 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
kevman | 0:38ceb79fef03 | 1661 | SCB_AIRCR_SYSRESETREQ_Msk); |
kevman | 0:38ceb79fef03 | 1662 | __DSB(); /* Ensure completion of memory access */ |
kevman | 0:38ceb79fef03 | 1663 | |
kevman | 0:38ceb79fef03 | 1664 | for(;;) /* wait until reset */ |
kevman | 0:38ceb79fef03 | 1665 | { |
kevman | 0:38ceb79fef03 | 1666 | __NOP(); |
kevman | 0:38ceb79fef03 | 1667 | } |
kevman | 0:38ceb79fef03 | 1668 | } |
kevman | 0:38ceb79fef03 | 1669 | |
kevman | 0:38ceb79fef03 | 1670 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
kevman | 0:38ceb79fef03 | 1671 | /** |
kevman | 0:38ceb79fef03 | 1672 | \brief Enable Interrupt (non-secure) |
kevman | 0:38ceb79fef03 | 1673 | \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. |
kevman | 0:38ceb79fef03 | 1674 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1675 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1676 | */ |
kevman | 0:38ceb79fef03 | 1677 | __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1678 | { |
kevman | 0:38ceb79fef03 | 1679 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1680 | { |
kevman | 0:38ceb79fef03 | 1681 | NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kevman | 0:38ceb79fef03 | 1682 | } |
kevman | 0:38ceb79fef03 | 1683 | } |
kevman | 0:38ceb79fef03 | 1684 | |
kevman | 0:38ceb79fef03 | 1685 | |
kevman | 0:38ceb79fef03 | 1686 | /** |
kevman | 0:38ceb79fef03 | 1687 | \brief Get Interrupt Enable status (non-secure) |
kevman | 0:38ceb79fef03 | 1688 | \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. |
kevman | 0:38ceb79fef03 | 1689 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1690 | \return 0 Interrupt is not enabled. |
kevman | 0:38ceb79fef03 | 1691 | \return 1 Interrupt is enabled. |
kevman | 0:38ceb79fef03 | 1692 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1693 | */ |
kevman | 0:38ceb79fef03 | 1694 | __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1695 | { |
kevman | 0:38ceb79fef03 | 1696 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1697 | { |
kevman | 0:38ceb79fef03 | 1698 | return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1699 | } |
kevman | 0:38ceb79fef03 | 1700 | else |
kevman | 0:38ceb79fef03 | 1701 | { |
kevman | 0:38ceb79fef03 | 1702 | return(0U); |
kevman | 0:38ceb79fef03 | 1703 | } |
kevman | 0:38ceb79fef03 | 1704 | } |
kevman | 0:38ceb79fef03 | 1705 | |
kevman | 0:38ceb79fef03 | 1706 | |
kevman | 0:38ceb79fef03 | 1707 | /** |
kevman | 0:38ceb79fef03 | 1708 | \brief Disable Interrupt (non-secure) |
kevman | 0:38ceb79fef03 | 1709 | \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. |
kevman | 0:38ceb79fef03 | 1710 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1711 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1712 | */ |
kevman | 0:38ceb79fef03 | 1713 | __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1714 | { |
kevman | 0:38ceb79fef03 | 1715 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1716 | { |
kevman | 0:38ceb79fef03 | 1717 | NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kevman | 0:38ceb79fef03 | 1718 | } |
kevman | 0:38ceb79fef03 | 1719 | } |
kevman | 0:38ceb79fef03 | 1720 | |
kevman | 0:38ceb79fef03 | 1721 | |
kevman | 0:38ceb79fef03 | 1722 | /** |
kevman | 0:38ceb79fef03 | 1723 | \brief Get Pending Interrupt (non-secure) |
kevman | 0:38ceb79fef03 | 1724 | \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. |
kevman | 0:38ceb79fef03 | 1725 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1726 | \return 0 Interrupt status is not pending. |
kevman | 0:38ceb79fef03 | 1727 | \return 1 Interrupt status is pending. |
kevman | 0:38ceb79fef03 | 1728 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1729 | */ |
kevman | 0:38ceb79fef03 | 1730 | __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1731 | { |
kevman | 0:38ceb79fef03 | 1732 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1733 | { |
kevman | 0:38ceb79fef03 | 1734 | return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1735 | } |
kevman | 0:38ceb79fef03 | 1736 | else |
kevman | 0:38ceb79fef03 | 1737 | { |
kevman | 0:38ceb79fef03 | 1738 | return(0U); |
kevman | 0:38ceb79fef03 | 1739 | } |
kevman | 0:38ceb79fef03 | 1740 | } |
kevman | 0:38ceb79fef03 | 1741 | |
kevman | 0:38ceb79fef03 | 1742 | |
kevman | 0:38ceb79fef03 | 1743 | /** |
kevman | 0:38ceb79fef03 | 1744 | \brief Set Pending Interrupt (non-secure) |
kevman | 0:38ceb79fef03 | 1745 | \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. |
kevman | 0:38ceb79fef03 | 1746 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1747 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1748 | */ |
kevman | 0:38ceb79fef03 | 1749 | __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1750 | { |
kevman | 0:38ceb79fef03 | 1751 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1752 | { |
kevman | 0:38ceb79fef03 | 1753 | NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kevman | 0:38ceb79fef03 | 1754 | } |
kevman | 0:38ceb79fef03 | 1755 | } |
kevman | 0:38ceb79fef03 | 1756 | |
kevman | 0:38ceb79fef03 | 1757 | |
kevman | 0:38ceb79fef03 | 1758 | /** |
kevman | 0:38ceb79fef03 | 1759 | \brief Clear Pending Interrupt (non-secure) |
kevman | 0:38ceb79fef03 | 1760 | \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. |
kevman | 0:38ceb79fef03 | 1761 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1762 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1763 | */ |
kevman | 0:38ceb79fef03 | 1764 | __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1765 | { |
kevman | 0:38ceb79fef03 | 1766 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1767 | { |
kevman | 0:38ceb79fef03 | 1768 | NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); |
kevman | 0:38ceb79fef03 | 1769 | } |
kevman | 0:38ceb79fef03 | 1770 | } |
kevman | 0:38ceb79fef03 | 1771 | |
kevman | 0:38ceb79fef03 | 1772 | |
kevman | 0:38ceb79fef03 | 1773 | /** |
kevman | 0:38ceb79fef03 | 1774 | \brief Get Active Interrupt (non-secure) |
kevman | 0:38ceb79fef03 | 1775 | \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. |
kevman | 0:38ceb79fef03 | 1776 | \param [in] IRQn Device specific interrupt number. |
kevman | 0:38ceb79fef03 | 1777 | \return 0 Interrupt status is not active. |
kevman | 0:38ceb79fef03 | 1778 | \return 1 Interrupt status is active. |
kevman | 0:38ceb79fef03 | 1779 | \note IRQn must not be negative. |
kevman | 0:38ceb79fef03 | 1780 | */ |
kevman | 0:38ceb79fef03 | 1781 | __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1782 | { |
kevman | 0:38ceb79fef03 | 1783 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1784 | { |
kevman | 0:38ceb79fef03 | 1785 | return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
kevman | 0:38ceb79fef03 | 1786 | } |
kevman | 0:38ceb79fef03 | 1787 | else |
kevman | 0:38ceb79fef03 | 1788 | { |
kevman | 0:38ceb79fef03 | 1789 | return(0U); |
kevman | 0:38ceb79fef03 | 1790 | } |
kevman | 0:38ceb79fef03 | 1791 | } |
kevman | 0:38ceb79fef03 | 1792 | |
kevman | 0:38ceb79fef03 | 1793 | |
kevman | 0:38ceb79fef03 | 1794 | /** |
kevman | 0:38ceb79fef03 | 1795 | \brief Set Interrupt Priority (non-secure) |
kevman | 0:38ceb79fef03 | 1796 | \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. |
kevman | 0:38ceb79fef03 | 1797 | The interrupt number can be positive to specify a device specific interrupt, |
kevman | 0:38ceb79fef03 | 1798 | or negative to specify a processor exception. |
kevman | 0:38ceb79fef03 | 1799 | \param [in] IRQn Interrupt number. |
kevman | 0:38ceb79fef03 | 1800 | \param [in] priority Priority to set. |
kevman | 0:38ceb79fef03 | 1801 | \note The priority cannot be set for every non-secure processor exception. |
kevman | 0:38ceb79fef03 | 1802 | */ |
kevman | 0:38ceb79fef03 | 1803 | __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) |
kevman | 0:38ceb79fef03 | 1804 | { |
kevman | 0:38ceb79fef03 | 1805 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1806 | { |
kevman | 0:38ceb79fef03 | 1807 | NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
kevman | 0:38ceb79fef03 | 1808 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
kevman | 0:38ceb79fef03 | 1809 | } |
kevman | 0:38ceb79fef03 | 1810 | else |
kevman | 0:38ceb79fef03 | 1811 | { |
kevman | 0:38ceb79fef03 | 1812 | SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
kevman | 0:38ceb79fef03 | 1813 | (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
kevman | 0:38ceb79fef03 | 1814 | } |
kevman | 0:38ceb79fef03 | 1815 | } |
kevman | 0:38ceb79fef03 | 1816 | |
kevman | 0:38ceb79fef03 | 1817 | |
kevman | 0:38ceb79fef03 | 1818 | /** |
kevman | 0:38ceb79fef03 | 1819 | \brief Get Interrupt Priority (non-secure) |
kevman | 0:38ceb79fef03 | 1820 | \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. |
kevman | 0:38ceb79fef03 | 1821 | The interrupt number can be positive to specify a device specific interrupt, |
kevman | 0:38ceb79fef03 | 1822 | or negative to specify a processor exception. |
kevman | 0:38ceb79fef03 | 1823 | \param [in] IRQn Interrupt number. |
kevman | 0:38ceb79fef03 | 1824 | \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. |
kevman | 0:38ceb79fef03 | 1825 | */ |
kevman | 0:38ceb79fef03 | 1826 | __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) |
kevman | 0:38ceb79fef03 | 1827 | { |
kevman | 0:38ceb79fef03 | 1828 | |
kevman | 0:38ceb79fef03 | 1829 | if ((int32_t)(IRQn) >= 0) |
kevman | 0:38ceb79fef03 | 1830 | { |
kevman | 0:38ceb79fef03 | 1831 | return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
kevman | 0:38ceb79fef03 | 1832 | } |
kevman | 0:38ceb79fef03 | 1833 | else |
kevman | 0:38ceb79fef03 | 1834 | { |
kevman | 0:38ceb79fef03 | 1835 | return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); |
kevman | 0:38ceb79fef03 | 1836 | } |
kevman | 0:38ceb79fef03 | 1837 | } |
kevman | 0:38ceb79fef03 | 1838 | #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ |
kevman | 0:38ceb79fef03 | 1839 | |
kevman | 0:38ceb79fef03 | 1840 | /*@} end of CMSIS_Core_NVICFunctions */ |
kevman | 0:38ceb79fef03 | 1841 | |
kevman | 0:38ceb79fef03 | 1842 | /* ########################## MPU functions #################################### */ |
kevman | 0:38ceb79fef03 | 1843 | |
kevman | 0:38ceb79fef03 | 1844 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
kevman | 0:38ceb79fef03 | 1845 | |
kevman | 0:38ceb79fef03 | 1846 | #include "mpu_armv8.h" |
kevman | 0:38ceb79fef03 | 1847 | |
kevman | 0:38ceb79fef03 | 1848 | #endif |
kevman | 0:38ceb79fef03 | 1849 | |
kevman | 0:38ceb79fef03 | 1850 | /* ########################## FPU functions #################################### */ |
kevman | 0:38ceb79fef03 | 1851 | /** |
kevman | 0:38ceb79fef03 | 1852 | \ingroup CMSIS_Core_FunctionInterface |
kevman | 0:38ceb79fef03 | 1853 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
kevman | 0:38ceb79fef03 | 1854 | \brief Function that provides FPU type. |
kevman | 0:38ceb79fef03 | 1855 | @{ |
kevman | 0:38ceb79fef03 | 1856 | */ |
kevman | 0:38ceb79fef03 | 1857 | |
kevman | 0:38ceb79fef03 | 1858 | /** |
kevman | 0:38ceb79fef03 | 1859 | \brief get FPU type |
kevman | 0:38ceb79fef03 | 1860 | \details returns the FPU type |
kevman | 0:38ceb79fef03 | 1861 | \returns |
kevman | 0:38ceb79fef03 | 1862 | - \b 0: No FPU |
kevman | 0:38ceb79fef03 | 1863 | - \b 1: Single precision FPU |
kevman | 0:38ceb79fef03 | 1864 | - \b 2: Double + Single precision FPU |
kevman | 0:38ceb79fef03 | 1865 | */ |
kevman | 0:38ceb79fef03 | 1866 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
kevman | 0:38ceb79fef03 | 1867 | { |
kevman | 0:38ceb79fef03 | 1868 | return 0U; /* No FPU */ |
kevman | 0:38ceb79fef03 | 1869 | } |
kevman | 0:38ceb79fef03 | 1870 | |
kevman | 0:38ceb79fef03 | 1871 | |
kevman | 0:38ceb79fef03 | 1872 | /*@} end of CMSIS_Core_FpuFunctions */ |
kevman | 0:38ceb79fef03 | 1873 | |
kevman | 0:38ceb79fef03 | 1874 | |
kevman | 0:38ceb79fef03 | 1875 | |
kevman | 0:38ceb79fef03 | 1876 | /* ########################## SAU functions #################################### */ |
kevman | 0:38ceb79fef03 | 1877 | /** |
kevman | 0:38ceb79fef03 | 1878 | \ingroup CMSIS_Core_FunctionInterface |
kevman | 0:38ceb79fef03 | 1879 | \defgroup CMSIS_Core_SAUFunctions SAU Functions |
kevman | 0:38ceb79fef03 | 1880 | \brief Functions that configure the SAU. |
kevman | 0:38ceb79fef03 | 1881 | @{ |
kevman | 0:38ceb79fef03 | 1882 | */ |
kevman | 0:38ceb79fef03 | 1883 | |
kevman | 0:38ceb79fef03 | 1884 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
kevman | 0:38ceb79fef03 | 1885 | |
kevman | 0:38ceb79fef03 | 1886 | /** |
kevman | 0:38ceb79fef03 | 1887 | \brief Enable SAU |
kevman | 0:38ceb79fef03 | 1888 | \details Enables the Security Attribution Unit (SAU). |
kevman | 0:38ceb79fef03 | 1889 | */ |
kevman | 0:38ceb79fef03 | 1890 | __STATIC_INLINE void TZ_SAU_Enable(void) |
kevman | 0:38ceb79fef03 | 1891 | { |
kevman | 0:38ceb79fef03 | 1892 | SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); |
kevman | 0:38ceb79fef03 | 1893 | } |
kevman | 0:38ceb79fef03 | 1894 | |
kevman | 0:38ceb79fef03 | 1895 | |
kevman | 0:38ceb79fef03 | 1896 | |
kevman | 0:38ceb79fef03 | 1897 | /** |
kevman | 0:38ceb79fef03 | 1898 | \brief Disable SAU |
kevman | 0:38ceb79fef03 | 1899 | \details Disables the Security Attribution Unit (SAU). |
kevman | 0:38ceb79fef03 | 1900 | */ |
kevman | 0:38ceb79fef03 | 1901 | __STATIC_INLINE void TZ_SAU_Disable(void) |
kevman | 0:38ceb79fef03 | 1902 | { |
kevman | 0:38ceb79fef03 | 1903 | SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); |
kevman | 0:38ceb79fef03 | 1904 | } |
kevman | 0:38ceb79fef03 | 1905 | |
kevman | 0:38ceb79fef03 | 1906 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
kevman | 0:38ceb79fef03 | 1907 | |
kevman | 0:38ceb79fef03 | 1908 | /*@} end of CMSIS_Core_SAUFunctions */ |
kevman | 0:38ceb79fef03 | 1909 | |
kevman | 0:38ceb79fef03 | 1910 | |
kevman | 0:38ceb79fef03 | 1911 | |
kevman | 0:38ceb79fef03 | 1912 | |
kevman | 0:38ceb79fef03 | 1913 | /* ################################## SysTick function ############################################ */ |
kevman | 0:38ceb79fef03 | 1914 | /** |
kevman | 0:38ceb79fef03 | 1915 | \ingroup CMSIS_Core_FunctionInterface |
kevman | 0:38ceb79fef03 | 1916 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
kevman | 0:38ceb79fef03 | 1917 | \brief Functions that configure the System. |
kevman | 0:38ceb79fef03 | 1918 | @{ |
kevman | 0:38ceb79fef03 | 1919 | */ |
kevman | 0:38ceb79fef03 | 1920 | |
kevman | 0:38ceb79fef03 | 1921 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
kevman | 0:38ceb79fef03 | 1922 | |
kevman | 0:38ceb79fef03 | 1923 | /** |
kevman | 0:38ceb79fef03 | 1924 | \brief System Tick Configuration |
kevman | 0:38ceb79fef03 | 1925 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
kevman | 0:38ceb79fef03 | 1926 | Counter is in free running mode to generate periodic interrupts. |
kevman | 0:38ceb79fef03 | 1927 | \param [in] ticks Number of ticks between two interrupts. |
kevman | 0:38ceb79fef03 | 1928 | \return 0 Function succeeded. |
kevman | 0:38ceb79fef03 | 1929 | \return 1 Function failed. |
kevman | 0:38ceb79fef03 | 1930 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
kevman | 0:38ceb79fef03 | 1931 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
kevman | 0:38ceb79fef03 | 1932 | must contain a vendor-specific implementation of this function. |
kevman | 0:38ceb79fef03 | 1933 | */ |
kevman | 0:38ceb79fef03 | 1934 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
kevman | 0:38ceb79fef03 | 1935 | { |
kevman | 0:38ceb79fef03 | 1936 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
kevman | 0:38ceb79fef03 | 1937 | { |
kevman | 0:38ceb79fef03 | 1938 | return (1UL); /* Reload value impossible */ |
kevman | 0:38ceb79fef03 | 1939 | } |
kevman | 0:38ceb79fef03 | 1940 | |
kevman | 0:38ceb79fef03 | 1941 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
kevman | 0:38ceb79fef03 | 1942 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
kevman | 0:38ceb79fef03 | 1943 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
kevman | 0:38ceb79fef03 | 1944 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
kevman | 0:38ceb79fef03 | 1945 | SysTick_CTRL_TICKINT_Msk | |
kevman | 0:38ceb79fef03 | 1946 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
kevman | 0:38ceb79fef03 | 1947 | return (0UL); /* Function successful */ |
kevman | 0:38ceb79fef03 | 1948 | } |
kevman | 0:38ceb79fef03 | 1949 | |
kevman | 0:38ceb79fef03 | 1950 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
kevman | 0:38ceb79fef03 | 1951 | /** |
kevman | 0:38ceb79fef03 | 1952 | \brief System Tick Configuration (non-secure) |
kevman | 0:38ceb79fef03 | 1953 | \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. |
kevman | 0:38ceb79fef03 | 1954 | Counter is in free running mode to generate periodic interrupts. |
kevman | 0:38ceb79fef03 | 1955 | \param [in] ticks Number of ticks between two interrupts. |
kevman | 0:38ceb79fef03 | 1956 | \return 0 Function succeeded. |
kevman | 0:38ceb79fef03 | 1957 | \return 1 Function failed. |
kevman | 0:38ceb79fef03 | 1958 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
kevman | 0:38ceb79fef03 | 1959 | function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> |
kevman | 0:38ceb79fef03 | 1960 | must contain a vendor-specific implementation of this function. |
kevman | 0:38ceb79fef03 | 1961 | |
kevman | 0:38ceb79fef03 | 1962 | */ |
kevman | 0:38ceb79fef03 | 1963 | __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) |
kevman | 0:38ceb79fef03 | 1964 | { |
kevman | 0:38ceb79fef03 | 1965 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
kevman | 0:38ceb79fef03 | 1966 | { |
kevman | 0:38ceb79fef03 | 1967 | return (1UL); /* Reload value impossible */ |
kevman | 0:38ceb79fef03 | 1968 | } |
kevman | 0:38ceb79fef03 | 1969 | |
kevman | 0:38ceb79fef03 | 1970 | SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
kevman | 0:38ceb79fef03 | 1971 | TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
kevman | 0:38ceb79fef03 | 1972 | SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ |
kevman | 0:38ceb79fef03 | 1973 | SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
kevman | 0:38ceb79fef03 | 1974 | SysTick_CTRL_TICKINT_Msk | |
kevman | 0:38ceb79fef03 | 1975 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
kevman | 0:38ceb79fef03 | 1976 | return (0UL); /* Function successful */ |
kevman | 0:38ceb79fef03 | 1977 | } |
kevman | 0:38ceb79fef03 | 1978 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
kevman | 0:38ceb79fef03 | 1979 | |
kevman | 0:38ceb79fef03 | 1980 | #endif |
kevman | 0:38ceb79fef03 | 1981 | |
kevman | 0:38ceb79fef03 | 1982 | /*@} end of CMSIS_Core_SysTickFunctions */ |
kevman | 0:38ceb79fef03 | 1983 | |
kevman | 0:38ceb79fef03 | 1984 | |
kevman | 0:38ceb79fef03 | 1985 | |
kevman | 0:38ceb79fef03 | 1986 | |
kevman | 0:38ceb79fef03 | 1987 | #ifdef __cplusplus |
kevman | 0:38ceb79fef03 | 1988 | } |
kevman | 0:38ceb79fef03 | 1989 | #endif |
kevman | 0:38ceb79fef03 | 1990 | |
kevman | 0:38ceb79fef03 | 1991 | #endif /* __CORE_CM23_H_DEPENDANT */ |
kevman | 0:38ceb79fef03 | 1992 | |
kevman | 0:38ceb79fef03 | 1993 | #endif /* __CMSIS_GENERIC */ |