Kev Mann / mbed-dev-OS5_10_4

RTC auf true

components/802_15_4_RF/mcr20a-rf-driver/source/MCR20Reg.h@2:7aab896b1a3b, 2019-03-13 (annotated)

Committer:
kevman
Date:
Wed Mar 13 11:03:24 2019 +0000
Revision:
2:7aab896b1a3b
2019-03-13

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kevman 2:7aab896b1a3b 1 /*!
kevman 2:7aab896b1a3b 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
kevman 2:7aab896b1a3b 3 * All rights reserved.
kevman 2:7aab896b1a3b 4 *
kevman 2:7aab896b1a3b 5 * \file MCR20reg.h
kevman 2:7aab896b1a3b 6 * MCR20 Registers
kevman 2:7aab896b1a3b 7 *
kevman 2:7aab896b1a3b 8 * Redistribution and use in source and binary forms, with or without modification,
kevman 2:7aab896b1a3b 9 * are permitted provided that the following conditions are met:
kevman 2:7aab896b1a3b 10 *
kevman 2:7aab896b1a3b 11 * o Redistributions of source code must retain the above copyright notice, this list
kevman 2:7aab896b1a3b 12 * of conditions and the following disclaimer.
kevman 2:7aab896b1a3b 13 *
kevman 2:7aab896b1a3b 14 * o Redistributions in binary form must reproduce the above copyright notice, this
kevman 2:7aab896b1a3b 15 * list of conditions and the following disclaimer in the documentation and/or
kevman 2:7aab896b1a3b 16 * other materials provided with the distribution.
kevman 2:7aab896b1a3b 17 *
kevman 2:7aab896b1a3b 18 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
kevman 2:7aab896b1a3b 19 * contributors may be used to endorse or promote products derived from this
kevman 2:7aab896b1a3b 20 * software without specific prior written permission.
kevman 2:7aab896b1a3b 21 *
kevman 2:7aab896b1a3b 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
kevman 2:7aab896b1a3b 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
kevman 2:7aab896b1a3b 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
kevman 2:7aab896b1a3b 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
kevman 2:7aab896b1a3b 26 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
kevman 2:7aab896b1a3b 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
kevman 2:7aab896b1a3b 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
kevman 2:7aab896b1a3b 29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
kevman 2:7aab896b1a3b 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
kevman 2:7aab896b1a3b 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
kevman 2:7aab896b1a3b 32 */
kevman 2:7aab896b1a3b 33
kevman 2:7aab896b1a3b 34 #ifndef __MCR20_REG_H__
kevman 2:7aab896b1a3b 35 #define __MCR20_REG_H__
kevman 2:7aab896b1a3b 36 /*****************************************************************************
kevman 2:7aab896b1a3b 37 * INCLUDED HEADERS *
kevman 2:7aab896b1a3b 38 *---------------------------------------------------------------------------*
kevman 2:7aab896b1a3b 39 * Add to this section all the headers that this module needs to include. *
kevman 2:7aab896b1a3b 40 * Note that it is not a good practice to include header files into header *
kevman 2:7aab896b1a3b 41 * files, so use this section only if there is no other better solution. *
kevman 2:7aab896b1a3b 42 *---------------------------------------------------------------------------*
kevman 2:7aab896b1a3b 43 *****************************************************************************/
kevman 2:7aab896b1a3b 44
kevman 2:7aab896b1a3b 45 /****************************************************************************/
kevman 2:7aab896b1a3b 46 /* Transceiver SPI Registers */
kevman 2:7aab896b1a3b 47 /****************************************************************************/
kevman 2:7aab896b1a3b 48
kevman 2:7aab896b1a3b 49 #define TransceiverSPI_IARIndexReg (0x3E)
kevman 2:7aab896b1a3b 50
kevman 2:7aab896b1a3b 51 #define TransceiverSPI_ReadSelect (1<<7)
kevman 2:7aab896b1a3b 52 #define TransceiverSPI_WriteSelect (0<<7)
kevman 2:7aab896b1a3b 53 #define TransceiverSPI_RegisterAccessSelect (0<<6)
kevman 2:7aab896b1a3b 54 #define TransceiverSPI_PacketBuffAccessSelect (1<<6)
kevman 2:7aab896b1a3b 55 #define TransceiverSPI_PacketBuffBurstModeSelect (0<<5)
kevman 2:7aab896b1a3b 56 #define TransceiverSPI_PacketBuffByteModeSelect (1<<5)
kevman 2:7aab896b1a3b 57
kevman 2:7aab896b1a3b 58 #define TransceiverSPI_DirectRegisterAddressMask (0x3F)
kevman 2:7aab896b1a3b 59
kevman 2:7aab896b1a3b 60 #define IRQSTS1 0x00
kevman 2:7aab896b1a3b 61 #define IRQSTS2 0x01
kevman 2:7aab896b1a3b 62 #define IRQSTS3 0x02
kevman 2:7aab896b1a3b 63 #define PHY_CTRL1 0x03
kevman 2:7aab896b1a3b 64 #define PHY_CTRL2 0x04
kevman 2:7aab896b1a3b 65 #define PHY_CTRL3 0x05
kevman 2:7aab896b1a3b 66 #define RX_FRM_LEN 0x06
kevman 2:7aab896b1a3b 67 #define PHY_CTRL4 0x07
kevman 2:7aab896b1a3b 68 #define SRC_CTRL 0x08
kevman 2:7aab896b1a3b 69 #define SRC_ADDRS_SUM_LSB 0x09
kevman 2:7aab896b1a3b 70 #define SRC_ADDRS_SUM_MSB 0x0A
kevman 2:7aab896b1a3b 71 #define CCA1_ED_FNL 0x0B
kevman 2:7aab896b1a3b 72 #define EVENT_TMR_LSB 0x0C
kevman 2:7aab896b1a3b 73 #define EVENT_TMR_MSB 0x0D
kevman 2:7aab896b1a3b 74 #define EVENT_TMR_USB 0x0E
kevman 2:7aab896b1a3b 75 #define TIMESTAMP_LSB 0x0F
kevman 2:7aab896b1a3b 76 #define TIMESTAMP_MSB 0x10
kevman 2:7aab896b1a3b 77 #define TIMESTAMP_USB 0x11
kevman 2:7aab896b1a3b 78 #define T3CMP_LSB 0x12
kevman 2:7aab896b1a3b 79 #define T3CMP_MSB 0x13
kevman 2:7aab896b1a3b 80 #define T3CMP_USB 0x14
kevman 2:7aab896b1a3b 81 #define T2PRIMECMP_LSB 0x15
kevman 2:7aab896b1a3b 82 #define T2PRIMECMP_MSB 0x16
kevman 2:7aab896b1a3b 83 #define T1CMP_LSB 0x17
kevman 2:7aab896b1a3b 84 #define T1CMP_MSB 0x18
kevman 2:7aab896b1a3b 85 #define T1CMP_USB 0x19
kevman 2:7aab896b1a3b 86 #define T2CMP_LSB 0x1A
kevman 2:7aab896b1a3b 87 #define T2CMP_MSB 0x1B
kevman 2:7aab896b1a3b 88 #define T2CMP_USB 0x1C
kevman 2:7aab896b1a3b 89 #define T4CMP_LSB 0x1D
kevman 2:7aab896b1a3b 90 #define T4CMP_MSB 0x1E
kevman 2:7aab896b1a3b 91 #define T4CMP_USB 0x1F
kevman 2:7aab896b1a3b 92 #define PLL_INT0 0x20
kevman 2:7aab896b1a3b 93 #define PLL_FRAC0_LSB 0x21
kevman 2:7aab896b1a3b 94 #define PLL_FRAC0_MSB 0x22
kevman 2:7aab896b1a3b 95 #define PA_PWR 0x23
kevman 2:7aab896b1a3b 96 #define SEQ_STATE 0x24
kevman 2:7aab896b1a3b 97 #define LQI_VALUE 0x25
kevman 2:7aab896b1a3b 98 #define RSSI_CCA_CONT 0x26
kevman 2:7aab896b1a3b 99 //-------------- 0x27
kevman 2:7aab896b1a3b 100 #define ASM_CTRL1 0x28
kevman 2:7aab896b1a3b 101 #define ASM_CTRL2 0x29
kevman 2:7aab896b1a3b 102 #define ASM_DATA_0 0x2A
kevman 2:7aab896b1a3b 103 #define ASM_DATA_1 0x2B
kevman 2:7aab896b1a3b 104 #define ASM_DATA_2 0x2C
kevman 2:7aab896b1a3b 105 #define ASM_DATA_3 0x2D
kevman 2:7aab896b1a3b 106 #define ASM_DATA_4 0x2E
kevman 2:7aab896b1a3b 107 #define ASM_DATA_5 0x2F
kevman 2:7aab896b1a3b 108 #define ASM_DATA_6 0x30
kevman 2:7aab896b1a3b 109 #define ASM_DATA_7 0x31
kevman 2:7aab896b1a3b 110 #define ASM_DATA_8 0x32
kevman 2:7aab896b1a3b 111 #define ASM_DATA_9 0x33
kevman 2:7aab896b1a3b 112 #define ASM_DATA_A 0x34
kevman 2:7aab896b1a3b 113 #define ASM_DATA_B 0x35
kevman 2:7aab896b1a3b 114 #define ASM_DATA_C 0x36
kevman 2:7aab896b1a3b 115 #define ASM_DATA_D 0x37
kevman 2:7aab896b1a3b 116 #define ASM_DATA_E 0x38
kevman 2:7aab896b1a3b 117 #define ASM_DATA_F 0x39
kevman 2:7aab896b1a3b 118 //------------------- 0x3A
kevman 2:7aab896b1a3b 119 #define OVERWRITE_VER 0x3B
kevman 2:7aab896b1a3b 120 #define CLK_OUT_CTRL 0x3C
kevman 2:7aab896b1a3b 121 #define PWR_MODES 0x3D
kevman 2:7aab896b1a3b 122 #define IAR_INDEX 0x3E
kevman 2:7aab896b1a3b 123 #define IAR_DATA 0x3F
kevman 2:7aab896b1a3b 124
kevman 2:7aab896b1a3b 125
kevman 2:7aab896b1a3b 126 #define PART_ID 0x00
kevman 2:7aab896b1a3b 127 #define XTAL_TRIM 0x01
kevman 2:7aab896b1a3b 128 #define PMC_LP_TRIM 0x02
kevman 2:7aab896b1a3b 129 #define MACPANID0_LSB 0x03
kevman 2:7aab896b1a3b 130 #define MACPANID0_MSB 0x04
kevman 2:7aab896b1a3b 131 #define MACSHORTADDRS0_LSB 0x05
kevman 2:7aab896b1a3b 132 #define MACSHORTADDRS0_MSB 0x06
kevman 2:7aab896b1a3b 133 #define MACLONGADDRS0_0 0x07
kevman 2:7aab896b1a3b 134 #define MACLONGADDRS0_8 0x08
kevman 2:7aab896b1a3b 135 #define MACLONGADDRS0_16 0x09
kevman 2:7aab896b1a3b 136 #define MACLONGADDRS0_24 0x0A
kevman 2:7aab896b1a3b 137 #define MACLONGADDRS0_32 0x0B
kevman 2:7aab896b1a3b 138 #define MACLONGADDRS0_40 0x0C
kevman 2:7aab896b1a3b 139 #define MACLONGADDRS0_48 0x0D
kevman 2:7aab896b1a3b 140 #define MACLONGADDRS0_56 0x0E
kevman 2:7aab896b1a3b 141 #define RX_FRAME_FILTER 0x0F
kevman 2:7aab896b1a3b 142 #define PLL_INT1 0x10
kevman 2:7aab896b1a3b 143 #define PLL_FRAC1_LSB 0x11
kevman 2:7aab896b1a3b 144 #define PLL_FRAC1_MSB 0x12
kevman 2:7aab896b1a3b 145 #define MACPANID1_LSB 0x13
kevman 2:7aab896b1a3b 146 #define MACPANID1_MSB 0x14
kevman 2:7aab896b1a3b 147 #define MACSHORTADDRS1_LSB 0x15
kevman 2:7aab896b1a3b 148 #define MACSHORTADDRS1_MSB 0x16
kevman 2:7aab896b1a3b 149 #define MACLONGADDRS1_0 0x17
kevman 2:7aab896b1a3b 150 #define MACLONGADDRS1_8 0x18
kevman 2:7aab896b1a3b 151 #define MACLONGADDRS1_16 0x19
kevman 2:7aab896b1a3b 152 #define MACLONGADDRS1_24 0x1A
kevman 2:7aab896b1a3b 153 #define MACLONGADDRS1_32 0x1B
kevman 2:7aab896b1a3b 154 #define MACLONGADDRS1_40 0x1C
kevman 2:7aab896b1a3b 155 #define MACLONGADDRS1_48 0x1D
kevman 2:7aab896b1a3b 156 #define MACLONGADDRS1_56 0x1E
kevman 2:7aab896b1a3b 157 #define DUAL_PAN_CTRL 0x1F
kevman 2:7aab896b1a3b 158 #define DUAL_PAN_DWELL 0x20
kevman 2:7aab896b1a3b 159 #define DUAL_PAN_STS 0x21
kevman 2:7aab896b1a3b 160 #define CCA1_THRESH 0x22
kevman 2:7aab896b1a3b 161 #define CCA1_ED_OFFSET_COMP 0x23
kevman 2:7aab896b1a3b 162 #define LQI_OFFSET_COMP 0x24
kevman 2:7aab896b1a3b 163 #define CCA_CTRL 0x25
kevman 2:7aab896b1a3b 164 #define CCA2_CORR_PEAKS 0x26
kevman 2:7aab896b1a3b 165 #define CCA2_CORR_THRESH 0x27
kevman 2:7aab896b1a3b 166 #define TMR_PRESCALE 0x28
kevman 2:7aab896b1a3b 167 //---------------- 0x29
kevman 2:7aab896b1a3b 168 #define GPIO_DATA 0x2A
kevman 2:7aab896b1a3b 169 #define GPIO_DIR 0x2B
kevman 2:7aab896b1a3b 170 #define GPIO_PUL_EN 0x2C
kevman 2:7aab896b1a3b 171 #define GPIO_PUL_SEL 0x2D
kevman 2:7aab896b1a3b 172 #define GPIO_DS 0x2E
kevman 2:7aab896b1a3b 173 //-------------- 0x2F
kevman 2:7aab896b1a3b 174 #define ANT_PAD_CTRL 0x30
kevman 2:7aab896b1a3b 175 #define MISC_PAD_CTRL 0x31
kevman 2:7aab896b1a3b 176 #define BSM_CTRL 0x32
kevman 2:7aab896b1a3b 177 //--------------- 0x33
kevman 2:7aab896b1a3b 178 #define _RNG 0x34
kevman 2:7aab896b1a3b 179 #define RX_BYTE_COUNT 0x35
kevman 2:7aab896b1a3b 180 #define RX_WTR_MARK 0x36
kevman 2:7aab896b1a3b 181 #define SOFT_RESET 0x37
kevman 2:7aab896b1a3b 182 #define TXDELAY 0x38
kevman 2:7aab896b1a3b 183 #define ACKDELAY 0x39
kevman 2:7aab896b1a3b 184 #define SEQ_MGR_CTRL 0x3A
kevman 2:7aab896b1a3b 185 #define SEQ_MGR_STS 0x3B
kevman 2:7aab896b1a3b 186 #define SEQ_T_STS 0x3C
kevman 2:7aab896b1a3b 187 #define ABORT_STS 0x3D
kevman 2:7aab896b1a3b 188 #define CCCA_BUSY_CNT 0x3E
kevman 2:7aab896b1a3b 189 #define SRC_ADDR_CHECKSUM1 0x3F
kevman 2:7aab896b1a3b 190 #define SRC_ADDR_CHECKSUM2 0x40
kevman 2:7aab896b1a3b 191 #define SRC_TBL_VALID1 0x41
kevman 2:7aab896b1a3b 192 #define SRC_TBL_VALID2 0x42
kevman 2:7aab896b1a3b 193 #define FILTERFAIL_CODE1 0x43
kevman 2:7aab896b1a3b 194 #define FILTERFAIL_CODE2 0x44
kevman 2:7aab896b1a3b 195 #define SLOT_PRELOAD 0x45
kevman 2:7aab896b1a3b 196 //---------------- 0x46
kevman 2:7aab896b1a3b 197 #define CORR_VT 0x47
kevman 2:7aab896b1a3b 198 #define SYNC_CTRL 0x48
kevman 2:7aab896b1a3b 199 #define PN_LSB_0 0x49
kevman 2:7aab896b1a3b 200 #define PN_LSB_1 0x4A
kevman 2:7aab896b1a3b 201 #define PN_MSB_0 0x4B
kevman 2:7aab896b1a3b 202 #define PN_MSB_1 0x4C
kevman 2:7aab896b1a3b 203 #define CORR_NVAL 0x4D
kevman 2:7aab896b1a3b 204 #define TX_MODE_CTRL 0x4E
kevman 2:7aab896b1a3b 205 #define SNF_THR 0x4F
kevman 2:7aab896b1a3b 206 #define FAD_THR 0x50
kevman 2:7aab896b1a3b 207 #define ANT_AGC_CTRL 0x51
kevman 2:7aab896b1a3b 208 #define AGC_THR1 0x52
kevman 2:7aab896b1a3b 209 #define AGC_THR2 0x53
kevman 2:7aab896b1a3b 210 #define AGC_HYS 0x54
kevman 2:7aab896b1a3b 211 #define AFC 0x55
kevman 2:7aab896b1a3b 212 //--------------- 0x56
kevman 2:7aab896b1a3b 213 //--------------- 0x57
kevman 2:7aab896b1a3b 214 #define PHY_STS 0x58
kevman 2:7aab896b1a3b 215 #define RX_MAX_CORR 0x59
kevman 2:7aab896b1a3b 216 #define RX_MAX_PREAMBLE 0x5A
kevman 2:7aab896b1a3b 217 #define RSSI 0x5B
kevman 2:7aab896b1a3b 218 //--------------- 0x5C
kevman 2:7aab896b1a3b 219 //--------------- 0x5D
kevman 2:7aab896b1a3b 220 #define PLL_DIG_CTRL 0x5E
kevman 2:7aab896b1a3b 221 #define VCO_CAL 0x5F
kevman 2:7aab896b1a3b 222 #define VCO_BEST_DIFF 0x60
kevman 2:7aab896b1a3b 223 #define VCO_BIAS 0x61
kevman 2:7aab896b1a3b 224 #define KMOD_CTRL 0x62
kevman 2:7aab896b1a3b 225 #define KMOD_CAL 0x63
kevman 2:7aab896b1a3b 226 #define PA_CAL 0x64
kevman 2:7aab896b1a3b 227 #define PA_PWRCAL 0x65
kevman 2:7aab896b1a3b 228 #define ATT_RSSI1 0x66
kevman 2:7aab896b1a3b 229 #define ATT_RSSI2 0x67
kevman 2:7aab896b1a3b 230 #define RSSI_OFFSET 0x68
kevman 2:7aab896b1a3b 231 #define RSSI_SLOPE 0x69
kevman 2:7aab896b1a3b 232 #define RSSI_CAL1 0x6A
kevman 2:7aab896b1a3b 233 #define RSSI_CAL2 0x6B
kevman 2:7aab896b1a3b 234 //--------------- 0x6C
kevman 2:7aab896b1a3b 235 //--------------- 0x6D
kevman 2:7aab896b1a3b 236 #define XTAL_CTRL 0x6E
kevman 2:7aab896b1a3b 237 #define XTAL_COMP_MIN 0x6F
kevman 2:7aab896b1a3b 238 #define XTAL_COMP_MAX 0x70
kevman 2:7aab896b1a3b 239 #define XTAL_GM 0x71
kevman 2:7aab896b1a3b 240 //--------------- 0x72
kevman 2:7aab896b1a3b 241 //--------------- 0x73
kevman 2:7aab896b1a3b 242 #define LNA_TUNE 0x74
kevman 2:7aab896b1a3b 243 #define LNA_AGCGAIN 0x75
kevman 2:7aab896b1a3b 244 //--------------- 0x76
kevman 2:7aab896b1a3b 245 //--------------- 0x77
kevman 2:7aab896b1a3b 246 #define CHF_PMA_GAIN 0x78
kevman 2:7aab896b1a3b 247 #define CHF_IBUF 0x79
kevman 2:7aab896b1a3b 248 #define CHF_QBUF 0x7A
kevman 2:7aab896b1a3b 249 #define CHF_IRIN 0x7B
kevman 2:7aab896b1a3b 250 #define CHF_QRIN 0x7C
kevman 2:7aab896b1a3b 251 #define CHF_IL 0x7D
kevman 2:7aab896b1a3b 252 #define CHF_QL 0x7E
kevman 2:7aab896b1a3b 253 #define CHF_CC1 0x7F
kevman 2:7aab896b1a3b 254 #define CHF_CCL 0x80
kevman 2:7aab896b1a3b 255 #define CHF_CC2 0x81
kevman 2:7aab896b1a3b 256 #define CHF_IROUT 0x82
kevman 2:7aab896b1a3b 257 #define CHF_QROUT 0x83
kevman 2:7aab896b1a3b 258 //--------------- 0x84
kevman 2:7aab896b1a3b 259 //--------------- 0x85
kevman 2:7aab896b1a3b 260 #define RSSI_CTRL 0x86
kevman 2:7aab896b1a3b 261 //--------------- 0x87
kevman 2:7aab896b1a3b 262 //--------------- 0x88
kevman 2:7aab896b1a3b 263 #define PA_BIAS 0x89
kevman 2:7aab896b1a3b 264 #define PA_TUNING 0x8A
kevman 2:7aab896b1a3b 265 //--------------- 0x8B
kevman 2:7aab896b1a3b 266 //--------------- 0x8C
kevman 2:7aab896b1a3b 267 #define PMC_HP_TRIM 0x8D
kevman 2:7aab896b1a3b 268 #define VREGA_TRIM 0x8E
kevman 2:7aab896b1a3b 269 //--------------- 0x8F
kevman 2:7aab896b1a3b 270 //--------------- 0x90
kevman 2:7aab896b1a3b 271 #define VCO_CTRL1 0x91
kevman 2:7aab896b1a3b 272 #define VCO_CTRL2 0x92
kevman 2:7aab896b1a3b 273 //--------------- 0x93
kevman 2:7aab896b1a3b 274 //--------------- 0x94
kevman 2:7aab896b1a3b 275 #define ANA_SPARE_OUT1 0x95
kevman 2:7aab896b1a3b 276 #define ANA_SPARE_OUT2 0x96
kevman 2:7aab896b1a3b 277 #define ANA_SPARE_IN 0x97
kevman 2:7aab896b1a3b 278 #define MISCELLANEOUS 0x98
kevman 2:7aab896b1a3b 279 //--------------- 0x99
kevman 2:7aab896b1a3b 280 #define SEQ_MGR_OVRD0 0x9A
kevman 2:7aab896b1a3b 281 #define SEQ_MGR_OVRD1 0x9B
kevman 2:7aab896b1a3b 282 #define SEQ_MGR_OVRD2 0x9C
kevman 2:7aab896b1a3b 283 #define SEQ_MGR_OVRD3 0x9D
kevman 2:7aab896b1a3b 284 #define SEQ_MGR_OVRD4 0x9E
kevman 2:7aab896b1a3b 285 #define SEQ_MGR_OVRD5 0x9F
kevman 2:7aab896b1a3b 286 #define SEQ_MGR_OVRD6 0xA0
kevman 2:7aab896b1a3b 287 #define SEQ_MGR_OVRD7 0xA1
kevman 2:7aab896b1a3b 288 //--------------- 0xA2
kevman 2:7aab896b1a3b 289 #define TESTMODE_CTRL 0xA3
kevman 2:7aab896b1a3b 290 #define DTM_CTRL1 0xA4
kevman 2:7aab896b1a3b 291 #define DTM_CTRL2 0xA5
kevman 2:7aab896b1a3b 292 #define ATM_CTRL1 0xA6
kevman 2:7aab896b1a3b 293 #define ATM_CTRL2 0xA7
kevman 2:7aab896b1a3b 294 #define ATM_CTRL3 0xA8
kevman 2:7aab896b1a3b 295 //--------------- 0xA9
kevman 2:7aab896b1a3b 296 #define LIM_FE_TEST_CTRL 0xAA
kevman 2:7aab896b1a3b 297 #define CHF_TEST_CTRL 0xAB
kevman 2:7aab896b1a3b 298 #define VCO_TEST_CTRL 0xAC
kevman 2:7aab896b1a3b 299 #define PLL_TEST_CTRL 0xAD
kevman 2:7aab896b1a3b 300 #define PA_TEST_CTRL 0xAE
kevman 2:7aab896b1a3b 301 #define PMC_TEST_CTRL 0xAF
kevman 2:7aab896b1a3b 302 #define SCAN_DTM_PROTECT_1 0xFE
kevman 2:7aab896b1a3b 303 #define SCAN_DTM_PROTECT_0 0xFF
kevman 2:7aab896b1a3b 304
kevman 2:7aab896b1a3b 305 // IRQSTS1 bits
kevman 2:7aab896b1a3b 306 #define cIRQSTS1_RX_FRM_PEND (1<<7)
kevman 2:7aab896b1a3b 307 #define cIRQSTS1_PLL_UNLOCK_IRQ (1<<6)
kevman 2:7aab896b1a3b 308 #define cIRQSTS1_FILTERFAIL_IRQ (1<<5)
kevman 2:7aab896b1a3b 309 #define cIRQSTS1_RXWTRMRKIRQ (1<<4)
kevman 2:7aab896b1a3b 310 #define cIRQSTS1_CCAIRQ (1<<3)
kevman 2:7aab896b1a3b 311 #define cIRQSTS1_RXIRQ (1<<2)
kevman 2:7aab896b1a3b 312 #define cIRQSTS1_TXIRQ (1<<1)
kevman 2:7aab896b1a3b 313 #define cIRQSTS1_SEQIRQ (1<<0)
kevman 2:7aab896b1a3b 314
kevman 2:7aab896b1a3b 315 typedef union regIRQSTS1_tag{
kevman 2:7aab896b1a3b 316 uint8_t byte;
kevman 2:7aab896b1a3b 317 struct{
kevman 2:7aab896b1a3b 318 uint8_t SEQIRQ:1;
kevman 2:7aab896b1a3b 319 uint8_t TXIRQ:1;
kevman 2:7aab896b1a3b 320 uint8_t RXIRQ:1;
kevman 2:7aab896b1a3b 321 uint8_t CCAIRQ:1;
kevman 2:7aab896b1a3b 322 uint8_t RXWTRMRKIRQ:1;
kevman 2:7aab896b1a3b 323 uint8_t FILTERFAIL_IRQ:1;
kevman 2:7aab896b1a3b 324 uint8_t PLL_UNLOCK_IRQ:1;
kevman 2:7aab896b1a3b 325 uint8_t RX_FRM_PEND:1;
kevman 2:7aab896b1a3b 326 }bit;
kevman 2:7aab896b1a3b 327 } regIRQSTS1_t;
kevman 2:7aab896b1a3b 328
kevman 2:7aab896b1a3b 329 // IRQSTS2 bits
kevman 2:7aab896b1a3b 330 #define cIRQSTS2_CRCVALID (1<<7)
kevman 2:7aab896b1a3b 331 #define cIRQSTS2_CCA (1<<6)
kevman 2:7aab896b1a3b 332 #define cIRQSTS2_SRCADDR (1<<5)
kevman 2:7aab896b1a3b 333 #define cIRQSTS2_PI (1<<4)
kevman 2:7aab896b1a3b 334 #define cIRQSTS2_TMRSTATUS (1<<3)
kevman 2:7aab896b1a3b 335 #define cIRQSTS2_ASM_IRQ (1<<2)
kevman 2:7aab896b1a3b 336 #define cIRQSTS2_PB_ERR_IRQ (1<<1)
kevman 2:7aab896b1a3b 337 #define cIRQSTS2_WAKE_IRQ (1<<0)
kevman 2:7aab896b1a3b 338
kevman 2:7aab896b1a3b 339 typedef union regIRQSTS2_tag{
kevman 2:7aab896b1a3b 340 uint8_t byte;
kevman 2:7aab896b1a3b 341 struct{
kevman 2:7aab896b1a3b 342 uint8_t WAKE_IRQ:1;
kevman 2:7aab896b1a3b 343 uint8_t PB_ERR_IRQ:1;
kevman 2:7aab896b1a3b 344 uint8_t ASM_IRQ:1;
kevman 2:7aab896b1a3b 345 uint8_t TMRSTATUS:1;
kevman 2:7aab896b1a3b 346 uint8_t PI_:1;
kevman 2:7aab896b1a3b 347 uint8_t SRCADDR:1;
kevman 2:7aab896b1a3b 348 uint8_t CCA:1;
kevman 2:7aab896b1a3b 349 uint8_t CRCVALID:1;
kevman 2:7aab896b1a3b 350 }bit;
kevman 2:7aab896b1a3b 351 } regIRQSTS2_t;
kevman 2:7aab896b1a3b 352
kevman 2:7aab896b1a3b 353 // IRQSTS3 bits
kevman 2:7aab896b1a3b 354 #define cIRQSTS3_TMR4MSK (1<<7)
kevman 2:7aab896b1a3b 355 #define cIRQSTS3_TMR3MSK (1<<6)
kevman 2:7aab896b1a3b 356 #define cIRQSTS3_TMR2MSK (1<<5)
kevman 2:7aab896b1a3b 357 #define cIRQSTS3_TMR1MSK (1<<4)
kevman 2:7aab896b1a3b 358 #define cIRQSTS3_TMR4IRQ (1<<3)
kevman 2:7aab896b1a3b 359 #define cIRQSTS3_TMR3IRQ (1<<2)
kevman 2:7aab896b1a3b 360 #define cIRQSTS3_TMR2IRQ (1<<1)
kevman 2:7aab896b1a3b 361 #define cIRQSTS3_TMR1IRQ (1<<0)
kevman 2:7aab896b1a3b 362
kevman 2:7aab896b1a3b 363 typedef union regIRQSTS3_tag{
kevman 2:7aab896b1a3b 364 uint8_t byte;
kevman 2:7aab896b1a3b 365 struct{
kevman 2:7aab896b1a3b 366 uint8_t TMR1IRQ:1;
kevman 2:7aab896b1a3b 367 uint8_t TMR2IRQ:1;
kevman 2:7aab896b1a3b 368 uint8_t TMR3IRQ:1;
kevman 2:7aab896b1a3b 369 uint8_t TMR4IRQ:1;
kevman 2:7aab896b1a3b 370 uint8_t TMR1MSK:1;
kevman 2:7aab896b1a3b 371 uint8_t TMR2MSK:1;
kevman 2:7aab896b1a3b 372 uint8_t TMR3MSK:1;
kevman 2:7aab896b1a3b 373 uint8_t TMR4MSK:1;
kevman 2:7aab896b1a3b 374 }bit;
kevman 2:7aab896b1a3b 375 } regIRQSTS3_t;
kevman 2:7aab896b1a3b 376
kevman 2:7aab896b1a3b 377 // PHY_CTRL1 bits
kevman 2:7aab896b1a3b 378 #define cPHY_CTRL1_TMRTRIGEN (1<<7)
kevman 2:7aab896b1a3b 379 #define cPHY_CTRL1_SLOTTED (1<<6)
kevman 2:7aab896b1a3b 380 #define cPHY_CTRL1_CCABFRTX (1<<5)
kevman 2:7aab896b1a3b 381 #define cPHY_CTRL1_RXACKRQD (1<<4)
kevman 2:7aab896b1a3b 382 #define cPHY_CTRL1_AUTOACK (1<<3)
kevman 2:7aab896b1a3b 383 #define cPHY_CTRL1_XCVSEQ (7<<0)
kevman 2:7aab896b1a3b 384
kevman 2:7aab896b1a3b 385 typedef union regPHY_CTRL1_tag{
kevman 2:7aab896b1a3b 386 uint8_t byte;
kevman 2:7aab896b1a3b 387 struct{
kevman 2:7aab896b1a3b 388 uint8_t XCVSEQ:3;
kevman 2:7aab896b1a3b 389 uint8_t AUTOACK:1;
kevman 2:7aab896b1a3b 390 uint8_t RXACKRQD:1;
kevman 2:7aab896b1a3b 391 uint8_t CCABFRTX:1;
kevman 2:7aab896b1a3b 392 uint8_t SLOTTED:1;
kevman 2:7aab896b1a3b 393 uint8_t TMRTRIGEN:1;
kevman 2:7aab896b1a3b 394 }bit;
kevman 2:7aab896b1a3b 395 } regPHY_CTRL1_t;
kevman 2:7aab896b1a3b 396
kevman 2:7aab896b1a3b 397 // PHY_CTRL2 bits
kevman 2:7aab896b1a3b 398 #define cPHY_CTRL2_CRC_MSK (1<<7)
kevman 2:7aab896b1a3b 399 #define cPHY_CTRL2_PLL_UNLOCK_MSK (1<<6)
kevman 2:7aab896b1a3b 400 #define cPHY_CTRL2_FILTERFAIL_MSK (1<<5)
kevman 2:7aab896b1a3b 401 #define cPHY_CTRL2_RX_WMRK_MSK (1<<4)
kevman 2:7aab896b1a3b 402 #define cPHY_CTRL2_CCAMSK (1<<3)
kevman 2:7aab896b1a3b 403 #define cPHY_CTRL2_RXMSK (1<<2)
kevman 2:7aab896b1a3b 404 #define cPHY_CTRL2_TXMSK (1<<1)
kevman 2:7aab896b1a3b 405 #define cPHY_CTRL2_SEQMSK (1<<0)
kevman 2:7aab896b1a3b 406
kevman 2:7aab896b1a3b 407 typedef union regPHY_CTRL2_tag{
kevman 2:7aab896b1a3b 408 uint8_t byte;
kevman 2:7aab896b1a3b 409 struct{
kevman 2:7aab896b1a3b 410 uint8_t SEQMSK:1;
kevman 2:7aab896b1a3b 411 uint8_t TXMSK:1;
kevman 2:7aab896b1a3b 412 uint8_t RXMSK:1;
kevman 2:7aab896b1a3b 413 uint8_t CCAMSK:1;
kevman 2:7aab896b1a3b 414 uint8_t RX_WMRK_MSK:1;
kevman 2:7aab896b1a3b 415 uint8_t FILTERFAIL_MSK:1;
kevman 2:7aab896b1a3b 416 uint8_t PLL_UNLOCK_MSK:1;
kevman 2:7aab896b1a3b 417 uint8_t CRC_MSK:1;
kevman 2:7aab896b1a3b 418 }bit;
kevman 2:7aab896b1a3b 419 } regPHY_CTRL2_t;
kevman 2:7aab896b1a3b 420
kevman 2:7aab896b1a3b 421 // PHY_CTRL3 bits
kevman 2:7aab896b1a3b 422 #define cPHY_CTRL3_TMR4CMP_EN (1<<7)
kevman 2:7aab896b1a3b 423 #define cPHY_CTRL3_TMR3CMP_EN (1<<6)
kevman 2:7aab896b1a3b 424 #define cPHY_CTRL3_TMR2CMP_EN (1<<5)
kevman 2:7aab896b1a3b 425 #define cPHY_CTRL3_TMR1CMP_EN (1<<4)
kevman 2:7aab896b1a3b 426 #define cPHY_CTRL3_ASM_MSK (1<<2)
kevman 2:7aab896b1a3b 427 #define cPHY_CTRL3_PB_ERR_MSK (1<<1)
kevman 2:7aab896b1a3b 428 #define cPHY_CTRL3_WAKE_MSK (1<<0)
kevman 2:7aab896b1a3b 429
kevman 2:7aab896b1a3b 430 typedef union regPHY_CTRL3_tag{
kevman 2:7aab896b1a3b 431 uint8_t byte;
kevman 2:7aab896b1a3b 432 struct{
kevman 2:7aab896b1a3b 433 uint8_t WAKE_MSK:1;
kevman 2:7aab896b1a3b 434 uint8_t PB_ERR_MSK:1;
kevman 2:7aab896b1a3b 435 uint8_t ASM_MSK:1;
kevman 2:7aab896b1a3b 436 uint8_t RESERVED:1;
kevman 2:7aab896b1a3b 437 uint8_t TMR1CMP_EN:1;
kevman 2:7aab896b1a3b 438 uint8_t TMR2CMP_EN:1;
kevman 2:7aab896b1a3b 439 uint8_t TMR3CMP_EN:1;
kevman 2:7aab896b1a3b 440 uint8_t TMR4CMP_EN:1;
kevman 2:7aab896b1a3b 441 }bit;
kevman 2:7aab896b1a3b 442 } regPHY_CTRL3_t;
kevman 2:7aab896b1a3b 443
kevman 2:7aab896b1a3b 444 // RX_FRM_LEN bits
kevman 2:7aab896b1a3b 445 #define cRX_FRAME_LENGTH (0x7F)
kevman 2:7aab896b1a3b 446
kevman 2:7aab896b1a3b 447 // PHY_CTRL4 bits
kevman 2:7aab896b1a3b 448 #define cPHY_CTRL4_TRCV_MSK (1<<7)
kevman 2:7aab896b1a3b 449 #define cPHY_CTRL4_TC3TMOUT (1<<6)
kevman 2:7aab896b1a3b 450 #define cPHY_CTRL4_PANCORDNTR0 (1<<5)
kevman 2:7aab896b1a3b 451 #define cPHY_CTRL4_CCATYPE (3<<0)
kevman 2:7aab896b1a3b 452 #define cPHY_CTRL4_CCATYPE_Shift_c (3)
kevman 2:7aab896b1a3b 453 #define cPHY_CTRL4_TMRLOAD (1<<2)
kevman 2:7aab896b1a3b 454 #define cPHY_CTRL4_PROMISCUOUS (1<<1)
kevman 2:7aab896b1a3b 455 #define cPHY_CTRL4_TC2PRIME_EN (1<<0)
kevman 2:7aab896b1a3b 456
kevman 2:7aab896b1a3b 457 typedef union regPHY_CTRL4_tag{
kevman 2:7aab896b1a3b 458 uint8_t byte;
kevman 2:7aab896b1a3b 459 struct{
kevman 2:7aab896b1a3b 460 uint8_t TC2PRIME_EN:1;
kevman 2:7aab896b1a3b 461 uint8_t PROMISCUOUS:1;
kevman 2:7aab896b1a3b 462 uint8_t TMRLOAD:1;
kevman 2:7aab896b1a3b 463 uint8_t CCATYPE:2;
kevman 2:7aab896b1a3b 464 uint8_t PANCORDNTR0:1;
kevman 2:7aab896b1a3b 465 uint8_t TC3TMOUT:1;
kevman 2:7aab896b1a3b 466 uint8_t TRCV_MSK:1;
kevman 2:7aab896b1a3b 467 }bit;
kevman 2:7aab896b1a3b 468 } regPHY_CTRL4_t;
kevman 2:7aab896b1a3b 469
kevman 2:7aab896b1a3b 470 // SRC_CTRL bits
kevman 2:7aab896b1a3b 471 #define cSRC_CTRL_INDEX (0x0F)
kevman 2:7aab896b1a3b 472 #define cSRC_CTRL_INDEX_Shift_c (4)
kevman 2:7aab896b1a3b 473 #define cSRC_CTRL_ACK_FRM_PND (1<<3)
kevman 2:7aab896b1a3b 474 #define cSRC_CTRL_SRCADDR_EN (1<<2)
kevman 2:7aab896b1a3b 475 #define cSRC_CTRL_INDEX_EN (1<<1)
kevman 2:7aab896b1a3b 476 #define cSRC_CTRL_INDEX_DISABLE (1<<0)
kevman 2:7aab896b1a3b 477
kevman 2:7aab896b1a3b 478 typedef union regSRC_CTRL_tag{
kevman 2:7aab896b1a3b 479 uint8_t byte;
kevman 2:7aab896b1a3b 480 struct{
kevman 2:7aab896b1a3b 481 uint8_t INDEX_DISABLE:1;
kevman 2:7aab896b1a3b 482 uint8_t INDEX_EN:1;
kevman 2:7aab896b1a3b 483 uint8_t SRCADDR_EN:1;
kevman 2:7aab896b1a3b 484 uint8_t ACK_FRM_PND:1;
kevman 2:7aab896b1a3b 485 uint8_t INDEX:4;
kevman 2:7aab896b1a3b 486 }bit;
kevman 2:7aab896b1a3b 487 } regSRC_CTRL_t;
kevman 2:7aab896b1a3b 488
kevman 2:7aab896b1a3b 489 // ASM_CTRL1 bits
kevman 2:7aab896b1a3b 490 #define cASM_CTRL1_CLEAR (1<<7)
kevman 2:7aab896b1a3b 491 #define cASM_CTRL1_START (1<<6)
kevman 2:7aab896b1a3b 492 #define cASM_CTRL1_SELFTST (1<<5)
kevman 2:7aab896b1a3b 493 #define cASM_CTRL1_CTR (1<<4)
kevman 2:7aab896b1a3b 494 #define cASM_CTRL1_CBC (1<<3)
kevman 2:7aab896b1a3b 495 #define cASM_CTRL1_AES (1<<2)
kevman 2:7aab896b1a3b 496 #define cASM_CTRL1_LOAD_MAC (1<<1)
kevman 2:7aab896b1a3b 497
kevman 2:7aab896b1a3b 498 // ASM_CTRL2 bits
kevman 2:7aab896b1a3b 499 #define cASM_CTRL2_DATA_REG_TYPE_SEL (7)
kevman 2:7aab896b1a3b 500 #define cASM_CTRL2_DATA_REG_TYPE_SEL_Shift_c (5)
kevman 2:7aab896b1a3b 501 #define cASM_CTRL2_TSTPAS (1<<1)
kevman 2:7aab896b1a3b 502
kevman 2:7aab896b1a3b 503 // CLK_OUT_CTRL bits
kevman 2:7aab896b1a3b 504 #define cCLK_OUT_CTRL_EXTEND (1<<7)
kevman 2:7aab896b1a3b 505 #define cCLK_OUT_CTRL_HIZ (1<<6)
kevman 2:7aab896b1a3b 506 #define cCLK_OUT_CTRL_SR (1<<5)
kevman 2:7aab896b1a3b 507 #define cCLK_OUT_CTRL_DS (1<<4)
kevman 2:7aab896b1a3b 508 #define cCLK_OUT_CTRL_EN (1<<3)
kevman 2:7aab896b1a3b 509 #define cCLK_OUT_CTRL_DIV (7)
kevman 2:7aab896b1a3b 510
kevman 2:7aab896b1a3b 511 // PWR_MODES bits
kevman 2:7aab896b1a3b 512 #define cPWR_MODES_XTAL_READY (1<<5)
kevman 2:7aab896b1a3b 513 #define cPWR_MODES_XTALEN (1<<4)
kevman 2:7aab896b1a3b 514 #define cPWR_MODES_ASM_CLK_EN (1<<3)
kevman 2:7aab896b1a3b 515 #define cPWR_MODES_AUTODOZE (1<<1)
kevman 2:7aab896b1a3b 516 #define cPWR_MODES_PMC_MODE (1<<0)
kevman 2:7aab896b1a3b 517
kevman 2:7aab896b1a3b 518 // RX_FRAME_FILTER bits
kevman 2:7aab896b1a3b 519 #define cRX_FRAME_FLT_FRM_VER (0xC0)
kevman 2:7aab896b1a3b 520 #define cRX_FRAME_FLT_FRM_VER_Shift_c (6)
kevman 2:7aab896b1a3b 521 #define cRX_FRAME_FLT_ACTIVE_PROMISCUOUS (1<<5)
kevman 2:7aab896b1a3b 522 #define cRX_FRAME_FLT_NS_FT (1<<4)
kevman 2:7aab896b1a3b 523 #define cRX_FRAME_FLT_CMD_FT (1<<3)
kevman 2:7aab896b1a3b 524 #define cRX_FRAME_FLT_ACK_FT (1<<2)
kevman 2:7aab896b1a3b 525 #define cRX_FRAME_FLT_DATA_FT (1<<1)
kevman 2:7aab896b1a3b 526 #define cRX_FRAME_FLT_BEACON_FT (1<<0)
kevman 2:7aab896b1a3b 527
kevman 2:7aab896b1a3b 528 typedef union regRX_FRAME_FILTER_tag{
kevman 2:7aab896b1a3b 529 uint8_t byte;
kevman 2:7aab896b1a3b 530 struct{
kevman 2:7aab896b1a3b 531 uint8_t FRAME_FLT_BEACON_FT:1;
kevman 2:7aab896b1a3b 532 uint8_t FRAME_FLT_DATA_FT:1;
kevman 2:7aab896b1a3b 533 uint8_t FRAME_FLT_ACK_FT:1;
kevman 2:7aab896b1a3b 534 uint8_t FRAME_FLT_CMD_FT:1;
kevman 2:7aab896b1a3b 535 uint8_t FRAME_FLT_NS_FT:1;
kevman 2:7aab896b1a3b 536 uint8_t FRAME_FLT_ACTIVE_PROMISCUOUS:1;
kevman 2:7aab896b1a3b 537 uint8_t FRAME_FLT_FRM_VER:2;
kevman 2:7aab896b1a3b 538 }bit;
kevman 2:7aab896b1a3b 539 } regRX_FRAME_FILTER_t;
kevman 2:7aab896b1a3b 540
kevman 2:7aab896b1a3b 541 // DUAL_PAN_CTRL bits
kevman 2:7aab896b1a3b 542 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_MSK (0xF0)
kevman 2:7aab896b1a3b 543 #define cDUAL_PAN_CTRL_DUAL_PAN_SAM_LVL_Shift_c (4)
kevman 2:7aab896b1a3b 544 #define cDUAL_PAN_CTRL_CURRENT_NETWORK (1<<3)
kevman 2:7aab896b1a3b 545 #define cDUAL_PAN_CTRL_PANCORDNTR1 (1<<2)
kevman 2:7aab896b1a3b 546 #define cDUAL_PAN_CTRL_DUAL_PAN_AUTO (1<<1)
kevman 2:7aab896b1a3b 547 #define cDUAL_PAN_CTRL_ACTIVE_NETWORK (1<<0)
kevman 2:7aab896b1a3b 548
kevman 2:7aab896b1a3b 549 // DUAL_PAN_STS bits
kevman 2:7aab896b1a3b 550 #define cDUAL_PAN_STS_RECD_ON_PAN1 (1<<7)
kevman 2:7aab896b1a3b 551 #define cDUAL_PAN_STS_RECD_ON_PAN0 (1<<6)
kevman 2:7aab896b1a3b 552 #define cDUAL_PAN_STS_DUAL_PAN_REMAIN (0x3F)
kevman 2:7aab896b1a3b 553
kevman 2:7aab896b1a3b 554 // CCA_CTRL bits
kevman 2:7aab896b1a3b 555 #define cCCA_CTRL_AGC_FRZ_EN (1<<6)
kevman 2:7aab896b1a3b 556 #define cCCA_CTRL_CONT_RSSI_EN (1<<5)
kevman 2:7aab896b1a3b 557 #define cCCA_CTRL_LQI_RSSI_NOT_CORR (1<<4)
kevman 2:7aab896b1a3b 558 #define cCCA_CTRL_CCA3_AND_NOT_OR (1<<3)
kevman 2:7aab896b1a3b 559 #define cCCA_CTRL_POWER_COMP_EN_LQI (1<<2)
kevman 2:7aab896b1a3b 560 #define cCCA_CTRL_POWER_COMP_EN_ED (1<<1)
kevman 2:7aab896b1a3b 561 #define cCCA_CTRL_POWER_COMP_EN_CCA1 (1<<0)
kevman 2:7aab896b1a3b 562
kevman 2:7aab896b1a3b 563 // GPIO_DATA bits
kevman 2:7aab896b1a3b 564 #define cGPIO_DATA_7 (1<<7)
kevman 2:7aab896b1a3b 565 #define cGPIO_DATA_6 (1<<6)
kevman 2:7aab896b1a3b 566 #define cGPIO_DATA_5 (1<<5)
kevman 2:7aab896b1a3b 567 #define cGPIO_DATA_4 (1<<4)
kevman 2:7aab896b1a3b 568 #define cGPIO_DATA_3 (1<<3)
kevman 2:7aab896b1a3b 569 #define cGPIO_DATA_2 (1<<2)
kevman 2:7aab896b1a3b 570 #define cGPIO_DATA_1 (1<<1)
kevman 2:7aab896b1a3b 571 #define cGPIO_DATA_0 (1<<0)
kevman 2:7aab896b1a3b 572
kevman 2:7aab896b1a3b 573 // GPIO_DIR bits
kevman 2:7aab896b1a3b 574 #define cGPIO_DIR_7 (1<<7)
kevman 2:7aab896b1a3b 575 #define cGPIO_DIR_6 (1<<6)
kevman 2:7aab896b1a3b 576 #define cGPIO_DIR_5 (1<<5)
kevman 2:7aab896b1a3b 577 #define cGPIO_DIR_4 (1<<4)
kevman 2:7aab896b1a3b 578 #define cGPIO_DIR_3 (1<<3)
kevman 2:7aab896b1a3b 579 #define cGPIO_DIR_2 (1<<2)
kevman 2:7aab896b1a3b 580 #define cGPIO_DIR_1 (1<<1)
kevman 2:7aab896b1a3b 581 #define cGPIO_DIR_0 (1<<0)
kevman 2:7aab896b1a3b 582
kevman 2:7aab896b1a3b 583 // GPIO_PUL_EN bits
kevman 2:7aab896b1a3b 584 #define cGPIO_PUL_EN_7 (1<<7)
kevman 2:7aab896b1a3b 585 #define cGPIO_PUL_EN_6 (1<<6)
kevman 2:7aab896b1a3b 586 #define cGPIO_PUL_EN_5 (1<<5)
kevman 2:7aab896b1a3b 587 #define cGPIO_PUL_EN_4 (1<<4)
kevman 2:7aab896b1a3b 588 #define cGPIO_PUL_EN_3 (1<<3)
kevman 2:7aab896b1a3b 589 #define cGPIO_PUL_EN_2 (1<<2)
kevman 2:7aab896b1a3b 590 #define cGPIO_PUL_EN_1 (1<<1)
kevman 2:7aab896b1a3b 591 #define cGPIO_PUL_EN_0 (1<<0)
kevman 2:7aab896b1a3b 592
kevman 2:7aab896b1a3b 593 // GPIO_PUL_SEL bits
kevman 2:7aab896b1a3b 594 #define cGPIO_PUL_SEL_7 (1<<7)
kevman 2:7aab896b1a3b 595 #define cGPIO_PUL_SEL_6 (1<<6)
kevman 2:7aab896b1a3b 596 #define cGPIO_PUL_SEL_5 (1<<5)
kevman 2:7aab896b1a3b 597 #define cGPIO_PUL_SEL_4 (1<<4)
kevman 2:7aab896b1a3b 598 #define cGPIO_PUL_SEL_3 (1<<3)
kevman 2:7aab896b1a3b 599 #define cGPIO_PUL_SEL_2 (1<<2)
kevman 2:7aab896b1a3b 600 #define cGPIO_PUL_SEL_1 (1<<1)
kevman 2:7aab896b1a3b 601 #define cGPIO_PUL_SEL_0 (1<<0)
kevman 2:7aab896b1a3b 602
kevman 2:7aab896b1a3b 603 // GPIO_DS bits
kevman 2:7aab896b1a3b 604 #define cGPIO_DS_7 (1<<7)
kevman 2:7aab896b1a3b 605 #define cGPIO_DS_6 (1<<6)
kevman 2:7aab896b1a3b 606 #define cGPIO_DS_5 (1<<5)
kevman 2:7aab896b1a3b 607 #define cGPIO_DS_4 (1<<4)
kevman 2:7aab896b1a3b 608 #define cGPIO_DS_3 (1<<3)
kevman 2:7aab896b1a3b 609 #define cGPIO_DS_2 (1<<2)
kevman 2:7aab896b1a3b 610 #define cGPIO_DS_1 (1<<1)
kevman 2:7aab896b1a3b 611 #define cGPIO_DS_0 (1<<0)
kevman 2:7aab896b1a3b 612
kevman 2:7aab896b1a3b 613 // SPI_CTRL bits
kevman 2:7aab896b1a3b 614 //#define cSPI_CTRL_MISO_HIZ_EN (1<<1)
kevman 2:7aab896b1a3b 615 //#define cSPI_CTRL_PB_PROTECT (1<<0)
kevman 2:7aab896b1a3b 616
kevman 2:7aab896b1a3b 617 // ANT_PAD_CTRL bits
kevman 2:7aab896b1a3b 618 #define cANT_PAD_CTRL_ANTX_POL (0x0F)
kevman 2:7aab896b1a3b 619 #define cANT_PAD_CTRL_ANTX_POL_Shift_c (4)
kevman 2:7aab896b1a3b 620 #define cANT_PAD_CTRL_ANTX_CTRLMODE (1<<3)
kevman 2:7aab896b1a3b 621 #define cANT_PAD_CTRL_ANTX_HZ (1<<2)
kevman 2:7aab896b1a3b 622 #define cANT_PAD_CTRL_ANTX_EN (3)
kevman 2:7aab896b1a3b 623
kevman 2:7aab896b1a3b 624 // MISC_PAD_CTRL bits
kevman 2:7aab896b1a3b 625 #define cMISC_PAD_CTRL_MISO_HIZ_EN (1<<3)
kevman 2:7aab896b1a3b 626 #define cMISC_PAD_CTRL_IRQ_B_OD (1<<2)
kevman 2:7aab896b1a3b 627 #define cMISC_PAD_CTRL_NON_GPIO_DS (1<<1)
kevman 2:7aab896b1a3b 628 #define cMISC_PAD_CTRL_ANTX_CURR (1<<0)
kevman 2:7aab896b1a3b 629
kevman 2:7aab896b1a3b 630 // ANT_AGC_CTRL bits
kevman 2:7aab896b1a3b 631 #define cANT_AGC_CTRL_FAD_EN_Shift_c (0)
kevman 2:7aab896b1a3b 632 #define cANT_AGC_CTRL_FAD_EN_Mask_c (1<<cANT_AGC_CTRL_FAD_EN_Shift_c)
kevman 2:7aab896b1a3b 633 #define cANT_AGC_CTRL_ANTX_Shift_c (1)
kevman 2:7aab896b1a3b 634 #define cANT_AGC_CTRL_ANTX_Mask_c (1<<cANT_AGC_CTRL_ANTX_Shift_c)
kevman 2:7aab896b1a3b 635
kevman 2:7aab896b1a3b 636 // BSM_CTRL bits
kevman 2:7aab896b1a3b 637 #define cBSM_CTRL_BSM_EN (1<<0)
kevman 2:7aab896b1a3b 638
kevman 2:7aab896b1a3b 639 // SOFT_RESET bits
kevman 2:7aab896b1a3b 640 #define cSOFT_RESET_SOG_RST (1<<7)
kevman 2:7aab896b1a3b 641 #define cSOFT_RESET_REGS_RST (1<<4)
kevman 2:7aab896b1a3b 642 #define cSOFT_RESET_PLL_RST (1<<3)
kevman 2:7aab896b1a3b 643 #define cSOFT_RESET_TX_RST (1<<2)
kevman 2:7aab896b1a3b 644 #define cSOFT_RESET_RX_RST (1<<1)
kevman 2:7aab896b1a3b 645 #define cSOFT_RESET_SEQ_MGR_RST (1<<0)
kevman 2:7aab896b1a3b 646
kevman 2:7aab896b1a3b 647 // SEQ_MGR_CTRL bits
kevman 2:7aab896b1a3b 648 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL (3)
kevman 2:7aab896b1a3b 649 #define cSEQ_MGR_CTRL_SEQ_STATE_CTRL_Shift_c (6)
kevman 2:7aab896b1a3b 650 #define cSEQ_MGR_CTRL_NO_RX_RECYCLE (1<<5)
kevman 2:7aab896b1a3b 651 #define cSEQ_MGR_CTRL_LATCH_PREAMBLE (1<<4)
kevman 2:7aab896b1a3b 652 #define cSEQ_MGR_CTRL_EVENT_TMR_DO_NOT_LATCH (1<<3)
kevman 2:7aab896b1a3b 653 #define cSEQ_MGR_CTRL_CLR_NEW_SEQ_INHIBIT (1<<2)
kevman 2:7aab896b1a3b 654 #define cSEQ_MGR_CTRL_PSM_LOCK_DIS (1<<1)
kevman 2:7aab896b1a3b 655 #define cSEQ_MGR_CTRL_PLL_ABORT_OVRD (1<<0)
kevman 2:7aab896b1a3b 656
kevman 2:7aab896b1a3b 657 // SEQ_MGR_STS bits
kevman 2:7aab896b1a3b 658 #define cSEQ_MGR_STS_TMR2_SEQ_TRIG_ARMED (1<<7)
kevman 2:7aab896b1a3b 659 #define cSEQ_MGR_STS_RX_MODE (1<<6)
kevman 2:7aab896b1a3b 660 #define cSEQ_MGR_STS_RX_TIMEOUT_PENDING (1<<5)
kevman 2:7aab896b1a3b 661 #define cSEQ_MGR_STS_NEW_SEQ_INHIBIT (1<<4)
kevman 2:7aab896b1a3b 662 #define cSEQ_MGR_STS_SEQ_IDLE (1<<3)
kevman 2:7aab896b1a3b 663 #define cSEQ_MGR_STS_XCVSEQ_ACTUAL (7)
kevman 2:7aab896b1a3b 664
kevman 2:7aab896b1a3b 665 // ABORT_STS bits
kevman 2:7aab896b1a3b 666 #define cABORT_STS_PLL_ABORTED (1<<2)
kevman 2:7aab896b1a3b 667 #define cABORT_STS_TC3_ABORTED (1<<1)
kevman 2:7aab896b1a3b 668 #define cABORT_STS_SW_ABORTED (1<<0)
kevman 2:7aab896b1a3b 669
kevman 2:7aab896b1a3b 670 // FILTERFAIL_CODE2 bits
kevman 2:7aab896b1a3b 671 #define cFILTERFAIL_CODE2_PAN_SEL (1<<7)
kevman 2:7aab896b1a3b 672 #define cFILTERFAIL_CODE2_9_8 (3)
kevman 2:7aab896b1a3b 673
kevman 2:7aab896b1a3b 674 // PHY_STS bits
kevman 2:7aab896b1a3b 675 #define cPHY_STS_PLL_UNLOCK (1<<7)
kevman 2:7aab896b1a3b 676 #define cPHY_STS_PLL_LOCK_ERR (1<<6)
kevman 2:7aab896b1a3b 677 #define cPHY_STS_PLL_LOCK (1<<5)
kevman 2:7aab896b1a3b 678 #define cPHY_STS_CRCVALID (1<<3)
kevman 2:7aab896b1a3b 679 #define cPHY_STS_FILTERFAIL_FLAG_SEL (1<<2)
kevman 2:7aab896b1a3b 680 #define cPHY_STS_SFD_DET (1<<1)
kevman 2:7aab896b1a3b 681 #define cPHY_STS_PREAMBLE_DET (1<<0)
kevman 2:7aab896b1a3b 682
kevman 2:7aab896b1a3b 683 // TESTMODE_CTRL bits
kevman 2:7aab896b1a3b 684 #define cTEST_MODE_CTRL_HOT_ANT (1<<4)
kevman 2:7aab896b1a3b 685 #define cTEST_MODE_CTRL_IDEAL_RSSI_EN (1<<3)
kevman 2:7aab896b1a3b 686 #define cTEST_MODE_CTRL_IDEAL_PFC_EN (1<<2)
kevman 2:7aab896b1a3b 687 #define cTEST_MODE_CTRL_CONTINUOUS_EN (1<<1)
kevman 2:7aab896b1a3b 688 #define cTEST_MODE_CTRL_FPGA_EN (1<<0)
kevman 2:7aab896b1a3b 689
kevman 2:7aab896b1a3b 690 // DTM_CTRL1 bits
kevman 2:7aab896b1a3b 691 #define cDTM_CTRL1_ATM_LOCKED (1<<7)
kevman 2:7aab896b1a3b 692 #define cDTM_CTRL1_DTM_EN (1<<6)
kevman 2:7aab896b1a3b 693 #define cDTM_CTRL1_PAGE5 (1<<5)
kevman 2:7aab896b1a3b 694 #define cDTM_CTRL1_PAGE4 (1<<4)
kevman 2:7aab896b1a3b 695 #define cDTM_CTRL1_PAGE3 (1<<3)
kevman 2:7aab896b1a3b 696 #define cDTM_CTRL1_PAGE2 (1<<2)
kevman 2:7aab896b1a3b 697 #define cDTM_CTRL1_PAGE1 (1<<1)
kevman 2:7aab896b1a3b 698 #define cDTM_CTRL1_PAGE0 (1<<0)
kevman 2:7aab896b1a3b 699
kevman 2:7aab896b1a3b 700 // TX_MODE_CTRL
kevman 2:7aab896b1a3b 701 #define cTX_MODE_CTRL_TX_INV (1<<4)
kevman 2:7aab896b1a3b 702 #define cTX_MODE_CTRL_BT_EN (1<<3)
kevman 2:7aab896b1a3b 703 #define cTX_MODE_CTRL_DTS2 (1<<2)
kevman 2:7aab896b1a3b 704 #define cTX_MODE_CTRL_DTS1 (1<<1)
kevman 2:7aab896b1a3b 705 #define cTX_MODE_CTRL_DTS0 (1<<0)
kevman 2:7aab896b1a3b 706
kevman 2:7aab896b1a3b 707 #define cTX_MODE_CTRL_DTS_MASK (7)
kevman 2:7aab896b1a3b 708
kevman 2:7aab896b1a3b 709 // CLK_OUT_CTRL bits
kevman 2:7aab896b1a3b 710 #define cCLK_OUT_EXTEND (1<<7)
kevman 2:7aab896b1a3b 711 #define cCLK_OUT_HIZ (1<<6)
kevman 2:7aab896b1a3b 712 #define cCLK_OUT_SR (1<<5)
kevman 2:7aab896b1a3b 713 #define cCLK_OUT_DS (1<<4)
kevman 2:7aab896b1a3b 714 #define cCLK_OUT_EN (1<<3)
kevman 2:7aab896b1a3b 715 #define cCLK_OUT_DIV_Mask (7<<0)
kevman 2:7aab896b1a3b 716
kevman 2:7aab896b1a3b 717 #define gCLK_OUT_FREQ_32_MHz (0)
kevman 2:7aab896b1a3b 718 #define gCLK_OUT_FREQ_16_MHz (1)
kevman 2:7aab896b1a3b 719 #define gCLK_OUT_FREQ_8_MHz (2)
kevman 2:7aab896b1a3b 720 #define gCLK_OUT_FREQ_4_MHz (3)
kevman 2:7aab896b1a3b 721 #define gCLK_OUT_FREQ_1_MHz (4)
kevman 2:7aab896b1a3b 722 #define gCLK_OUT_FREQ_250_KHz (5)
kevman 2:7aab896b1a3b 723 #define gCLK_OUT_FREQ_62_5_KHz (6)
kevman 2:7aab896b1a3b 724 #define gCLK_OUT_FREQ_32_78_KHz (7)
kevman 2:7aab896b1a3b 725 #define gCLK_OUT_FREQ_DISABLE (8)
kevman 2:7aab896b1a3b 726
kevman 2:7aab896b1a3b 727
kevman 2:7aab896b1a3b 728
kevman 2:7aab896b1a3b 729
kevman 2:7aab896b1a3b 730 #endif /* __MCR20_REG_H__ */