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cmsis/TARGET_CORTEX_M/core_cm33.h@2:7aab896b1a3b, 2019-03-13 (annotated)

Committer:: kevman
Date:: Wed Mar 13 11:03:24 2019 +0000
Revision:: 2:7aab896b1a3b
Parent:: 0:38ceb79fef03

2019-03-13

Who changed what in which revision?

User	Revision	Line number	New contents of line
kevman	0:38ceb79fef03	1	/************************************************************************//
kevman	0:38ceb79fef03	2	* @file core_cm33.h
kevman	0:38ceb79fef03	3	* @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File
kevman	0:38ceb79fef03	4	* @version V5.0.9
kevman	0:38ceb79fef03	5	* @date 06. July 2018
kevman	0:38ceb79fef03	6	******************************************************************************/
kevman	0:38ceb79fef03	7	/*
kevman	0:38ceb79fef03	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
kevman	0:38ceb79fef03	9	*
kevman	0:38ceb79fef03	10	* SPDX-License-Identifier: Apache-2.0
kevman	0:38ceb79fef03	11	*
kevman	0:38ceb79fef03	12	* Licensed under the Apache License, Version 2.0 (the License); you may
kevman	0:38ceb79fef03	13	* not use this file except in compliance with the License.
kevman	0:38ceb79fef03	14	* You may obtain a copy of the License at
kevman	0:38ceb79fef03	15	*
kevman	0:38ceb79fef03	16	* www.apache.org/licenses/LICENSE-2.0
kevman	0:38ceb79fef03	17	*
kevman	0:38ceb79fef03	18	* Unless required by applicable law or agreed to in writing, software
kevman	0:38ceb79fef03	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
kevman	0:38ceb79fef03	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kevman	0:38ceb79fef03	21	* See the License for the specific language governing permissions and
kevman	0:38ceb79fef03	22	* limitations under the License.
kevman	0:38ceb79fef03	23	*/
kevman	0:38ceb79fef03	24
kevman	0:38ceb79fef03	25	#if defined ( __ICCARM__ )
kevman	0:38ceb79fef03	26	#pragma system_include /* treat file as system include file for MISRA check */
kevman	0:38ceb79fef03	27	#elif defined (__clang__)
kevman	0:38ceb79fef03	28	#pragma clang system_header /* treat file as system include file */
kevman	0:38ceb79fef03	29	#endif
kevman	0:38ceb79fef03	30
kevman	0:38ceb79fef03	31	#ifndef __CORE_CM33_H_GENERIC
kevman	0:38ceb79fef03	32	#define __CORE_CM33_H_GENERIC
kevman	0:38ceb79fef03	33
kevman	0:38ceb79fef03	34	#include <stdint.h>
kevman	0:38ceb79fef03	35
kevman	0:38ceb79fef03	36	#ifdef __cplusplus
kevman	0:38ceb79fef03	37	extern "C" {
kevman	0:38ceb79fef03	38	#endif
kevman	0:38ceb79fef03	39
kevman	0:38ceb79fef03	40	/**
kevman	0:38ceb79fef03	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
kevman	0:38ceb79fef03	42	CMSIS violates the following MISRA-C:2004 rules:
kevman	0:38ceb79fef03	43
kevman	0:38ceb79fef03	44	\li Required Rule 8.5, object/function definition in header file.<br>
kevman	0:38ceb79fef03	45	Function definitions in header files are used to allow 'inlining'.
kevman	0:38ceb79fef03	46
kevman	0:38ceb79fef03	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
kevman	0:38ceb79fef03	48	Unions are used for effective representation of core registers.
kevman	0:38ceb79fef03	49
kevman	0:38ceb79fef03	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
kevman	0:38ceb79fef03	51	Function-like macros are used to allow more efficient code.
kevman	0:38ceb79fef03	52	*/
kevman	0:38ceb79fef03	53
kevman	0:38ceb79fef03	54
kevman	0:38ceb79fef03	55	/*******************************************************************************
kevman	0:38ceb79fef03	56	* CMSIS definitions
kevman	0:38ceb79fef03	57	******************************************************************************/
kevman	0:38ceb79fef03	58	/**
kevman	0:38ceb79fef03	59	\ingroup Cortex_M33
kevman	0:38ceb79fef03	60	@{
kevman	0:38ceb79fef03	61	*/
kevman	0:38ceb79fef03	62
kevman	0:38ceb79fef03	63	#include "cmsis_version.h"
kevman	0:38ceb79fef03	64
kevman	0:38ceb79fef03	65	/* CMSIS CM33 definitions */
kevman	0:38ceb79fef03	66	#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
kevman	0:38ceb79fef03	67	#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
kevman	0:38ceb79fef03	68	#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) \| \
kevman	0:38ceb79fef03	69	__CM33_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
kevman	0:38ceb79fef03	70
kevman	0:38ceb79fef03	71	#define __CORTEX_M (33U) /!< Cortex-M Core /
kevman	0:38ceb79fef03	72
kevman	0:38ceb79fef03	73	/** __FPU_USED indicates whether an FPU is used or not.
kevman	0:38ceb79fef03	74	For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
kevman	0:38ceb79fef03	75	*/
kevman	0:38ceb79fef03	76	#if defined ( __CC_ARM )
kevman	0:38ceb79fef03	77	#if defined (__TARGET_FPU_VFP)
kevman	0:38ceb79fef03	78	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kevman	0:38ceb79fef03	79	#define __FPU_USED 1U
kevman	0:38ceb79fef03	80	#else
kevman	0:38ceb79fef03	81	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman	0:38ceb79fef03	82	#define __FPU_USED 0U
kevman	0:38ceb79fef03	83	#endif
kevman	0:38ceb79fef03	84	#else
kevman	0:38ceb79fef03	85	#define __FPU_USED 0U
kevman	0:38ceb79fef03	86	#endif
kevman	0:38ceb79fef03	87
kevman	0:38ceb79fef03	88	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
kevman	0:38ceb79fef03	89	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
kevman	0:38ceb79fef03	90	#define __DSP_USED 1U
kevman	0:38ceb79fef03	91	#else
kevman	0:38ceb79fef03	92	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
kevman	0:38ceb79fef03	93	#define __DSP_USED 0U
kevman	0:38ceb79fef03	94	#endif
kevman	0:38ceb79fef03	95	#else
kevman	0:38ceb79fef03	96	#define __DSP_USED 0U
kevman	0:38ceb79fef03	97	#endif
kevman	0:38ceb79fef03	98
kevman	0:38ceb79fef03	99	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
kevman	0:38ceb79fef03	100	#if defined (__ARM_PCS_VFP)
kevman	0:38ceb79fef03	101	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kevman	0:38ceb79fef03	102	#define __FPU_USED 1U
kevman	0:38ceb79fef03	103	#else
kevman	0:38ceb79fef03	104	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman	0:38ceb79fef03	105	#define __FPU_USED 0U
kevman	0:38ceb79fef03	106	#endif
kevman	0:38ceb79fef03	107	#else
kevman	0:38ceb79fef03	108	#define __FPU_USED 0U
kevman	0:38ceb79fef03	109	#endif
kevman	0:38ceb79fef03	110
kevman	0:38ceb79fef03	111	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
kevman	0:38ceb79fef03	112	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
kevman	0:38ceb79fef03	113	#define __DSP_USED 1U
kevman	0:38ceb79fef03	114	#else
kevman	0:38ceb79fef03	115	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
kevman	0:38ceb79fef03	116	#define __DSP_USED 0U
kevman	0:38ceb79fef03	117	#endif
kevman	0:38ceb79fef03	118	#else
kevman	0:38ceb79fef03	119	#define __DSP_USED 0U
kevman	0:38ceb79fef03	120	#endif
kevman	0:38ceb79fef03	121
kevman	0:38ceb79fef03	122	#elif defined ( __GNUC__ )
kevman	0:38ceb79fef03	123	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
kevman	0:38ceb79fef03	124	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kevman	0:38ceb79fef03	125	#define __FPU_USED 1U
kevman	0:38ceb79fef03	126	#else
kevman	0:38ceb79fef03	127	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman	0:38ceb79fef03	128	#define __FPU_USED 0U
kevman	0:38ceb79fef03	129	#endif
kevman	0:38ceb79fef03	130	#else
kevman	0:38ceb79fef03	131	#define __FPU_USED 0U
kevman	0:38ceb79fef03	132	#endif
kevman	0:38ceb79fef03	133
kevman	0:38ceb79fef03	134	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
kevman	0:38ceb79fef03	135	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
kevman	0:38ceb79fef03	136	#define __DSP_USED 1U
kevman	0:38ceb79fef03	137	#else
kevman	0:38ceb79fef03	138	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
kevman	0:38ceb79fef03	139	#define __DSP_USED 0U
kevman	0:38ceb79fef03	140	#endif
kevman	0:38ceb79fef03	141	#else
kevman	0:38ceb79fef03	142	#define __DSP_USED 0U
kevman	0:38ceb79fef03	143	#endif
kevman	0:38ceb79fef03	144
kevman	0:38ceb79fef03	145	#elif defined ( __ICCARM__ )
kevman	0:38ceb79fef03	146	#if defined (__ARMVFP__)
kevman	0:38ceb79fef03	147	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kevman	0:38ceb79fef03	148	#define __FPU_USED 1U
kevman	0:38ceb79fef03	149	#else
kevman	0:38ceb79fef03	150	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman	0:38ceb79fef03	151	#define __FPU_USED 0U
kevman	0:38ceb79fef03	152	#endif
kevman	0:38ceb79fef03	153	#else
kevman	0:38ceb79fef03	154	#define __FPU_USED 0U
kevman	0:38ceb79fef03	155	#endif
kevman	0:38ceb79fef03	156
kevman	0:38ceb79fef03	157	#if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
kevman	0:38ceb79fef03	158	#if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
kevman	0:38ceb79fef03	159	#define __DSP_USED 1U
kevman	0:38ceb79fef03	160	#else
kevman	0:38ceb79fef03	161	#error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
kevman	0:38ceb79fef03	162	#define __DSP_USED 0U
kevman	0:38ceb79fef03	163	#endif
kevman	0:38ceb79fef03	164	#else
kevman	0:38ceb79fef03	165	#define __DSP_USED 0U
kevman	0:38ceb79fef03	166	#endif
kevman	0:38ceb79fef03	167
kevman	0:38ceb79fef03	168	#elif defined ( __TI_ARM__ )
kevman	0:38ceb79fef03	169	#if defined (__TI_VFP_SUPPORT__)
kevman	0:38ceb79fef03	170	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kevman	0:38ceb79fef03	171	#define __FPU_USED 1U
kevman	0:38ceb79fef03	172	#else
kevman	0:38ceb79fef03	173	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman	0:38ceb79fef03	174	#define __FPU_USED 0U
kevman	0:38ceb79fef03	175	#endif
kevman	0:38ceb79fef03	176	#else
kevman	0:38ceb79fef03	177	#define __FPU_USED 0U
kevman	0:38ceb79fef03	178	#endif
kevman	0:38ceb79fef03	179
kevman	0:38ceb79fef03	180	#elif defined ( __TASKING__ )
kevman	0:38ceb79fef03	181	#if defined (__FPU_VFP__)
kevman	0:38ceb79fef03	182	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kevman	0:38ceb79fef03	183	#define __FPU_USED 1U
kevman	0:38ceb79fef03	184	#else
kevman	0:38ceb79fef03	185	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman	0:38ceb79fef03	186	#define __FPU_USED 0U
kevman	0:38ceb79fef03	187	#endif
kevman	0:38ceb79fef03	188	#else
kevman	0:38ceb79fef03	189	#define __FPU_USED 0U
kevman	0:38ceb79fef03	190	#endif
kevman	0:38ceb79fef03	191
kevman	0:38ceb79fef03	192	#elif defined ( __CSMC__ )
kevman	0:38ceb79fef03	193	#if ( __CSMC__ & 0x400U)
kevman	0:38ceb79fef03	194	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
kevman	0:38ceb79fef03	195	#define __FPU_USED 1U
kevman	0:38ceb79fef03	196	#else
kevman	0:38ceb79fef03	197	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman	0:38ceb79fef03	198	#define __FPU_USED 0U
kevman	0:38ceb79fef03	199	#endif
kevman	0:38ceb79fef03	200	#else
kevman	0:38ceb79fef03	201	#define __FPU_USED 0U
kevman	0:38ceb79fef03	202	#endif
kevman	0:38ceb79fef03	203
kevman	0:38ceb79fef03	204	#endif
kevman	0:38ceb79fef03	205
kevman	0:38ceb79fef03	206	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
kevman	0:38ceb79fef03	207
kevman	0:38ceb79fef03	208
kevman	0:38ceb79fef03	209	#ifdef __cplusplus
kevman	0:38ceb79fef03	210	}
kevman	0:38ceb79fef03	211	#endif
kevman	0:38ceb79fef03	212
kevman	0:38ceb79fef03	213	#endif /* __CORE_CM33_H_GENERIC */
kevman	0:38ceb79fef03	214
kevman	0:38ceb79fef03	215	#ifndef __CMSIS_GENERIC
kevman	0:38ceb79fef03	216
kevman	0:38ceb79fef03	217	#ifndef __CORE_CM33_H_DEPENDANT
kevman	0:38ceb79fef03	218	#define __CORE_CM33_H_DEPENDANT
kevman	0:38ceb79fef03	219
kevman	0:38ceb79fef03	220	#ifdef __cplusplus
kevman	0:38ceb79fef03	221	extern "C" {
kevman	0:38ceb79fef03	222	#endif
kevman	0:38ceb79fef03	223
kevman	0:38ceb79fef03	224	/* check device defines and use defaults */
kevman	0:38ceb79fef03	225	#if defined __CHECK_DEVICE_DEFINES
kevman	0:38ceb79fef03	226	#ifndef __CM33_REV
kevman	0:38ceb79fef03	227	#define __CM33_REV 0x0000U
kevman	0:38ceb79fef03	228	#warning "__CM33_REV not defined in device header file; using default!"
kevman	0:38ceb79fef03	229	#endif
kevman	0:38ceb79fef03	230
kevman	0:38ceb79fef03	231	#ifndef __FPU_PRESENT
kevman	0:38ceb79fef03	232	#define __FPU_PRESENT 0U
kevman	0:38ceb79fef03	233	#warning "__FPU_PRESENT not defined in device header file; using default!"
kevman	0:38ceb79fef03	234	#endif
kevman	0:38ceb79fef03	235
kevman	0:38ceb79fef03	236	#ifndef __MPU_PRESENT
kevman	0:38ceb79fef03	237	#define __MPU_PRESENT 0U
kevman	0:38ceb79fef03	238	#warning "__MPU_PRESENT not defined in device header file; using default!"
kevman	0:38ceb79fef03	239	#endif
kevman	0:38ceb79fef03	240
kevman	0:38ceb79fef03	241	#ifndef __SAUREGION_PRESENT
kevman	0:38ceb79fef03	242	#define __SAUREGION_PRESENT 0U
kevman	0:38ceb79fef03	243	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
kevman	0:38ceb79fef03	244	#endif
kevman	0:38ceb79fef03	245
kevman	0:38ceb79fef03	246	#ifndef __DSP_PRESENT
kevman	0:38ceb79fef03	247	#define __DSP_PRESENT 0U
kevman	0:38ceb79fef03	248	#warning "__DSP_PRESENT not defined in device header file; using default!"
kevman	0:38ceb79fef03	249	#endif
kevman	0:38ceb79fef03	250
kevman	0:38ceb79fef03	251	#ifndef __NVIC_PRIO_BITS
kevman	0:38ceb79fef03	252	#define __NVIC_PRIO_BITS 3U
kevman	0:38ceb79fef03	253	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
kevman	0:38ceb79fef03	254	#endif
kevman	0:38ceb79fef03	255
kevman	0:38ceb79fef03	256	#ifndef __Vendor_SysTickConfig
kevman	0:38ceb79fef03	257	#define __Vendor_SysTickConfig 0U
kevman	0:38ceb79fef03	258	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
kevman	0:38ceb79fef03	259	#endif
kevman	0:38ceb79fef03	260	#endif
kevman	0:38ceb79fef03	261
kevman	0:38ceb79fef03	262	/* IO definitions (access restrictions to peripheral registers) */
kevman	0:38ceb79fef03	263	/**
kevman	0:38ceb79fef03	264	\defgroup CMSIS_glob_defs CMSIS Global Defines
kevman	0:38ceb79fef03	265
kevman	0:38ceb79fef03	266	<strong>IO Type Qualifiers</strong> are used
kevman	0:38ceb79fef03	267	\li to specify the access to peripheral variables.
kevman	0:38ceb79fef03	268	\li for automatic generation of peripheral register debug information.
kevman	0:38ceb79fef03	269	*/
kevman	0:38ceb79fef03	270	#ifdef __cplusplus
kevman	0:38ceb79fef03	271	#define __I volatile /!< Defines 'read only' permissions /
kevman	0:38ceb79fef03	272	#else
kevman	0:38ceb79fef03	273	#define __I volatile const /!< Defines 'read only' permissions /
kevman	0:38ceb79fef03	274	#endif
kevman	0:38ceb79fef03	275	#define __O volatile /!< Defines 'write only' permissions /
kevman	0:38ceb79fef03	276	#define __IO volatile /!< Defines 'read / write' permissions /
kevman	0:38ceb79fef03	277
kevman	0:38ceb79fef03	278	/* following defines should be used for structure members */
kevman	0:38ceb79fef03	279	#define __IM volatile const /! Defines 'read only' structure member permissions /
kevman	0:38ceb79fef03	280	#define __OM volatile /! Defines 'write only' structure member permissions /
kevman	0:38ceb79fef03	281	#define __IOM volatile /! Defines 'read / write' structure member permissions /
kevman	0:38ceb79fef03	282
kevman	0:38ceb79fef03	283	/@} end of group Cortex_M33 /
kevman	0:38ceb79fef03	284
kevman	0:38ceb79fef03	285
kevman	0:38ceb79fef03	286
kevman	0:38ceb79fef03	287	/*******************************************************************************
kevman	0:38ceb79fef03	288	* Register Abstraction
kevman	0:38ceb79fef03	289	Core Register contain:
kevman	0:38ceb79fef03	290	- Core Register
kevman	0:38ceb79fef03	291	- Core NVIC Register
kevman	0:38ceb79fef03	292	- Core SCB Register
kevman	0:38ceb79fef03	293	- Core SysTick Register
kevman	0:38ceb79fef03	294	- Core Debug Register
kevman	0:38ceb79fef03	295	- Core MPU Register
kevman	0:38ceb79fef03	296	- Core SAU Register
kevman	0:38ceb79fef03	297	- Core FPU Register
kevman	0:38ceb79fef03	298	******************************************************************************/
kevman	0:38ceb79fef03	299	/**
kevman	0:38ceb79fef03	300	\defgroup CMSIS_core_register Defines and Type Definitions
kevman	0:38ceb79fef03	301	\brief Type definitions and defines for Cortex-M processor based devices.
kevman	0:38ceb79fef03	302	*/
kevman	0:38ceb79fef03	303
kevman	0:38ceb79fef03	304	/**
kevman	0:38ceb79fef03	305	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	306	\defgroup CMSIS_CORE Status and Control Registers
kevman	0:38ceb79fef03	307	\brief Core Register type definitions.
kevman	0:38ceb79fef03	308	@{
kevman	0:38ceb79fef03	309	*/
kevman	0:38ceb79fef03	310
kevman	0:38ceb79fef03	311	/**
kevman	0:38ceb79fef03	312	\brief Union type to access the Application Program Status Register (APSR).
kevman	0:38ceb79fef03	313	*/
kevman	0:38ceb79fef03	314	typedef union
kevman	0:38ceb79fef03	315	{
kevman	0:38ceb79fef03	316	struct
kevman	0:38ceb79fef03	317	{
kevman	0:38ceb79fef03	318	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
kevman	0:38ceb79fef03	319	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
kevman	0:38ceb79fef03	320	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
kevman	0:38ceb79fef03	321	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
kevman	0:38ceb79fef03	322	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kevman	0:38ceb79fef03	323	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kevman	0:38ceb79fef03	324	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kevman	0:38ceb79fef03	325	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kevman	0:38ceb79fef03	326	} b; /!< Structure used for bit access /
kevman	0:38ceb79fef03	327	uint32_t w; /!< Type used for word access /
kevman	0:38ceb79fef03	328	} APSR_Type;
kevman	0:38ceb79fef03	329
kevman	0:38ceb79fef03	330	/* APSR Register Definitions */
kevman	0:38ceb79fef03	331	#define APSR_N_Pos 31U /!< APSR: N Position /
kevman	0:38ceb79fef03	332	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
kevman	0:38ceb79fef03	333
kevman	0:38ceb79fef03	334	#define APSR_Z_Pos 30U /!< APSR: Z Position /
kevman	0:38ceb79fef03	335	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
kevman	0:38ceb79fef03	336
kevman	0:38ceb79fef03	337	#define APSR_C_Pos 29U /!< APSR: C Position /
kevman	0:38ceb79fef03	338	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
kevman	0:38ceb79fef03	339
kevman	0:38ceb79fef03	340	#define APSR_V_Pos 28U /!< APSR: V Position /
kevman	0:38ceb79fef03	341	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
kevman	0:38ceb79fef03	342
kevman	0:38ceb79fef03	343	#define APSR_Q_Pos 27U /!< APSR: Q Position /
kevman	0:38ceb79fef03	344	#define APSR_Q_Msk (1UL << APSR_Q_Pos) /!< APSR: Q Mask /
kevman	0:38ceb79fef03	345
kevman	0:38ceb79fef03	346	#define APSR_GE_Pos 16U /!< APSR: GE Position /
kevman	0:38ceb79fef03	347	#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /!< APSR: GE Mask /
kevman	0:38ceb79fef03	348
kevman	0:38ceb79fef03	349
kevman	0:38ceb79fef03	350	/**
kevman	0:38ceb79fef03	351	\brief Union type to access the Interrupt Program Status Register (IPSR).
kevman	0:38ceb79fef03	352	*/
kevman	0:38ceb79fef03	353	typedef union
kevman	0:38ceb79fef03	354	{
kevman	0:38ceb79fef03	355	struct
kevman	0:38ceb79fef03	356	{
kevman	0:38ceb79fef03	357	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kevman	0:38ceb79fef03	358	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
kevman	0:38ceb79fef03	359	} b; /!< Structure used for bit access /
kevman	0:38ceb79fef03	360	uint32_t w; /!< Type used for word access /
kevman	0:38ceb79fef03	361	} IPSR_Type;
kevman	0:38ceb79fef03	362
kevman	0:38ceb79fef03	363	/* IPSR Register Definitions */
kevman	0:38ceb79fef03	364	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
kevman	0:38ceb79fef03	365	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
kevman	0:38ceb79fef03	366
kevman	0:38ceb79fef03	367
kevman	0:38ceb79fef03	368	/**
kevman	0:38ceb79fef03	369	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
kevman	0:38ceb79fef03	370	*/
kevman	0:38ceb79fef03	371	typedef union
kevman	0:38ceb79fef03	372	{
kevman	0:38ceb79fef03	373	struct
kevman	0:38ceb79fef03	374	{
kevman	0:38ceb79fef03	375	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
kevman	0:38ceb79fef03	376	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
kevman	0:38ceb79fef03	377	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
kevman	0:38ceb79fef03	378	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
kevman	0:38ceb79fef03	379	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
kevman	0:38ceb79fef03	380	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
kevman	0:38ceb79fef03	381	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
kevman	0:38ceb79fef03	382	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
kevman	0:38ceb79fef03	383	uint32_t C:1; /!< bit: 29 Carry condition code flag /
kevman	0:38ceb79fef03	384	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
kevman	0:38ceb79fef03	385	uint32_t N:1; /!< bit: 31 Negative condition code flag /
kevman	0:38ceb79fef03	386	} b; /!< Structure used for bit access /
kevman	0:38ceb79fef03	387	uint32_t w; /!< Type used for word access /
kevman	0:38ceb79fef03	388	} xPSR_Type;
kevman	0:38ceb79fef03	389
kevman	0:38ceb79fef03	390	/* xPSR Register Definitions */
kevman	0:38ceb79fef03	391	#define xPSR_N_Pos 31U /!< xPSR: N Position /
kevman	0:38ceb79fef03	392	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
kevman	0:38ceb79fef03	393
kevman	0:38ceb79fef03	394	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
kevman	0:38ceb79fef03	395	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
kevman	0:38ceb79fef03	396
kevman	0:38ceb79fef03	397	#define xPSR_C_Pos 29U /!< xPSR: C Position /
kevman	0:38ceb79fef03	398	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
kevman	0:38ceb79fef03	399
kevman	0:38ceb79fef03	400	#define xPSR_V_Pos 28U /!< xPSR: V Position /
kevman	0:38ceb79fef03	401	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
kevman	0:38ceb79fef03	402
kevman	0:38ceb79fef03	403	#define xPSR_Q_Pos 27U /!< xPSR: Q Position /
kevman	0:38ceb79fef03	404	#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /!< xPSR: Q Mask /
kevman	0:38ceb79fef03	405
kevman	0:38ceb79fef03	406	#define xPSR_IT_Pos 25U /!< xPSR: IT Position /
kevman	0:38ceb79fef03	407	#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /!< xPSR: IT Mask /
kevman	0:38ceb79fef03	408
kevman	0:38ceb79fef03	409	#define xPSR_T_Pos 24U /!< xPSR: T Position /
kevman	0:38ceb79fef03	410	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
kevman	0:38ceb79fef03	411
kevman	0:38ceb79fef03	412	#define xPSR_GE_Pos 16U /!< xPSR: GE Position /
kevman	0:38ceb79fef03	413	#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /!< xPSR: GE Mask /
kevman	0:38ceb79fef03	414
kevman	0:38ceb79fef03	415	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
kevman	0:38ceb79fef03	416	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
kevman	0:38ceb79fef03	417
kevman	0:38ceb79fef03	418
kevman	0:38ceb79fef03	419	/**
kevman	0:38ceb79fef03	420	\brief Union type to access the Control Registers (CONTROL).
kevman	0:38ceb79fef03	421	*/
kevman	0:38ceb79fef03	422	typedef union
kevman	0:38ceb79fef03	423	{
kevman	0:38ceb79fef03	424	struct
kevman	0:38ceb79fef03	425	{
kevman	0:38ceb79fef03	426	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
kevman	0:38ceb79fef03	427	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
kevman	0:38ceb79fef03	428	uint32_t FPCA:1; /!< bit: 2 Floating-point context active /
kevman	0:38ceb79fef03	429	uint32_t SFPA:1; /!< bit: 3 Secure floating-point active /
kevman	0:38ceb79fef03	430	uint32_t _reserved1:28; /!< bit: 4..31 Reserved /
kevman	0:38ceb79fef03	431	} b; /!< Structure used for bit access /
kevman	0:38ceb79fef03	432	uint32_t w; /!< Type used for word access /
kevman	0:38ceb79fef03	433	} CONTROL_Type;
kevman	0:38ceb79fef03	434
kevman	0:38ceb79fef03	435	/* CONTROL Register Definitions */
kevman	0:38ceb79fef03	436	#define CONTROL_SFPA_Pos 3U /!< CONTROL: SFPA Position /
kevman	0:38ceb79fef03	437	#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /!< CONTROL: SFPA Mask /
kevman	0:38ceb79fef03	438
kevman	0:38ceb79fef03	439	#define CONTROL_FPCA_Pos 2U /!< CONTROL: FPCA Position /
kevman	0:38ceb79fef03	440	#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /!< CONTROL: FPCA Mask /
kevman	0:38ceb79fef03	441
kevman	0:38ceb79fef03	442	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
kevman	0:38ceb79fef03	443	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
kevman	0:38ceb79fef03	444
kevman	0:38ceb79fef03	445	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
kevman	0:38ceb79fef03	446	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
kevman	0:38ceb79fef03	447
kevman	0:38ceb79fef03	448	/@} end of group CMSIS_CORE /
kevman	0:38ceb79fef03	449
kevman	0:38ceb79fef03	450
kevman	0:38ceb79fef03	451	/**
kevman	0:38ceb79fef03	452	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	453	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
kevman	0:38ceb79fef03	454	\brief Type definitions for the NVIC Registers
kevman	0:38ceb79fef03	455	@{
kevman	0:38ceb79fef03	456	*/
kevman	0:38ceb79fef03	457
kevman	0:38ceb79fef03	458	/**
kevman	0:38ceb79fef03	459	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
kevman	0:38ceb79fef03	460	*/
kevman	0:38ceb79fef03	461	typedef struct
kevman	0:38ceb79fef03	462	{
kevman	0:38ceb79fef03	463	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
kevman	0:38ceb79fef03	464	uint32_t RESERVED0[16U];
kevman	0:38ceb79fef03	465	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
kevman	0:38ceb79fef03	466	uint32_t RSERVED1[16U];
kevman	0:38ceb79fef03	467	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
kevman	0:38ceb79fef03	468	uint32_t RESERVED2[16U];
kevman	0:38ceb79fef03	469	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
kevman	0:38ceb79fef03	470	uint32_t RESERVED3[16U];
kevman	0:38ceb79fef03	471	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
kevman	0:38ceb79fef03	472	uint32_t RESERVED4[16U];
kevman	0:38ceb79fef03	473	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
kevman	0:38ceb79fef03	474	uint32_t RESERVED5[16U];
kevman	0:38ceb79fef03	475	__IOM uint8_t IPR[496U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
kevman	0:38ceb79fef03	476	uint32_t RESERVED6[580U];
kevman	0:38ceb79fef03	477	__OM uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
kevman	0:38ceb79fef03	478	} NVIC_Type;
kevman	0:38ceb79fef03	479
kevman	0:38ceb79fef03	480	/* Software Triggered Interrupt Register Definitions */
kevman	0:38ceb79fef03	481	#define NVIC_STIR_INTID_Pos 0U /!< STIR: INTLINESNUM Position /
kevman	0:38ceb79fef03	482	#define NVIC_STIR_INTID_Msk (0x1FFUL /<< NVIC_STIR_INTID_Pos/) /!< STIR: INTLINESNUM Mask /
kevman	0:38ceb79fef03	483
kevman	0:38ceb79fef03	484	/@} end of group CMSIS_NVIC /
kevman	0:38ceb79fef03	485
kevman	0:38ceb79fef03	486
kevman	0:38ceb79fef03	487	/**
kevman	0:38ceb79fef03	488	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	489	\defgroup CMSIS_SCB System Control Block (SCB)
kevman	0:38ceb79fef03	490	\brief Type definitions for the System Control Block Registers
kevman	0:38ceb79fef03	491	@{
kevman	0:38ceb79fef03	492	*/
kevman	0:38ceb79fef03	493
kevman	0:38ceb79fef03	494	/**
kevman	0:38ceb79fef03	495	\brief Structure type to access the System Control Block (SCB).
kevman	0:38ceb79fef03	496	*/
kevman	0:38ceb79fef03	497	typedef struct
kevman	0:38ceb79fef03	498	{
kevman	0:38ceb79fef03	499	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
kevman	0:38ceb79fef03	500	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
kevman	0:38ceb79fef03	501	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
kevman	0:38ceb79fef03	502	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
kevman	0:38ceb79fef03	503	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
kevman	0:38ceb79fef03	504	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
kevman	0:38ceb79fef03	505	__IOM uint8_t SHPR[12U]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
kevman	0:38ceb79fef03	506	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
kevman	0:38ceb79fef03	507	__IOM uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
kevman	0:38ceb79fef03	508	__IOM uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
kevman	0:38ceb79fef03	509	__IOM uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
kevman	0:38ceb79fef03	510	__IOM uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
kevman	0:38ceb79fef03	511	__IOM uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
kevman	0:38ceb79fef03	512	__IOM uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
kevman	0:38ceb79fef03	513	__IM uint32_t ID_PFR[2U]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
kevman	0:38ceb79fef03	514	__IM uint32_t ID_DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
kevman	0:38ceb79fef03	515	__IM uint32_t ID_ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
kevman	0:38ceb79fef03	516	__IM uint32_t ID_MMFR[4U]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
kevman	0:38ceb79fef03	517	__IM uint32_t ID_ISAR[6U]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
kevman	0:38ceb79fef03	518	__IM uint32_t CLIDR; /!< Offset: 0x078 (R/ ) Cache Level ID register /
kevman	0:38ceb79fef03	519	__IM uint32_t CTR; /!< Offset: 0x07C (R/ ) Cache Type register /
kevman	0:38ceb79fef03	520	__IM uint32_t CCSIDR; /!< Offset: 0x080 (R/ ) Cache Size ID Register /
kevman	0:38ceb79fef03	521	__IOM uint32_t CSSELR; /!< Offset: 0x084 (R/W) Cache Size Selection Register /
kevman	0:38ceb79fef03	522	__IOM uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
kevman	0:38ceb79fef03	523	__IOM uint32_t NSACR; /!< Offset: 0x08C (R/W) Non-Secure Access Control Register /
kevman	0:38ceb79fef03	524	uint32_t RESERVED3[92U];
kevman	0:38ceb79fef03	525	__OM uint32_t STIR; /!< Offset: 0x200 ( /W) Software Triggered Interrupt Register /
kevman	0:38ceb79fef03	526	uint32_t RESERVED4[15U];
kevman	0:38ceb79fef03	527	__IM uint32_t MVFR0; /!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 /
kevman	0:38ceb79fef03	528	__IM uint32_t MVFR1; /!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 /
kevman	0:38ceb79fef03	529	__IM uint32_t MVFR2; /!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 /
kevman	0:38ceb79fef03	530	uint32_t RESERVED5[1U];
kevman	0:38ceb79fef03	531	__OM uint32_t ICIALLU; /!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU /
kevman	0:38ceb79fef03	532	uint32_t RESERVED6[1U];
kevman	0:38ceb79fef03	533	__OM uint32_t ICIMVAU; /!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU /
kevman	0:38ceb79fef03	534	__OM uint32_t DCIMVAC; /!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC /
kevman	0:38ceb79fef03	535	__OM uint32_t DCISW; /!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way /
kevman	0:38ceb79fef03	536	__OM uint32_t DCCMVAU; /!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU /
kevman	0:38ceb79fef03	537	__OM uint32_t DCCMVAC; /!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC /
kevman	0:38ceb79fef03	538	__OM uint32_t DCCSW; /!< Offset: 0x26C ( /W) D-Cache Clean by Set-way /
kevman	0:38ceb79fef03	539	__OM uint32_t DCCIMVAC; /!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC /
kevman	0:38ceb79fef03	540	__OM uint32_t DCCISW; /!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way /
kevman	0:38ceb79fef03	541	uint32_t RESERVED7[6U];
kevman	0:38ceb79fef03	542	__IOM uint32_t ITCMCR; /!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register /
kevman	0:38ceb79fef03	543	__IOM uint32_t DTCMCR; /!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers /
kevman	0:38ceb79fef03	544	__IOM uint32_t AHBPCR; /!< Offset: 0x298 (R/W) AHBP Control Register /
kevman	0:38ceb79fef03	545	__IOM uint32_t CACR; /!< Offset: 0x29C (R/W) L1 Cache Control Register /
kevman	0:38ceb79fef03	546	__IOM uint32_t AHBSCR; /!< Offset: 0x2A0 (R/W) AHB Slave Control Register /
kevman	0:38ceb79fef03	547	uint32_t RESERVED8[1U];
kevman	0:38ceb79fef03	548	__IOM uint32_t ABFSR; /!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register /
kevman	0:38ceb79fef03	549	} SCB_Type;
kevman	0:38ceb79fef03	550
kevman	0:38ceb79fef03	551	/* SCB CPUID Register Definitions */
kevman	0:38ceb79fef03	552	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
kevman	0:38ceb79fef03	553	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
kevman	0:38ceb79fef03	554
kevman	0:38ceb79fef03	555	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
kevman	0:38ceb79fef03	556	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
kevman	0:38ceb79fef03	557
kevman	0:38ceb79fef03	558	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
kevman	0:38ceb79fef03	559	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
kevman	0:38ceb79fef03	560
kevman	0:38ceb79fef03	561	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
kevman	0:38ceb79fef03	562	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
kevman	0:38ceb79fef03	563
kevman	0:38ceb79fef03	564	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
kevman	0:38ceb79fef03	565	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
kevman	0:38ceb79fef03	566
kevman	0:38ceb79fef03	567	/* SCB Interrupt Control State Register Definitions */
kevman	0:38ceb79fef03	568	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
kevman	0:38ceb79fef03	569	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
kevman	0:38ceb79fef03	570
kevman	0:38ceb79fef03	571	#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /!< SCB ICSR: NMIPENDSET Position, backward compatibility /
kevman	0:38ceb79fef03	572	#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /!< SCB ICSR: NMIPENDSET Mask, backward compatibility /
kevman	0:38ceb79fef03	573
kevman	0:38ceb79fef03	574	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
kevman	0:38ceb79fef03	575	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
kevman	0:38ceb79fef03	576
kevman	0:38ceb79fef03	577	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
kevman	0:38ceb79fef03	578	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
kevman	0:38ceb79fef03	579
kevman	0:38ceb79fef03	580	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
kevman	0:38ceb79fef03	581	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
kevman	0:38ceb79fef03	582
kevman	0:38ceb79fef03	583	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
kevman	0:38ceb79fef03	584	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
kevman	0:38ceb79fef03	585
kevman	0:38ceb79fef03	586	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
kevman	0:38ceb79fef03	587	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
kevman	0:38ceb79fef03	588
kevman	0:38ceb79fef03	589	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
kevman	0:38ceb79fef03	590	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
kevman	0:38ceb79fef03	591
kevman	0:38ceb79fef03	592	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
kevman	0:38ceb79fef03	593	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
kevman	0:38ceb79fef03	594
kevman	0:38ceb79fef03	595	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
kevman	0:38ceb79fef03	596	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
kevman	0:38ceb79fef03	597
kevman	0:38ceb79fef03	598	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
kevman	0:38ceb79fef03	599	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
kevman	0:38ceb79fef03	600
kevman	0:38ceb79fef03	601	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
kevman	0:38ceb79fef03	602	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
kevman	0:38ceb79fef03	603
kevman	0:38ceb79fef03	604	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
kevman	0:38ceb79fef03	605	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
kevman	0:38ceb79fef03	606
kevman	0:38ceb79fef03	607	/* SCB Vector Table Offset Register Definitions */
kevman	0:38ceb79fef03	608	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
kevman	0:38ceb79fef03	609	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
kevman	0:38ceb79fef03	610
kevman	0:38ceb79fef03	611	/* SCB Application Interrupt and Reset Control Register Definitions */
kevman	0:38ceb79fef03	612	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
kevman	0:38ceb79fef03	613	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
kevman	0:38ceb79fef03	614
kevman	0:38ceb79fef03	615	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
kevman	0:38ceb79fef03	616	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
kevman	0:38ceb79fef03	617
kevman	0:38ceb79fef03	618	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
kevman	0:38ceb79fef03	619	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
kevman	0:38ceb79fef03	620
kevman	0:38ceb79fef03	621	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
kevman	0:38ceb79fef03	622	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
kevman	0:38ceb79fef03	623
kevman	0:38ceb79fef03	624	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
kevman	0:38ceb79fef03	625	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
kevman	0:38ceb79fef03	626
kevman	0:38ceb79fef03	627	#define SCB_AIRCR_PRIGROUP_Pos 8U /!< SCB AIRCR: PRIGROUP Position /
kevman	0:38ceb79fef03	628	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
kevman	0:38ceb79fef03	629
kevman	0:38ceb79fef03	630	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
kevman	0:38ceb79fef03	631	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
kevman	0:38ceb79fef03	632
kevman	0:38ceb79fef03	633	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
kevman	0:38ceb79fef03	634	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
kevman	0:38ceb79fef03	635
kevman	0:38ceb79fef03	636	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
kevman	0:38ceb79fef03	637	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
kevman	0:38ceb79fef03	638
kevman	0:38ceb79fef03	639	/* SCB System Control Register Definitions */
kevman	0:38ceb79fef03	640	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
kevman	0:38ceb79fef03	641	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
kevman	0:38ceb79fef03	642
kevman	0:38ceb79fef03	643	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
kevman	0:38ceb79fef03	644	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
kevman	0:38ceb79fef03	645
kevman	0:38ceb79fef03	646	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
kevman	0:38ceb79fef03	647	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
kevman	0:38ceb79fef03	648
kevman	0:38ceb79fef03	649	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
kevman	0:38ceb79fef03	650	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
kevman	0:38ceb79fef03	651
kevman	0:38ceb79fef03	652	/* SCB Configuration Control Register Definitions */
kevman	0:38ceb79fef03	653	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
kevman	0:38ceb79fef03	654	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
kevman	0:38ceb79fef03	655
kevman	0:38ceb79fef03	656	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
kevman	0:38ceb79fef03	657	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
kevman	0:38ceb79fef03	658
kevman	0:38ceb79fef03	659	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
kevman	0:38ceb79fef03	660	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
kevman	0:38ceb79fef03	661
kevman	0:38ceb79fef03	662	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
kevman	0:38ceb79fef03	663	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
kevman	0:38ceb79fef03	664
kevman	0:38ceb79fef03	665	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
kevman	0:38ceb79fef03	666	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
kevman	0:38ceb79fef03	667
kevman	0:38ceb79fef03	668	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
kevman	0:38ceb79fef03	669	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
kevman	0:38ceb79fef03	670
kevman	0:38ceb79fef03	671	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
kevman	0:38ceb79fef03	672	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
kevman	0:38ceb79fef03	673
kevman	0:38ceb79fef03	674	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
kevman	0:38ceb79fef03	675	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
kevman	0:38ceb79fef03	676
kevman	0:38ceb79fef03	677	/* SCB System Handler Control and State Register Definitions */
kevman	0:38ceb79fef03	678	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
kevman	0:38ceb79fef03	679	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
kevman	0:38ceb79fef03	680
kevman	0:38ceb79fef03	681	#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /!< SCB SHCSR: SECUREFAULTPENDED Position /
kevman	0:38ceb79fef03	682	#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /!< SCB SHCSR: SECUREFAULTPENDED Mask /
kevman	0:38ceb79fef03	683
kevman	0:38ceb79fef03	684	#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /!< SCB SHCSR: SECUREFAULTENA Position /
kevman	0:38ceb79fef03	685	#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /!< SCB SHCSR: SECUREFAULTENA Mask /
kevman	0:38ceb79fef03	686
kevman	0:38ceb79fef03	687	#define SCB_SHCSR_USGFAULTENA_Pos 18U /!< SCB SHCSR: USGFAULTENA Position /
kevman	0:38ceb79fef03	688	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
kevman	0:38ceb79fef03	689
kevman	0:38ceb79fef03	690	#define SCB_SHCSR_BUSFAULTENA_Pos 17U /!< SCB SHCSR: BUSFAULTENA Position /
kevman	0:38ceb79fef03	691	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
kevman	0:38ceb79fef03	692
kevman	0:38ceb79fef03	693	#define SCB_SHCSR_MEMFAULTENA_Pos 16U /!< SCB SHCSR: MEMFAULTENA Position /
kevman	0:38ceb79fef03	694	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
kevman	0:38ceb79fef03	695
kevman	0:38ceb79fef03	696	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
kevman	0:38ceb79fef03	697	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
kevman	0:38ceb79fef03	698
kevman	0:38ceb79fef03	699	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /!< SCB SHCSR: BUSFAULTPENDED Position /
kevman	0:38ceb79fef03	700	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
kevman	0:38ceb79fef03	701
kevman	0:38ceb79fef03	702	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /!< SCB SHCSR: MEMFAULTPENDED Position /
kevman	0:38ceb79fef03	703	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
kevman	0:38ceb79fef03	704
kevman	0:38ceb79fef03	705	#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /!< SCB SHCSR: USGFAULTPENDED Position /
kevman	0:38ceb79fef03	706	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
kevman	0:38ceb79fef03	707
kevman	0:38ceb79fef03	708	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
kevman	0:38ceb79fef03	709	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
kevman	0:38ceb79fef03	710
kevman	0:38ceb79fef03	711	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
kevman	0:38ceb79fef03	712	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
kevman	0:38ceb79fef03	713
kevman	0:38ceb79fef03	714	#define SCB_SHCSR_MONITORACT_Pos 8U /!< SCB SHCSR: MONITORACT Position /
kevman	0:38ceb79fef03	715	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
kevman	0:38ceb79fef03	716
kevman	0:38ceb79fef03	717	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
kevman	0:38ceb79fef03	718	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
kevman	0:38ceb79fef03	719
kevman	0:38ceb79fef03	720	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
kevman	0:38ceb79fef03	721	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
kevman	0:38ceb79fef03	722
kevman	0:38ceb79fef03	723	#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /!< SCB SHCSR: SECUREFAULTACT Position /
kevman	0:38ceb79fef03	724	#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /!< SCB SHCSR: SECUREFAULTACT Mask /
kevman	0:38ceb79fef03	725
kevman	0:38ceb79fef03	726	#define SCB_SHCSR_USGFAULTACT_Pos 3U /!< SCB SHCSR: USGFAULTACT Position /
kevman	0:38ceb79fef03	727	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
kevman	0:38ceb79fef03	728
kevman	0:38ceb79fef03	729	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
kevman	0:38ceb79fef03	730	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
kevman	0:38ceb79fef03	731
kevman	0:38ceb79fef03	732	#define SCB_SHCSR_BUSFAULTACT_Pos 1U /!< SCB SHCSR: BUSFAULTACT Position /
kevman	0:38ceb79fef03	733	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
kevman	0:38ceb79fef03	734
kevman	0:38ceb79fef03	735	#define SCB_SHCSR_MEMFAULTACT_Pos 0U /!< SCB SHCSR: MEMFAULTACT Position /
kevman	0:38ceb79fef03	736	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /<< SCB_SHCSR_MEMFAULTACT_Pos/) /!< SCB SHCSR: MEMFAULTACT Mask /
kevman	0:38ceb79fef03	737
kevman	0:38ceb79fef03	738	/* SCB Configurable Fault Status Register Definitions */
kevman	0:38ceb79fef03	739	#define SCB_CFSR_USGFAULTSR_Pos 16U /!< SCB CFSR: Usage Fault Status Register Position /
kevman	0:38ceb79fef03	740	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
kevman	0:38ceb79fef03	741
kevman	0:38ceb79fef03	742	#define SCB_CFSR_BUSFAULTSR_Pos 8U /!< SCB CFSR: Bus Fault Status Register Position /
kevman	0:38ceb79fef03	743	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
kevman	0:38ceb79fef03	744
kevman	0:38ceb79fef03	745	#define SCB_CFSR_MEMFAULTSR_Pos 0U /!< SCB CFSR: Memory Manage Fault Status Register Position /
kevman	0:38ceb79fef03	746	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /<< SCB_CFSR_MEMFAULTSR_Pos/) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
kevman	0:38ceb79fef03	747
kevman	0:38ceb79fef03	748	/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
kevman	0:38ceb79fef03	749	#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /!< SCB CFSR (MMFSR): MMARVALID Position /
kevman	0:38ceb79fef03	750	#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /!< SCB CFSR (MMFSR): MMARVALID Mask /
kevman	0:38ceb79fef03	751
kevman	0:38ceb79fef03	752	#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /!< SCB CFSR (MMFSR): MLSPERR Position /
kevman	0:38ceb79fef03	753	#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /!< SCB CFSR (MMFSR): MLSPERR Mask /
kevman	0:38ceb79fef03	754
kevman	0:38ceb79fef03	755	#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /!< SCB CFSR (MMFSR): MSTKERR Position /
kevman	0:38ceb79fef03	756	#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /!< SCB CFSR (MMFSR): MSTKERR Mask /
kevman	0:38ceb79fef03	757
kevman	0:38ceb79fef03	758	#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /!< SCB CFSR (MMFSR): MUNSTKERR Position /
kevman	0:38ceb79fef03	759	#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /!< SCB CFSR (MMFSR): MUNSTKERR Mask /
kevman	0:38ceb79fef03	760
kevman	0:38ceb79fef03	761	#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /!< SCB CFSR (MMFSR): DACCVIOL Position /
kevman	0:38ceb79fef03	762	#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /!< SCB CFSR (MMFSR): DACCVIOL Mask /
kevman	0:38ceb79fef03	763
kevman	0:38ceb79fef03	764	#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /!< SCB CFSR (MMFSR): IACCVIOL Position /
kevman	0:38ceb79fef03	765	#define SCB_CFSR_IACCVIOL_Msk (1UL /<< SCB_CFSR_IACCVIOL_Pos/) /!< SCB CFSR (MMFSR): IACCVIOL Mask /
kevman	0:38ceb79fef03	766
kevman	0:38ceb79fef03	767	/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
kevman	0:38ceb79fef03	768	#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /!< SCB CFSR (BFSR): BFARVALID Position /
kevman	0:38ceb79fef03	769	#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /!< SCB CFSR (BFSR): BFARVALID Mask /
kevman	0:38ceb79fef03	770
kevman	0:38ceb79fef03	771	#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /!< SCB CFSR (BFSR): LSPERR Position /
kevman	0:38ceb79fef03	772	#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /!< SCB CFSR (BFSR): LSPERR Mask /
kevman	0:38ceb79fef03	773
kevman	0:38ceb79fef03	774	#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /!< SCB CFSR (BFSR): STKERR Position /
kevman	0:38ceb79fef03	775	#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /!< SCB CFSR (BFSR): STKERR Mask /
kevman	0:38ceb79fef03	776
kevman	0:38ceb79fef03	777	#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /!< SCB CFSR (BFSR): UNSTKERR Position /
kevman	0:38ceb79fef03	778	#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /!< SCB CFSR (BFSR): UNSTKERR Mask /
kevman	0:38ceb79fef03	779
kevman	0:38ceb79fef03	780	#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /!< SCB CFSR (BFSR): IMPRECISERR Position /
kevman	0:38ceb79fef03	781	#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /!< SCB CFSR (BFSR): IMPRECISERR Mask /
kevman	0:38ceb79fef03	782
kevman	0:38ceb79fef03	783	#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /!< SCB CFSR (BFSR): PRECISERR Position /
kevman	0:38ceb79fef03	784	#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /!< SCB CFSR (BFSR): PRECISERR Mask /
kevman	0:38ceb79fef03	785
kevman	0:38ceb79fef03	786	#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /!< SCB CFSR (BFSR): IBUSERR Position /
kevman	0:38ceb79fef03	787	#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /!< SCB CFSR (BFSR): IBUSERR Mask /
kevman	0:38ceb79fef03	788
kevman	0:38ceb79fef03	789	/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
kevman	0:38ceb79fef03	790	#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /!< SCB CFSR (UFSR): DIVBYZERO Position /
kevman	0:38ceb79fef03	791	#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /!< SCB CFSR (UFSR): DIVBYZERO Mask /
kevman	0:38ceb79fef03	792
kevman	0:38ceb79fef03	793	#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /!< SCB CFSR (UFSR): UNALIGNED Position /
kevman	0:38ceb79fef03	794	#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /!< SCB CFSR (UFSR): UNALIGNED Mask /
kevman	0:38ceb79fef03	795
kevman	0:38ceb79fef03	796	#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /!< SCB CFSR (UFSR): STKOF Position /
kevman	0:38ceb79fef03	797	#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /!< SCB CFSR (UFSR): STKOF Mask /
kevman	0:38ceb79fef03	798
kevman	0:38ceb79fef03	799	#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /!< SCB CFSR (UFSR): NOCP Position /
kevman	0:38ceb79fef03	800	#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /!< SCB CFSR (UFSR): NOCP Mask /
kevman	0:38ceb79fef03	801
kevman	0:38ceb79fef03	802	#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /!< SCB CFSR (UFSR): INVPC Position /
kevman	0:38ceb79fef03	803	#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /!< SCB CFSR (UFSR): INVPC Mask /
kevman	0:38ceb79fef03	804
kevman	0:38ceb79fef03	805	#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /!< SCB CFSR (UFSR): INVSTATE Position /
kevman	0:38ceb79fef03	806	#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /!< SCB CFSR (UFSR): INVSTATE Mask /
kevman	0:38ceb79fef03	807
kevman	0:38ceb79fef03	808	#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /!< SCB CFSR (UFSR): UNDEFINSTR Position /
kevman	0:38ceb79fef03	809	#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /!< SCB CFSR (UFSR): UNDEFINSTR Mask /
kevman	0:38ceb79fef03	810
kevman	0:38ceb79fef03	811	/* SCB Hard Fault Status Register Definitions */
kevman	0:38ceb79fef03	812	#define SCB_HFSR_DEBUGEVT_Pos 31U /!< SCB HFSR: DEBUGEVT Position /
kevman	0:38ceb79fef03	813	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
kevman	0:38ceb79fef03	814
kevman	0:38ceb79fef03	815	#define SCB_HFSR_FORCED_Pos 30U /!< SCB HFSR: FORCED Position /
kevman	0:38ceb79fef03	816	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
kevman	0:38ceb79fef03	817
kevman	0:38ceb79fef03	818	#define SCB_HFSR_VECTTBL_Pos 1U /!< SCB HFSR: VECTTBL Position /
kevman	0:38ceb79fef03	819	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
kevman	0:38ceb79fef03	820
kevman	0:38ceb79fef03	821	/* SCB Debug Fault Status Register Definitions */
kevman	0:38ceb79fef03	822	#define SCB_DFSR_EXTERNAL_Pos 4U /!< SCB DFSR: EXTERNAL Position /
kevman	0:38ceb79fef03	823	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
kevman	0:38ceb79fef03	824
kevman	0:38ceb79fef03	825	#define SCB_DFSR_VCATCH_Pos 3U /!< SCB DFSR: VCATCH Position /
kevman	0:38ceb79fef03	826	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
kevman	0:38ceb79fef03	827
kevman	0:38ceb79fef03	828	#define SCB_DFSR_DWTTRAP_Pos 2U /!< SCB DFSR: DWTTRAP Position /
kevman	0:38ceb79fef03	829	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
kevman	0:38ceb79fef03	830
kevman	0:38ceb79fef03	831	#define SCB_DFSR_BKPT_Pos 1U /!< SCB DFSR: BKPT Position /
kevman	0:38ceb79fef03	832	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
kevman	0:38ceb79fef03	833
kevman	0:38ceb79fef03	834	#define SCB_DFSR_HALTED_Pos 0U /!< SCB DFSR: HALTED Position /
kevman	0:38ceb79fef03	835	#define SCB_DFSR_HALTED_Msk (1UL /<< SCB_DFSR_HALTED_Pos/) /!< SCB DFSR: HALTED Mask /
kevman	0:38ceb79fef03	836
kevman	0:38ceb79fef03	837	/* SCB Non-Secure Access Control Register Definitions */
kevman	0:38ceb79fef03	838	#define SCB_NSACR_CP11_Pos 11U /!< SCB NSACR: CP11 Position /
kevman	0:38ceb79fef03	839	#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /!< SCB NSACR: CP11 Mask /
kevman	0:38ceb79fef03	840
kevman	0:38ceb79fef03	841	#define SCB_NSACR_CP10_Pos 10U /!< SCB NSACR: CP10 Position /
kevman	0:38ceb79fef03	842	#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /!< SCB NSACR: CP10 Mask /
kevman	0:38ceb79fef03	843
kevman	0:38ceb79fef03	844	#define SCB_NSACR_CPn_Pos 0U /!< SCB NSACR: CPn Position /
kevman	0:38ceb79fef03	845	#define SCB_NSACR_CPn_Msk (1UL /<< SCB_NSACR_CPn_Pos/) /!< SCB NSACR: CPn Mask /
kevman	0:38ceb79fef03	846
kevman	0:38ceb79fef03	847	/* SCB Cache Level ID Register Definitions */
kevman	0:38ceb79fef03	848	#define SCB_CLIDR_LOUU_Pos 27U /!< SCB CLIDR: LoUU Position /
kevman	0:38ceb79fef03	849	#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /!< SCB CLIDR: LoUU Mask /
kevman	0:38ceb79fef03	850
kevman	0:38ceb79fef03	851	#define SCB_CLIDR_LOC_Pos 24U /!< SCB CLIDR: LoC Position /
kevman	0:38ceb79fef03	852	#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /!< SCB CLIDR: LoC Mask /
kevman	0:38ceb79fef03	853
kevman	0:38ceb79fef03	854	/* SCB Cache Type Register Definitions */
kevman	0:38ceb79fef03	855	#define SCB_CTR_FORMAT_Pos 29U /!< SCB CTR: Format Position /
kevman	0:38ceb79fef03	856	#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /!< SCB CTR: Format Mask /
kevman	0:38ceb79fef03	857
kevman	0:38ceb79fef03	858	#define SCB_CTR_CWG_Pos 24U /!< SCB CTR: CWG Position /
kevman	0:38ceb79fef03	859	#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /!< SCB CTR: CWG Mask /
kevman	0:38ceb79fef03	860
kevman	0:38ceb79fef03	861	#define SCB_CTR_ERG_Pos 20U /!< SCB CTR: ERG Position /
kevman	0:38ceb79fef03	862	#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /!< SCB CTR: ERG Mask /
kevman	0:38ceb79fef03	863
kevman	0:38ceb79fef03	864	#define SCB_CTR_DMINLINE_Pos 16U /!< SCB CTR: DminLine Position /
kevman	0:38ceb79fef03	865	#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /!< SCB CTR: DminLine Mask /
kevman	0:38ceb79fef03	866
kevman	0:38ceb79fef03	867	#define SCB_CTR_IMINLINE_Pos 0U /!< SCB CTR: ImInLine Position /
kevman	0:38ceb79fef03	868	#define SCB_CTR_IMINLINE_Msk (0xFUL /<< SCB_CTR_IMINLINE_Pos/) /!< SCB CTR: ImInLine Mask /
kevman	0:38ceb79fef03	869
kevman	0:38ceb79fef03	870	/* SCB Cache Size ID Register Definitions */
kevman	0:38ceb79fef03	871	#define SCB_CCSIDR_WT_Pos 31U /!< SCB CCSIDR: WT Position /
kevman	0:38ceb79fef03	872	#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /!< SCB CCSIDR: WT Mask /
kevman	0:38ceb79fef03	873
kevman	0:38ceb79fef03	874	#define SCB_CCSIDR_WB_Pos 30U /!< SCB CCSIDR: WB Position /
kevman	0:38ceb79fef03	875	#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /!< SCB CCSIDR: WB Mask /
kevman	0:38ceb79fef03	876
kevman	0:38ceb79fef03	877	#define SCB_CCSIDR_RA_Pos 29U /!< SCB CCSIDR: RA Position /
kevman	0:38ceb79fef03	878	#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /!< SCB CCSIDR: RA Mask /
kevman	0:38ceb79fef03	879
kevman	0:38ceb79fef03	880	#define SCB_CCSIDR_WA_Pos 28U /!< SCB CCSIDR: WA Position /
kevman	0:38ceb79fef03	881	#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /!< SCB CCSIDR: WA Mask /
kevman	0:38ceb79fef03	882
kevman	0:38ceb79fef03	883	#define SCB_CCSIDR_NUMSETS_Pos 13U /!< SCB CCSIDR: NumSets Position /
kevman	0:38ceb79fef03	884	#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /!< SCB CCSIDR: NumSets Mask /
kevman	0:38ceb79fef03	885
kevman	0:38ceb79fef03	886	#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /!< SCB CCSIDR: Associativity Position /
kevman	0:38ceb79fef03	887	#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /!< SCB CCSIDR: Associativity Mask /
kevman	0:38ceb79fef03	888
kevman	0:38ceb79fef03	889	#define SCB_CCSIDR_LINESIZE_Pos 0U /!< SCB CCSIDR: LineSize Position /
kevman	0:38ceb79fef03	890	#define SCB_CCSIDR_LINESIZE_Msk (7UL /<< SCB_CCSIDR_LINESIZE_Pos/) /!< SCB CCSIDR: LineSize Mask /
kevman	0:38ceb79fef03	891
kevman	0:38ceb79fef03	892	/* SCB Cache Size Selection Register Definitions */
kevman	0:38ceb79fef03	893	#define SCB_CSSELR_LEVEL_Pos 1U /!< SCB CSSELR: Level Position /
kevman	0:38ceb79fef03	894	#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /!< SCB CSSELR: Level Mask /
kevman	0:38ceb79fef03	895
kevman	0:38ceb79fef03	896	#define SCB_CSSELR_IND_Pos 0U /!< SCB CSSELR: InD Position /
kevman	0:38ceb79fef03	897	#define SCB_CSSELR_IND_Msk (1UL /<< SCB_CSSELR_IND_Pos/) /!< SCB CSSELR: InD Mask /
kevman	0:38ceb79fef03	898
kevman	0:38ceb79fef03	899	/* SCB Software Triggered Interrupt Register Definitions */
kevman	0:38ceb79fef03	900	#define SCB_STIR_INTID_Pos 0U /!< SCB STIR: INTID Position /
kevman	0:38ceb79fef03	901	#define SCB_STIR_INTID_Msk (0x1FFUL /<< SCB_STIR_INTID_Pos/) /!< SCB STIR: INTID Mask /
kevman	0:38ceb79fef03	902
kevman	0:38ceb79fef03	903	/* SCB D-Cache Invalidate by Set-way Register Definitions */
kevman	0:38ceb79fef03	904	#define SCB_DCISW_WAY_Pos 30U /!< SCB DCISW: Way Position /
kevman	0:38ceb79fef03	905	#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /!< SCB DCISW: Way Mask /
kevman	0:38ceb79fef03	906
kevman	0:38ceb79fef03	907	#define SCB_DCISW_SET_Pos 5U /!< SCB DCISW: Set Position /
kevman	0:38ceb79fef03	908	#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /!< SCB DCISW: Set Mask /
kevman	0:38ceb79fef03	909
kevman	0:38ceb79fef03	910	/* SCB D-Cache Clean by Set-way Register Definitions */
kevman	0:38ceb79fef03	911	#define SCB_DCCSW_WAY_Pos 30U /!< SCB DCCSW: Way Position /
kevman	0:38ceb79fef03	912	#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /!< SCB DCCSW: Way Mask /
kevman	0:38ceb79fef03	913
kevman	0:38ceb79fef03	914	#define SCB_DCCSW_SET_Pos 5U /!< SCB DCCSW: Set Position /
kevman	0:38ceb79fef03	915	#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /!< SCB DCCSW: Set Mask /
kevman	0:38ceb79fef03	916
kevman	0:38ceb79fef03	917	/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
kevman	0:38ceb79fef03	918	#define SCB_DCCISW_WAY_Pos 30U /!< SCB DCCISW: Way Position /
kevman	0:38ceb79fef03	919	#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /!< SCB DCCISW: Way Mask /
kevman	0:38ceb79fef03	920
kevman	0:38ceb79fef03	921	#define SCB_DCCISW_SET_Pos 5U /!< SCB DCCISW: Set Position /
kevman	0:38ceb79fef03	922	#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /!< SCB DCCISW: Set Mask /
kevman	0:38ceb79fef03	923
kevman	0:38ceb79fef03	924	/* Instruction Tightly-Coupled Memory Control Register Definitions */
kevman	0:38ceb79fef03	925	#define SCB_ITCMCR_SZ_Pos 3U /!< SCB ITCMCR: SZ Position /
kevman	0:38ceb79fef03	926	#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /!< SCB ITCMCR: SZ Mask /
kevman	0:38ceb79fef03	927
kevman	0:38ceb79fef03	928	#define SCB_ITCMCR_RETEN_Pos 2U /!< SCB ITCMCR: RETEN Position /
kevman	0:38ceb79fef03	929	#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /!< SCB ITCMCR: RETEN Mask /
kevman	0:38ceb79fef03	930
kevman	0:38ceb79fef03	931	#define SCB_ITCMCR_RMW_Pos 1U /!< SCB ITCMCR: RMW Position /
kevman	0:38ceb79fef03	932	#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /!< SCB ITCMCR: RMW Mask /
kevman	0:38ceb79fef03	933
kevman	0:38ceb79fef03	934	#define SCB_ITCMCR_EN_Pos 0U /!< SCB ITCMCR: EN Position /
kevman	0:38ceb79fef03	935	#define SCB_ITCMCR_EN_Msk (1UL /<< SCB_ITCMCR_EN_Pos/) /!< SCB ITCMCR: EN Mask /
kevman	0:38ceb79fef03	936
kevman	0:38ceb79fef03	937	/* Data Tightly-Coupled Memory Control Register Definitions */
kevman	0:38ceb79fef03	938	#define SCB_DTCMCR_SZ_Pos 3U /!< SCB DTCMCR: SZ Position /
kevman	0:38ceb79fef03	939	#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /!< SCB DTCMCR: SZ Mask /
kevman	0:38ceb79fef03	940
kevman	0:38ceb79fef03	941	#define SCB_DTCMCR_RETEN_Pos 2U /!< SCB DTCMCR: RETEN Position /
kevman	0:38ceb79fef03	942	#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /!< SCB DTCMCR: RETEN Mask /
kevman	0:38ceb79fef03	943
kevman	0:38ceb79fef03	944	#define SCB_DTCMCR_RMW_Pos 1U /!< SCB DTCMCR: RMW Position /
kevman	0:38ceb79fef03	945	#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /!< SCB DTCMCR: RMW Mask /
kevman	0:38ceb79fef03	946
kevman	0:38ceb79fef03	947	#define SCB_DTCMCR_EN_Pos 0U /!< SCB DTCMCR: EN Position /
kevman	0:38ceb79fef03	948	#define SCB_DTCMCR_EN_Msk (1UL /<< SCB_DTCMCR_EN_Pos/) /!< SCB DTCMCR: EN Mask /
kevman	0:38ceb79fef03	949
kevman	0:38ceb79fef03	950	/* AHBP Control Register Definitions */
kevman	0:38ceb79fef03	951	#define SCB_AHBPCR_SZ_Pos 1U /!< SCB AHBPCR: SZ Position /
kevman	0:38ceb79fef03	952	#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /!< SCB AHBPCR: SZ Mask /
kevman	0:38ceb79fef03	953
kevman	0:38ceb79fef03	954	#define SCB_AHBPCR_EN_Pos 0U /!< SCB AHBPCR: EN Position /
kevman	0:38ceb79fef03	955	#define SCB_AHBPCR_EN_Msk (1UL /<< SCB_AHBPCR_EN_Pos/) /!< SCB AHBPCR: EN Mask /
kevman	0:38ceb79fef03	956
kevman	0:38ceb79fef03	957	/* L1 Cache Control Register Definitions */
kevman	0:38ceb79fef03	958	#define SCB_CACR_FORCEWT_Pos 2U /!< SCB CACR: FORCEWT Position /
kevman	0:38ceb79fef03	959	#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /!< SCB CACR: FORCEWT Mask /
kevman	0:38ceb79fef03	960
kevman	0:38ceb79fef03	961	#define SCB_CACR_ECCEN_Pos 1U /!< SCB CACR: ECCEN Position /
kevman	0:38ceb79fef03	962	#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /!< SCB CACR: ECCEN Mask /
kevman	0:38ceb79fef03	963
kevman	0:38ceb79fef03	964	#define SCB_CACR_SIWT_Pos 0U /!< SCB CACR: SIWT Position /
kevman	0:38ceb79fef03	965	#define SCB_CACR_SIWT_Msk (1UL /<< SCB_CACR_SIWT_Pos/) /!< SCB CACR: SIWT Mask /
kevman	0:38ceb79fef03	966
kevman	0:38ceb79fef03	967	/* AHBS Control Register Definitions */
kevman	0:38ceb79fef03	968	#define SCB_AHBSCR_INITCOUNT_Pos 11U /!< SCB AHBSCR: INITCOUNT Position /
kevman	0:38ceb79fef03	969	#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /!< SCB AHBSCR: INITCOUNT Mask /
kevman	0:38ceb79fef03	970
kevman	0:38ceb79fef03	971	#define SCB_AHBSCR_TPRI_Pos 2U /!< SCB AHBSCR: TPRI Position /
kevman	0:38ceb79fef03	972	#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /!< SCB AHBSCR: TPRI Mask /
kevman	0:38ceb79fef03	973
kevman	0:38ceb79fef03	974	#define SCB_AHBSCR_CTL_Pos 0U /!< SCB AHBSCR: CTL Position/
kevman	0:38ceb79fef03	975	#define SCB_AHBSCR_CTL_Msk (3UL /<< SCB_AHBPCR_CTL_Pos/) /!< SCB AHBSCR: CTL Mask /
kevman	0:38ceb79fef03	976
kevman	0:38ceb79fef03	977	/* Auxiliary Bus Fault Status Register Definitions */
kevman	0:38ceb79fef03	978	#define SCB_ABFSR_AXIMTYPE_Pos 8U /!< SCB ABFSR: AXIMTYPE Position/
kevman	0:38ceb79fef03	979	#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /!< SCB ABFSR: AXIMTYPE Mask /
kevman	0:38ceb79fef03	980
kevman	0:38ceb79fef03	981	#define SCB_ABFSR_EPPB_Pos 4U /!< SCB ABFSR: EPPB Position/
kevman	0:38ceb79fef03	982	#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /!< SCB ABFSR: EPPB Mask /
kevman	0:38ceb79fef03	983
kevman	0:38ceb79fef03	984	#define SCB_ABFSR_AXIM_Pos 3U /!< SCB ABFSR: AXIM Position/
kevman	0:38ceb79fef03	985	#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /!< SCB ABFSR: AXIM Mask /
kevman	0:38ceb79fef03	986
kevman	0:38ceb79fef03	987	#define SCB_ABFSR_AHBP_Pos 2U /!< SCB ABFSR: AHBP Position/
kevman	0:38ceb79fef03	988	#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /!< SCB ABFSR: AHBP Mask /
kevman	0:38ceb79fef03	989
kevman	0:38ceb79fef03	990	#define SCB_ABFSR_DTCM_Pos 1U /!< SCB ABFSR: DTCM Position/
kevman	0:38ceb79fef03	991	#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /!< SCB ABFSR: DTCM Mask /
kevman	0:38ceb79fef03	992
kevman	0:38ceb79fef03	993	#define SCB_ABFSR_ITCM_Pos 0U /!< SCB ABFSR: ITCM Position/
kevman	0:38ceb79fef03	994	#define SCB_ABFSR_ITCM_Msk (1UL /<< SCB_ABFSR_ITCM_Pos/) /!< SCB ABFSR: ITCM Mask /
kevman	0:38ceb79fef03	995
kevman	0:38ceb79fef03	996	/@} end of group CMSIS_SCB /
kevman	0:38ceb79fef03	997
kevman	0:38ceb79fef03	998
kevman	0:38ceb79fef03	999	/**
kevman	0:38ceb79fef03	1000	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1001	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
kevman	0:38ceb79fef03	1002	\brief Type definitions for the System Control and ID Register not in the SCB
kevman	0:38ceb79fef03	1003	@{
kevman	0:38ceb79fef03	1004	*/
kevman	0:38ceb79fef03	1005
kevman	0:38ceb79fef03	1006	/**
kevman	0:38ceb79fef03	1007	\brief Structure type to access the System Control and ID Register not in the SCB.
kevman	0:38ceb79fef03	1008	*/
kevman	0:38ceb79fef03	1009	typedef struct
kevman	0:38ceb79fef03	1010	{
kevman	0:38ceb79fef03	1011	uint32_t RESERVED0[1U];
kevman	0:38ceb79fef03	1012	__IM uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
kevman	0:38ceb79fef03	1013	__IOM uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
kevman	0:38ceb79fef03	1014	__IOM uint32_t CPPWR; /!< Offset: 0x00C (R/W) Coprocessor Power Control Register /
kevman	0:38ceb79fef03	1015	} SCnSCB_Type;
kevman	0:38ceb79fef03	1016
kevman	0:38ceb79fef03	1017	/* Interrupt Controller Type Register Definitions */
kevman	0:38ceb79fef03	1018	#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /!< ICTR: INTLINESNUM Position /
kevman	0:38ceb79fef03	1019	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /<< SCnSCB_ICTR_INTLINESNUM_Pos/) /!< ICTR: INTLINESNUM Mask /
kevman	0:38ceb79fef03	1020
kevman	0:38ceb79fef03	1021	/@} end of group CMSIS_SCnotSCB /
kevman	0:38ceb79fef03	1022
kevman	0:38ceb79fef03	1023
kevman	0:38ceb79fef03	1024	/**
kevman	0:38ceb79fef03	1025	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1026	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
kevman	0:38ceb79fef03	1027	\brief Type definitions for the System Timer Registers.
kevman	0:38ceb79fef03	1028	@{
kevman	0:38ceb79fef03	1029	*/
kevman	0:38ceb79fef03	1030
kevman	0:38ceb79fef03	1031	/**
kevman	0:38ceb79fef03	1032	\brief Structure type to access the System Timer (SysTick).
kevman	0:38ceb79fef03	1033	*/
kevman	0:38ceb79fef03	1034	typedef struct
kevman	0:38ceb79fef03	1035	{
kevman	0:38ceb79fef03	1036	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
kevman	0:38ceb79fef03	1037	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
kevman	0:38ceb79fef03	1038	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
kevman	0:38ceb79fef03	1039	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
kevman	0:38ceb79fef03	1040	} SysTick_Type;
kevman	0:38ceb79fef03	1041
kevman	0:38ceb79fef03	1042	/* SysTick Control / Status Register Definitions */
kevman	0:38ceb79fef03	1043	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
kevman	0:38ceb79fef03	1044	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
kevman	0:38ceb79fef03	1045
kevman	0:38ceb79fef03	1046	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
kevman	0:38ceb79fef03	1047	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
kevman	0:38ceb79fef03	1048
kevman	0:38ceb79fef03	1049	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
kevman	0:38ceb79fef03	1050	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
kevman	0:38ceb79fef03	1051
kevman	0:38ceb79fef03	1052	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
kevman	0:38ceb79fef03	1053	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
kevman	0:38ceb79fef03	1054
kevman	0:38ceb79fef03	1055	/* SysTick Reload Register Definitions */
kevman	0:38ceb79fef03	1056	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
kevman	0:38ceb79fef03	1057	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
kevman	0:38ceb79fef03	1058
kevman	0:38ceb79fef03	1059	/* SysTick Current Register Definitions */
kevman	0:38ceb79fef03	1060	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
kevman	0:38ceb79fef03	1061	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
kevman	0:38ceb79fef03	1062
kevman	0:38ceb79fef03	1063	/* SysTick Calibration Register Definitions */
kevman	0:38ceb79fef03	1064	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
kevman	0:38ceb79fef03	1065	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
kevman	0:38ceb79fef03	1066
kevman	0:38ceb79fef03	1067	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
kevman	0:38ceb79fef03	1068	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
kevman	0:38ceb79fef03	1069
kevman	0:38ceb79fef03	1070	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
kevman	0:38ceb79fef03	1071	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
kevman	0:38ceb79fef03	1072
kevman	0:38ceb79fef03	1073	/@} end of group CMSIS_SysTick /
kevman	0:38ceb79fef03	1074
kevman	0:38ceb79fef03	1075
kevman	0:38ceb79fef03	1076	/**
kevman	0:38ceb79fef03	1077	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1078	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
kevman	0:38ceb79fef03	1079	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
kevman	0:38ceb79fef03	1080	@{
kevman	0:38ceb79fef03	1081	*/
kevman	0:38ceb79fef03	1082
kevman	0:38ceb79fef03	1083	/**
kevman	0:38ceb79fef03	1084	\brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
kevman	0:38ceb79fef03	1085	*/
kevman	0:38ceb79fef03	1086	typedef struct
kevman	0:38ceb79fef03	1087	{
kevman	0:38ceb79fef03	1088	__OM union
kevman	0:38ceb79fef03	1089	{
kevman	0:38ceb79fef03	1090	__OM uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
kevman	0:38ceb79fef03	1091	__OM uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
kevman	0:38ceb79fef03	1092	__OM uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
kevman	0:38ceb79fef03	1093	} PORT [32U]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
kevman	0:38ceb79fef03	1094	uint32_t RESERVED0[864U];
kevman	0:38ceb79fef03	1095	__IOM uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
kevman	0:38ceb79fef03	1096	uint32_t RESERVED1[15U];
kevman	0:38ceb79fef03	1097	__IOM uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
kevman	0:38ceb79fef03	1098	uint32_t RESERVED2[15U];
kevman	0:38ceb79fef03	1099	__IOM uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
kevman	0:38ceb79fef03	1100	uint32_t RESERVED3[29U];
kevman	0:38ceb79fef03	1101	__OM uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
kevman	0:38ceb79fef03	1102	__IM uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
kevman	0:38ceb79fef03	1103	__IOM uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
kevman	0:38ceb79fef03	1104	uint32_t RESERVED4[43U];
kevman	0:38ceb79fef03	1105	__OM uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
kevman	0:38ceb79fef03	1106	__IM uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
kevman	0:38ceb79fef03	1107	uint32_t RESERVED5[1U];
kevman	0:38ceb79fef03	1108	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) ITM Device Architecture Register /
kevman	0:38ceb79fef03	1109	uint32_t RESERVED6[4U];
kevman	0:38ceb79fef03	1110	__IM uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
kevman	0:38ceb79fef03	1111	__IM uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
kevman	0:38ceb79fef03	1112	__IM uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
kevman	0:38ceb79fef03	1113	__IM uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
kevman	0:38ceb79fef03	1114	__IM uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
kevman	0:38ceb79fef03	1115	__IM uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
kevman	0:38ceb79fef03	1116	__IM uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
kevman	0:38ceb79fef03	1117	__IM uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
kevman	0:38ceb79fef03	1118	__IM uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
kevman	0:38ceb79fef03	1119	__IM uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
kevman	0:38ceb79fef03	1120	__IM uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
kevman	0:38ceb79fef03	1121	__IM uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
kevman	0:38ceb79fef03	1122	} ITM_Type;
kevman	0:38ceb79fef03	1123
kevman	0:38ceb79fef03	1124	/* ITM Stimulus Port Register Definitions */
kevman	0:38ceb79fef03	1125	#define ITM_STIM_DISABLED_Pos 1U /!< ITM STIM: DISABLED Position /
kevman	0:38ceb79fef03	1126	#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /!< ITM STIM: DISABLED Mask /
kevman	0:38ceb79fef03	1127
kevman	0:38ceb79fef03	1128	#define ITM_STIM_FIFOREADY_Pos 0U /!< ITM STIM: FIFOREADY Position /
kevman	0:38ceb79fef03	1129	#define ITM_STIM_FIFOREADY_Msk (0x1UL /<< ITM_STIM_FIFOREADY_Pos/) /!< ITM STIM: FIFOREADY Mask /
kevman	0:38ceb79fef03	1130
kevman	0:38ceb79fef03	1131	/* ITM Trace Privilege Register Definitions */
kevman	0:38ceb79fef03	1132	#define ITM_TPR_PRIVMASK_Pos 0U /!< ITM TPR: PRIVMASK Position /
kevman	0:38ceb79fef03	1133	#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /<< ITM_TPR_PRIVMASK_Pos/) /!< ITM TPR: PRIVMASK Mask /
kevman	0:38ceb79fef03	1134
kevman	0:38ceb79fef03	1135	/* ITM Trace Control Register Definitions */
kevman	0:38ceb79fef03	1136	#define ITM_TCR_BUSY_Pos 23U /!< ITM TCR: BUSY Position /
kevman	0:38ceb79fef03	1137	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
kevman	0:38ceb79fef03	1138
kevman	0:38ceb79fef03	1139	#define ITM_TCR_TRACEBUSID_Pos 16U /!< ITM TCR: ATBID Position /
kevman	0:38ceb79fef03	1140	#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /!< ITM TCR: ATBID Mask /
kevman	0:38ceb79fef03	1141
kevman	0:38ceb79fef03	1142	#define ITM_TCR_GTSFREQ_Pos 10U /!< ITM TCR: Global timestamp frequency Position /
kevman	0:38ceb79fef03	1143	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
kevman	0:38ceb79fef03	1144
kevman	0:38ceb79fef03	1145	#define ITM_TCR_TSPRESCALE_Pos 8U /!< ITM TCR: TSPRESCALE Position /
kevman	0:38ceb79fef03	1146	#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /!< ITM TCR: TSPRESCALE Mask /
kevman	0:38ceb79fef03	1147
kevman	0:38ceb79fef03	1148	#define ITM_TCR_STALLENA_Pos 5U /!< ITM TCR: STALLENA Position /
kevman	0:38ceb79fef03	1149	#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /!< ITM TCR: STALLENA Mask /
kevman	0:38ceb79fef03	1150
kevman	0:38ceb79fef03	1151	#define ITM_TCR_SWOENA_Pos 4U /!< ITM TCR: SWOENA Position /
kevman	0:38ceb79fef03	1152	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
kevman	0:38ceb79fef03	1153
kevman	0:38ceb79fef03	1154	#define ITM_TCR_DWTENA_Pos 3U /!< ITM TCR: DWTENA Position /
kevman	0:38ceb79fef03	1155	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
kevman	0:38ceb79fef03	1156
kevman	0:38ceb79fef03	1157	#define ITM_TCR_SYNCENA_Pos 2U /!< ITM TCR: SYNCENA Position /
kevman	0:38ceb79fef03	1158	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
kevman	0:38ceb79fef03	1159
kevman	0:38ceb79fef03	1160	#define ITM_TCR_TSENA_Pos 1U /!< ITM TCR: TSENA Position /
kevman	0:38ceb79fef03	1161	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
kevman	0:38ceb79fef03	1162
kevman	0:38ceb79fef03	1163	#define ITM_TCR_ITMENA_Pos 0U /!< ITM TCR: ITM Enable bit Position /
kevman	0:38ceb79fef03	1164	#define ITM_TCR_ITMENA_Msk (1UL /<< ITM_TCR_ITMENA_Pos/) /!< ITM TCR: ITM Enable bit Mask /
kevman	0:38ceb79fef03	1165
kevman	0:38ceb79fef03	1166	/* ITM Integration Write Register Definitions */
kevman	0:38ceb79fef03	1167	#define ITM_IWR_ATVALIDM_Pos 0U /!< ITM IWR: ATVALIDM Position /
kevman	0:38ceb79fef03	1168	#define ITM_IWR_ATVALIDM_Msk (1UL /<< ITM_IWR_ATVALIDM_Pos/) /!< ITM IWR: ATVALIDM Mask /
kevman	0:38ceb79fef03	1169
kevman	0:38ceb79fef03	1170	/* ITM Integration Read Register Definitions */
kevman	0:38ceb79fef03	1171	#define ITM_IRR_ATREADYM_Pos 0U /!< ITM IRR: ATREADYM Position /
kevman	0:38ceb79fef03	1172	#define ITM_IRR_ATREADYM_Msk (1UL /<< ITM_IRR_ATREADYM_Pos/) /!< ITM IRR: ATREADYM Mask /
kevman	0:38ceb79fef03	1173
kevman	0:38ceb79fef03	1174	/* ITM Integration Mode Control Register Definitions */
kevman	0:38ceb79fef03	1175	#define ITM_IMCR_INTEGRATION_Pos 0U /!< ITM IMCR: INTEGRATION Position /
kevman	0:38ceb79fef03	1176	#define ITM_IMCR_INTEGRATION_Msk (1UL /<< ITM_IMCR_INTEGRATION_Pos/) /!< ITM IMCR: INTEGRATION Mask /
kevman	0:38ceb79fef03	1177
kevman	0:38ceb79fef03	1178	/* ITM Lock Status Register Definitions */
kevman	0:38ceb79fef03	1179	#define ITM_LSR_ByteAcc_Pos 2U /!< ITM LSR: ByteAcc Position /
kevman	0:38ceb79fef03	1180	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
kevman	0:38ceb79fef03	1181
kevman	0:38ceb79fef03	1182	#define ITM_LSR_Access_Pos 1U /!< ITM LSR: Access Position /
kevman	0:38ceb79fef03	1183	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
kevman	0:38ceb79fef03	1184
kevman	0:38ceb79fef03	1185	#define ITM_LSR_Present_Pos 0U /!< ITM LSR: Present Position /
kevman	0:38ceb79fef03	1186	#define ITM_LSR_Present_Msk (1UL /<< ITM_LSR_Present_Pos/) /!< ITM LSR: Present Mask /
kevman	0:38ceb79fef03	1187
kevman	0:38ceb79fef03	1188	/@}/ /* end of group CMSIS_ITM */
kevman	0:38ceb79fef03	1189
kevman	0:38ceb79fef03	1190
kevman	0:38ceb79fef03	1191	/**
kevman	0:38ceb79fef03	1192	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1193	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
kevman	0:38ceb79fef03	1194	\brief Type definitions for the Data Watchpoint and Trace (DWT)
kevman	0:38ceb79fef03	1195	@{
kevman	0:38ceb79fef03	1196	*/
kevman	0:38ceb79fef03	1197
kevman	0:38ceb79fef03	1198	/**
kevman	0:38ceb79fef03	1199	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
kevman	0:38ceb79fef03	1200	*/
kevman	0:38ceb79fef03	1201	typedef struct
kevman	0:38ceb79fef03	1202	{
kevman	0:38ceb79fef03	1203	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
kevman	0:38ceb79fef03	1204	__IOM uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
kevman	0:38ceb79fef03	1205	__IOM uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
kevman	0:38ceb79fef03	1206	__IOM uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
kevman	0:38ceb79fef03	1207	__IOM uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
kevman	0:38ceb79fef03	1208	__IOM uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
kevman	0:38ceb79fef03	1209	__IOM uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
kevman	0:38ceb79fef03	1210	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
kevman	0:38ceb79fef03	1211	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
kevman	0:38ceb79fef03	1212	uint32_t RESERVED1[1U];
kevman	0:38ceb79fef03	1213	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
kevman	0:38ceb79fef03	1214	uint32_t RESERVED2[1U];
kevman	0:38ceb79fef03	1215	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
kevman	0:38ceb79fef03	1216	uint32_t RESERVED3[1U];
kevman	0:38ceb79fef03	1217	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
kevman	0:38ceb79fef03	1218	uint32_t RESERVED4[1U];
kevman	0:38ceb79fef03	1219	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
kevman	0:38ceb79fef03	1220	uint32_t RESERVED5[1U];
kevman	0:38ceb79fef03	1221	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
kevman	0:38ceb79fef03	1222	uint32_t RESERVED6[1U];
kevman	0:38ceb79fef03	1223	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
kevman	0:38ceb79fef03	1224	uint32_t RESERVED7[1U];
kevman	0:38ceb79fef03	1225	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
kevman	0:38ceb79fef03	1226	uint32_t RESERVED8[1U];
kevman	0:38ceb79fef03	1227	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
kevman	0:38ceb79fef03	1228	uint32_t RESERVED9[1U];
kevman	0:38ceb79fef03	1229	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
kevman	0:38ceb79fef03	1230	uint32_t RESERVED10[1U];
kevman	0:38ceb79fef03	1231	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
kevman	0:38ceb79fef03	1232	uint32_t RESERVED11[1U];
kevman	0:38ceb79fef03	1233	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
kevman	0:38ceb79fef03	1234	uint32_t RESERVED12[1U];
kevman	0:38ceb79fef03	1235	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
kevman	0:38ceb79fef03	1236	uint32_t RESERVED13[1U];
kevman	0:38ceb79fef03	1237	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
kevman	0:38ceb79fef03	1238	uint32_t RESERVED14[1U];
kevman	0:38ceb79fef03	1239	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
kevman	0:38ceb79fef03	1240	uint32_t RESERVED15[1U];
kevman	0:38ceb79fef03	1241	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
kevman	0:38ceb79fef03	1242	uint32_t RESERVED16[1U];
kevman	0:38ceb79fef03	1243	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
kevman	0:38ceb79fef03	1244	uint32_t RESERVED17[1U];
kevman	0:38ceb79fef03	1245	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
kevman	0:38ceb79fef03	1246	uint32_t RESERVED18[1U];
kevman	0:38ceb79fef03	1247	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
kevman	0:38ceb79fef03	1248	uint32_t RESERVED19[1U];
kevman	0:38ceb79fef03	1249	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
kevman	0:38ceb79fef03	1250	uint32_t RESERVED20[1U];
kevman	0:38ceb79fef03	1251	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
kevman	0:38ceb79fef03	1252	uint32_t RESERVED21[1U];
kevman	0:38ceb79fef03	1253	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
kevman	0:38ceb79fef03	1254	uint32_t RESERVED22[1U];
kevman	0:38ceb79fef03	1255	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
kevman	0:38ceb79fef03	1256	uint32_t RESERVED23[1U];
kevman	0:38ceb79fef03	1257	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
kevman	0:38ceb79fef03	1258	uint32_t RESERVED24[1U];
kevman	0:38ceb79fef03	1259	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
kevman	0:38ceb79fef03	1260	uint32_t RESERVED25[1U];
kevman	0:38ceb79fef03	1261	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
kevman	0:38ceb79fef03	1262	uint32_t RESERVED26[1U];
kevman	0:38ceb79fef03	1263	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
kevman	0:38ceb79fef03	1264	uint32_t RESERVED27[1U];
kevman	0:38ceb79fef03	1265	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
kevman	0:38ceb79fef03	1266	uint32_t RESERVED28[1U];
kevman	0:38ceb79fef03	1267	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
kevman	0:38ceb79fef03	1268	uint32_t RESERVED29[1U];
kevman	0:38ceb79fef03	1269	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
kevman	0:38ceb79fef03	1270	uint32_t RESERVED30[1U];
kevman	0:38ceb79fef03	1271	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
kevman	0:38ceb79fef03	1272	uint32_t RESERVED31[1U];
kevman	0:38ceb79fef03	1273	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
kevman	0:38ceb79fef03	1274	uint32_t RESERVED32[934U];
kevman	0:38ceb79fef03	1275	__IM uint32_t LSR; /!< Offset: 0xFB4 (R ) Lock Status Register /
kevman	0:38ceb79fef03	1276	uint32_t RESERVED33[1U];
kevman	0:38ceb79fef03	1277	__IM uint32_t DEVARCH; /!< Offset: 0xFBC (R/ ) Device Architecture Register /
kevman	0:38ceb79fef03	1278	} DWT_Type;
kevman	0:38ceb79fef03	1279
kevman	0:38ceb79fef03	1280	/* DWT Control Register Definitions */
kevman	0:38ceb79fef03	1281	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
kevman	0:38ceb79fef03	1282	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
kevman	0:38ceb79fef03	1283
kevman	0:38ceb79fef03	1284	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
kevman	0:38ceb79fef03	1285	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
kevman	0:38ceb79fef03	1286
kevman	0:38ceb79fef03	1287	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
kevman	0:38ceb79fef03	1288	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
kevman	0:38ceb79fef03	1289
kevman	0:38ceb79fef03	1290	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
kevman	0:38ceb79fef03	1291	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
kevman	0:38ceb79fef03	1292
kevman	0:38ceb79fef03	1293	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
kevman	0:38ceb79fef03	1294	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
kevman	0:38ceb79fef03	1295
kevman	0:38ceb79fef03	1296	#define DWT_CTRL_CYCDISS_Pos 23U /!< DWT CTRL: CYCDISS Position /
kevman	0:38ceb79fef03	1297	#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /!< DWT CTRL: CYCDISS Mask /
kevman	0:38ceb79fef03	1298
kevman	0:38ceb79fef03	1299	#define DWT_CTRL_CYCEVTENA_Pos 22U /!< DWT CTRL: CYCEVTENA Position /
kevman	0:38ceb79fef03	1300	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
kevman	0:38ceb79fef03	1301
kevman	0:38ceb79fef03	1302	#define DWT_CTRL_FOLDEVTENA_Pos 21U /!< DWT CTRL: FOLDEVTENA Position /
kevman	0:38ceb79fef03	1303	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
kevman	0:38ceb79fef03	1304
kevman	0:38ceb79fef03	1305	#define DWT_CTRL_LSUEVTENA_Pos 20U /!< DWT CTRL: LSUEVTENA Position /
kevman	0:38ceb79fef03	1306	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
kevman	0:38ceb79fef03	1307
kevman	0:38ceb79fef03	1308	#define DWT_CTRL_SLEEPEVTENA_Pos 19U /!< DWT CTRL: SLEEPEVTENA Position /
kevman	0:38ceb79fef03	1309	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
kevman	0:38ceb79fef03	1310
kevman	0:38ceb79fef03	1311	#define DWT_CTRL_EXCEVTENA_Pos 18U /!< DWT CTRL: EXCEVTENA Position /
kevman	0:38ceb79fef03	1312	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
kevman	0:38ceb79fef03	1313
kevman	0:38ceb79fef03	1314	#define DWT_CTRL_CPIEVTENA_Pos 17U /!< DWT CTRL: CPIEVTENA Position /
kevman	0:38ceb79fef03	1315	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
kevman	0:38ceb79fef03	1316
kevman	0:38ceb79fef03	1317	#define DWT_CTRL_EXCTRCENA_Pos 16U /!< DWT CTRL: EXCTRCENA Position /
kevman	0:38ceb79fef03	1318	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
kevman	0:38ceb79fef03	1319
kevman	0:38ceb79fef03	1320	#define DWT_CTRL_PCSAMPLENA_Pos 12U /!< DWT CTRL: PCSAMPLENA Position /
kevman	0:38ceb79fef03	1321	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
kevman	0:38ceb79fef03	1322
kevman	0:38ceb79fef03	1323	#define DWT_CTRL_SYNCTAP_Pos 10U /!< DWT CTRL: SYNCTAP Position /
kevman	0:38ceb79fef03	1324	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
kevman	0:38ceb79fef03	1325
kevman	0:38ceb79fef03	1326	#define DWT_CTRL_CYCTAP_Pos 9U /!< DWT CTRL: CYCTAP Position /
kevman	0:38ceb79fef03	1327	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
kevman	0:38ceb79fef03	1328
kevman	0:38ceb79fef03	1329	#define DWT_CTRL_POSTINIT_Pos 5U /!< DWT CTRL: POSTINIT Position /
kevman	0:38ceb79fef03	1330	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
kevman	0:38ceb79fef03	1331
kevman	0:38ceb79fef03	1332	#define DWT_CTRL_POSTPRESET_Pos 1U /!< DWT CTRL: POSTPRESET Position /
kevman	0:38ceb79fef03	1333	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
kevman	0:38ceb79fef03	1334
kevman	0:38ceb79fef03	1335	#define DWT_CTRL_CYCCNTENA_Pos 0U /!< DWT CTRL: CYCCNTENA Position /
kevman	0:38ceb79fef03	1336	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /<< DWT_CTRL_CYCCNTENA_Pos/) /!< DWT CTRL: CYCCNTENA Mask /
kevman	0:38ceb79fef03	1337
kevman	0:38ceb79fef03	1338	/* DWT CPI Count Register Definitions */
kevman	0:38ceb79fef03	1339	#define DWT_CPICNT_CPICNT_Pos 0U /!< DWT CPICNT: CPICNT Position /
kevman	0:38ceb79fef03	1340	#define DWT_CPICNT_CPICNT_Msk (0xFFUL /<< DWT_CPICNT_CPICNT_Pos/) /!< DWT CPICNT: CPICNT Mask /
kevman	0:38ceb79fef03	1341
kevman	0:38ceb79fef03	1342	/* DWT Exception Overhead Count Register Definitions */
kevman	0:38ceb79fef03	1343	#define DWT_EXCCNT_EXCCNT_Pos 0U /!< DWT EXCCNT: EXCCNT Position /
kevman	0:38ceb79fef03	1344	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /<< DWT_EXCCNT_EXCCNT_Pos/) /!< DWT EXCCNT: EXCCNT Mask /
kevman	0:38ceb79fef03	1345
kevman	0:38ceb79fef03	1346	/* DWT Sleep Count Register Definitions */
kevman	0:38ceb79fef03	1347	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /!< DWT SLEEPCNT: SLEEPCNT Position /
kevman	0:38ceb79fef03	1348	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /<< DWT_SLEEPCNT_SLEEPCNT_Pos/) /!< DWT SLEEPCNT: SLEEPCNT Mask /
kevman	0:38ceb79fef03	1349
kevman	0:38ceb79fef03	1350	/* DWT LSU Count Register Definitions */
kevman	0:38ceb79fef03	1351	#define DWT_LSUCNT_LSUCNT_Pos 0U /!< DWT LSUCNT: LSUCNT Position /
kevman	0:38ceb79fef03	1352	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /<< DWT_LSUCNT_LSUCNT_Pos/) /!< DWT LSUCNT: LSUCNT Mask /
kevman	0:38ceb79fef03	1353
kevman	0:38ceb79fef03	1354	/* DWT Folded-instruction Count Register Definitions */
kevman	0:38ceb79fef03	1355	#define DWT_FOLDCNT_FOLDCNT_Pos 0U /!< DWT FOLDCNT: FOLDCNT Position /
kevman	0:38ceb79fef03	1356	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /<< DWT_FOLDCNT_FOLDCNT_Pos/) /!< DWT FOLDCNT: FOLDCNT Mask /
kevman	0:38ceb79fef03	1357
kevman	0:38ceb79fef03	1358	/* DWT Comparator Function Register Definitions */
kevman	0:38ceb79fef03	1359	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
kevman	0:38ceb79fef03	1360	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
kevman	0:38ceb79fef03	1361
kevman	0:38ceb79fef03	1362	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
kevman	0:38ceb79fef03	1363	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
kevman	0:38ceb79fef03	1364
kevman	0:38ceb79fef03	1365	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
kevman	0:38ceb79fef03	1366	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
kevman	0:38ceb79fef03	1367
kevman	0:38ceb79fef03	1368	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
kevman	0:38ceb79fef03	1369	#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
kevman	0:38ceb79fef03	1370
kevman	0:38ceb79fef03	1371	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
kevman	0:38ceb79fef03	1372	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
kevman	0:38ceb79fef03	1373
kevman	0:38ceb79fef03	1374	/@}/ /* end of group CMSIS_DWT */
kevman	0:38ceb79fef03	1375
kevman	0:38ceb79fef03	1376
kevman	0:38ceb79fef03	1377	/**
kevman	0:38ceb79fef03	1378	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1379	\defgroup CMSIS_TPI Trace Port Interface (TPI)
kevman	0:38ceb79fef03	1380	\brief Type definitions for the Trace Port Interface (TPI)
kevman	0:38ceb79fef03	1381	@{
kevman	0:38ceb79fef03	1382	*/
kevman	0:38ceb79fef03	1383
kevman	0:38ceb79fef03	1384	/**
kevman	0:38ceb79fef03	1385	\brief Structure type to access the Trace Port Interface Register (TPI).
kevman	0:38ceb79fef03	1386	*/
kevman	0:38ceb79fef03	1387	typedef struct
kevman	0:38ceb79fef03	1388	{
kevman	0:38ceb79fef03	1389	__IM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
kevman	0:38ceb79fef03	1390	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
kevman	0:38ceb79fef03	1391	uint32_t RESERVED0[2U];
kevman	0:38ceb79fef03	1392	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
kevman	0:38ceb79fef03	1393	uint32_t RESERVED1[55U];
kevman	0:38ceb79fef03	1394	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
kevman	0:38ceb79fef03	1395	uint32_t RESERVED2[131U];
kevman	0:38ceb79fef03	1396	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
kevman	0:38ceb79fef03	1397	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
kevman	0:38ceb79fef03	1398	__IOM uint32_t PSCR; /!< Offset: 0x308 (R/W) Periodic Synchronization Control Register /
kevman	0:38ceb79fef03	1399	uint32_t RESERVED3[759U];
kevman	0:38ceb79fef03	1400	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER Register /
kevman	0:38ceb79fef03	1401	__IM uint32_t ITFTTD0; /!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register /
kevman	0:38ceb79fef03	1402	__IOM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 /
kevman	0:38ceb79fef03	1403	uint32_t RESERVED4[1U];
kevman	0:38ceb79fef03	1404	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 /
kevman	0:38ceb79fef03	1405	__IM uint32_t ITFTTD1; /!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register /
kevman	0:38ceb79fef03	1406	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
kevman	0:38ceb79fef03	1407	uint32_t RESERVED5[39U];
kevman	0:38ceb79fef03	1408	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
kevman	0:38ceb79fef03	1409	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
kevman	0:38ceb79fef03	1410	uint32_t RESERVED7[8U];
kevman	0:38ceb79fef03	1411	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) Device Configuration Register /
kevman	0:38ceb79fef03	1412	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) Device Type Identifier Register /
kevman	0:38ceb79fef03	1413	} TPI_Type;
kevman	0:38ceb79fef03	1414
kevman	0:38ceb79fef03	1415	/* TPI Asynchronous Clock Prescaler Register Definitions */
kevman	0:38ceb79fef03	1416	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
kevman	0:38ceb79fef03	1417	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
kevman	0:38ceb79fef03	1418
kevman	0:38ceb79fef03	1419	/* TPI Selected Pin Protocol Register Definitions */
kevman	0:38ceb79fef03	1420	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
kevman	0:38ceb79fef03	1421	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
kevman	0:38ceb79fef03	1422
kevman	0:38ceb79fef03	1423	/* TPI Formatter and Flush Status Register Definitions */
kevman	0:38ceb79fef03	1424	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
kevman	0:38ceb79fef03	1425	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
kevman	0:38ceb79fef03	1426
kevman	0:38ceb79fef03	1427	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
kevman	0:38ceb79fef03	1428	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
kevman	0:38ceb79fef03	1429
kevman	0:38ceb79fef03	1430	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
kevman	0:38ceb79fef03	1431	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
kevman	0:38ceb79fef03	1432
kevman	0:38ceb79fef03	1433	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
kevman	0:38ceb79fef03	1434	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
kevman	0:38ceb79fef03	1435
kevman	0:38ceb79fef03	1436	/* TPI Formatter and Flush Control Register Definitions */
kevman	0:38ceb79fef03	1437	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
kevman	0:38ceb79fef03	1438	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
kevman	0:38ceb79fef03	1439
kevman	0:38ceb79fef03	1440	#define TPI_FFCR_FOnMan_Pos 6U /!< TPI FFCR: FOnMan Position /
kevman	0:38ceb79fef03	1441	#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /!< TPI FFCR: FOnMan Mask /
kevman	0:38ceb79fef03	1442
kevman	0:38ceb79fef03	1443	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
kevman	0:38ceb79fef03	1444	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
kevman	0:38ceb79fef03	1445
kevman	0:38ceb79fef03	1446	/* TPI TRIGGER Register Definitions */
kevman	0:38ceb79fef03	1447	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
kevman	0:38ceb79fef03	1448	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
kevman	0:38ceb79fef03	1449
kevman	0:38ceb79fef03	1450	/* TPI Integration Test FIFO Test Data 0 Register Definitions */
kevman	0:38ceb79fef03	1451	#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition /
kevman	0:38ceb79fef03	1452	#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask /
kevman	0:38ceb79fef03	1453
kevman	0:38ceb79fef03	1454	#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /!< TPI ITFTTD0: ATB Interface 2 byte count Position /
kevman	0:38ceb79fef03	1455	#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /!< TPI ITFTTD0: ATB Interface 2 byte count Mask /
kevman	0:38ceb79fef03	1456
kevman	0:38ceb79fef03	1457	#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /!< TPI ITFTTD0: ATB Interface 1 ATVALID Position /
kevman	0:38ceb79fef03	1458	#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask /
kevman	0:38ceb79fef03	1459
kevman	0:38ceb79fef03	1460	#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /!< TPI ITFTTD0: ATB Interface 1 byte count Position /
kevman	0:38ceb79fef03	1461	#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /!< TPI ITFTTD0: ATB Interface 1 byte countt Mask /
kevman	0:38ceb79fef03	1462
kevman	0:38ceb79fef03	1463	#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /!< TPI ITFTTD0: ATB Interface 1 data2 Position /
kevman	0:38ceb79fef03	1464	#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /!< TPI ITFTTD0: ATB Interface 1 data2 Mask /
kevman	0:38ceb79fef03	1465
kevman	0:38ceb79fef03	1466	#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /!< TPI ITFTTD0: ATB Interface 1 data1 Position /
kevman	0:38ceb79fef03	1467	#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /!< TPI ITFTTD0: ATB Interface 1 data1 Mask /
kevman	0:38ceb79fef03	1468
kevman	0:38ceb79fef03	1469	#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /!< TPI ITFTTD0: ATB Interface 1 data0 Position /
kevman	0:38ceb79fef03	1470	#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/) /!< TPI ITFTTD0: ATB Interface 1 data0 Mask /
kevman	0:38ceb79fef03	1471
kevman	0:38ceb79fef03	1472	/* TPI Integration Test ATB Control Register 2 Register Definitions */
kevman	0:38ceb79fef03	1473	#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /!< TPI ITATBCTR2: AFVALID2S Position /
kevman	0:38ceb79fef03	1474	#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /!< TPI ITATBCTR2: AFVALID2SS Mask /
kevman	0:38ceb79fef03	1475
kevman	0:38ceb79fef03	1476	#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /!< TPI ITATBCTR2: AFVALID1S Position /
kevman	0:38ceb79fef03	1477	#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /!< TPI ITATBCTR2: AFVALID1SS Mask /
kevman	0:38ceb79fef03	1478
kevman	0:38ceb79fef03	1479	#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /!< TPI ITATBCTR2: ATREADY2S Position /
kevman	0:38ceb79fef03	1480	#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/) /!< TPI ITATBCTR2: ATREADY2S Mask /
kevman	0:38ceb79fef03	1481
kevman	0:38ceb79fef03	1482	#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /!< TPI ITATBCTR2: ATREADY1S Position /
kevman	0:38ceb79fef03	1483	#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/) /!< TPI ITATBCTR2: ATREADY1S Mask /
kevman	0:38ceb79fef03	1484
kevman	0:38ceb79fef03	1485	/* TPI Integration Test FIFO Test Data 1 Register Definitions */
kevman	0:38ceb79fef03	1486	#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /!< TPI ITFTTD1: ATB Interface 2 ATVALID Position /
kevman	0:38ceb79fef03	1487	#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask /
kevman	0:38ceb79fef03	1488
kevman	0:38ceb79fef03	1489	#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /!< TPI ITFTTD1: ATB Interface 2 byte count Position /
kevman	0:38ceb79fef03	1490	#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /!< TPI ITFTTD1: ATB Interface 2 byte count Mask /
kevman	0:38ceb79fef03	1491
kevman	0:38ceb79fef03	1492	#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /!< TPI ITFTTD1: ATB Interface 1 ATVALID Position /
kevman	0:38ceb79fef03	1493	#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask /
kevman	0:38ceb79fef03	1494
kevman	0:38ceb79fef03	1495	#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /!< TPI ITFTTD1: ATB Interface 1 byte count Position /
kevman	0:38ceb79fef03	1496	#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /!< TPI ITFTTD1: ATB Interface 1 byte countt Mask /
kevman	0:38ceb79fef03	1497
kevman	0:38ceb79fef03	1498	#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /!< TPI ITFTTD1: ATB Interface 2 data2 Position /
kevman	0:38ceb79fef03	1499	#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /!< TPI ITFTTD1: ATB Interface 2 data2 Mask /
kevman	0:38ceb79fef03	1500
kevman	0:38ceb79fef03	1501	#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /!< TPI ITFTTD1: ATB Interface 2 data1 Position /
kevman	0:38ceb79fef03	1502	#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /!< TPI ITFTTD1: ATB Interface 2 data1 Mask /
kevman	0:38ceb79fef03	1503
kevman	0:38ceb79fef03	1504	#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /!< TPI ITFTTD1: ATB Interface 2 data0 Position /
kevman	0:38ceb79fef03	1505	#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/) /!< TPI ITFTTD1: ATB Interface 2 data0 Mask /
kevman	0:38ceb79fef03	1506
kevman	0:38ceb79fef03	1507	/* TPI Integration Test ATB Control Register 0 Definitions */
kevman	0:38ceb79fef03	1508	#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /!< TPI ITATBCTR0: AFVALID2S Position /
kevman	0:38ceb79fef03	1509	#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /!< TPI ITATBCTR0: AFVALID2SS Mask /
kevman	0:38ceb79fef03	1510
kevman	0:38ceb79fef03	1511	#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /!< TPI ITATBCTR0: AFVALID1S Position /
kevman	0:38ceb79fef03	1512	#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /!< TPI ITATBCTR0: AFVALID1SS Mask /
kevman	0:38ceb79fef03	1513
kevman	0:38ceb79fef03	1514	#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /!< TPI ITATBCTR0: ATREADY2S Position /
kevman	0:38ceb79fef03	1515	#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/) /!< TPI ITATBCTR0: ATREADY2S Mask /
kevman	0:38ceb79fef03	1516
kevman	0:38ceb79fef03	1517	#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /!< TPI ITATBCTR0: ATREADY1S Position /
kevman	0:38ceb79fef03	1518	#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/) /!< TPI ITATBCTR0: ATREADY1S Mask /
kevman	0:38ceb79fef03	1519
kevman	0:38ceb79fef03	1520	/* TPI Integration Mode Control Register Definitions */
kevman	0:38ceb79fef03	1521	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
kevman	0:38ceb79fef03	1522	#define TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
kevman	0:38ceb79fef03	1523
kevman	0:38ceb79fef03	1524	/* TPI DEVID Register Definitions */
kevman	0:38ceb79fef03	1525	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
kevman	0:38ceb79fef03	1526	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
kevman	0:38ceb79fef03	1527
kevman	0:38ceb79fef03	1528	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
kevman	0:38ceb79fef03	1529	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
kevman	0:38ceb79fef03	1530
kevman	0:38ceb79fef03	1531	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
kevman	0:38ceb79fef03	1532	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
kevman	0:38ceb79fef03	1533
kevman	0:38ceb79fef03	1534	#define TPI_DEVID_FIFOSZ_Pos 6U /!< TPI DEVID: FIFOSZ Position /
kevman	0:38ceb79fef03	1535	#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /!< TPI DEVID: FIFOSZ Mask /
kevman	0:38ceb79fef03	1536
kevman	0:38ceb79fef03	1537	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
kevman	0:38ceb79fef03	1538	#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
kevman	0:38ceb79fef03	1539
kevman	0:38ceb79fef03	1540	/* TPI DEVTYPE Register Definitions */
kevman	0:38ceb79fef03	1541	#define TPI_DEVTYPE_SubType_Pos 4U /!< TPI DEVTYPE: SubType Position /
kevman	0:38ceb79fef03	1542	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
kevman	0:38ceb79fef03	1543
kevman	0:38ceb79fef03	1544	#define TPI_DEVTYPE_MajorType_Pos 0U /!< TPI DEVTYPE: MajorType Position /
kevman	0:38ceb79fef03	1545	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
kevman	0:38ceb79fef03	1546
kevman	0:38ceb79fef03	1547	/@}/ /* end of group CMSIS_TPI */
kevman	0:38ceb79fef03	1548
kevman	0:38ceb79fef03	1549
kevman	0:38ceb79fef03	1550	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman	0:38ceb79fef03	1551	/**
kevman	0:38ceb79fef03	1552	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1553	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
kevman	0:38ceb79fef03	1554	\brief Type definitions for the Memory Protection Unit (MPU)
kevman	0:38ceb79fef03	1555	@{
kevman	0:38ceb79fef03	1556	*/
kevman	0:38ceb79fef03	1557
kevman	0:38ceb79fef03	1558	/**
kevman	0:38ceb79fef03	1559	\brief Structure type to access the Memory Protection Unit (MPU).
kevman	0:38ceb79fef03	1560	*/
kevman	0:38ceb79fef03	1561	typedef struct
kevman	0:38ceb79fef03	1562	{
kevman	0:38ceb79fef03	1563	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
kevman	0:38ceb79fef03	1564	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
kevman	0:38ceb79fef03	1565	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
kevman	0:38ceb79fef03	1566	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
kevman	0:38ceb79fef03	1567	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
kevman	0:38ceb79fef03	1568	__IOM uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 /
kevman	0:38ceb79fef03	1569	__IOM uint32_t RLAR_A1; /!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 /
kevman	0:38ceb79fef03	1570	__IOM uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 /
kevman	0:38ceb79fef03	1571	__IOM uint32_t RLAR_A2; /!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 /
kevman	0:38ceb79fef03	1572	__IOM uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 /
kevman	0:38ceb79fef03	1573	__IOM uint32_t RLAR_A3; /!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 /
kevman	0:38ceb79fef03	1574	uint32_t RESERVED0[1];
kevman	0:38ceb79fef03	1575	union {
kevman	0:38ceb79fef03	1576	__IOM uint32_t MAIR[2];
kevman	0:38ceb79fef03	1577	struct {
kevman	0:38ceb79fef03	1578	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
kevman	0:38ceb79fef03	1579	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
kevman	0:38ceb79fef03	1580	};
kevman	0:38ceb79fef03	1581	};
kevman	0:38ceb79fef03	1582	} MPU_Type;
kevman	0:38ceb79fef03	1583
kevman	0:38ceb79fef03	1584	#define MPU_TYPE_RALIASES 4U
kevman	0:38ceb79fef03	1585
kevman	0:38ceb79fef03	1586	/* MPU Type Register Definitions */
kevman	0:38ceb79fef03	1587	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
kevman	0:38ceb79fef03	1588	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
kevman	0:38ceb79fef03	1589
kevman	0:38ceb79fef03	1590	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
kevman	0:38ceb79fef03	1591	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
kevman	0:38ceb79fef03	1592
kevman	0:38ceb79fef03	1593	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
kevman	0:38ceb79fef03	1594	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
kevman	0:38ceb79fef03	1595
kevman	0:38ceb79fef03	1596	/* MPU Control Register Definitions */
kevman	0:38ceb79fef03	1597	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
kevman	0:38ceb79fef03	1598	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
kevman	0:38ceb79fef03	1599
kevman	0:38ceb79fef03	1600	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
kevman	0:38ceb79fef03	1601	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
kevman	0:38ceb79fef03	1602
kevman	0:38ceb79fef03	1603	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
kevman	0:38ceb79fef03	1604	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
kevman	0:38ceb79fef03	1605
kevman	0:38ceb79fef03	1606	/* MPU Region Number Register Definitions */
kevman	0:38ceb79fef03	1607	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
kevman	0:38ceb79fef03	1608	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
kevman	0:38ceb79fef03	1609
kevman	0:38ceb79fef03	1610	/* MPU Region Base Address Register Definitions */
kevman	0:38ceb79fef03	1611	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
kevman	0:38ceb79fef03	1612	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
kevman	0:38ceb79fef03	1613
kevman	0:38ceb79fef03	1614	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
kevman	0:38ceb79fef03	1615	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
kevman	0:38ceb79fef03	1616
kevman	0:38ceb79fef03	1617	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
kevman	0:38ceb79fef03	1618	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
kevman	0:38ceb79fef03	1619
kevman	0:38ceb79fef03	1620	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
kevman	0:38ceb79fef03	1621	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
kevman	0:38ceb79fef03	1622
kevman	0:38ceb79fef03	1623	/* MPU Region Limit Address Register Definitions */
kevman	0:38ceb79fef03	1624	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
kevman	0:38ceb79fef03	1625	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
kevman	0:38ceb79fef03	1626
kevman	0:38ceb79fef03	1627	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
kevman	0:38ceb79fef03	1628	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
kevman	0:38ceb79fef03	1629
kevman	0:38ceb79fef03	1630	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: Region enable bit Position /
kevman	0:38ceb79fef03	1631	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: Region enable bit Disable Mask /
kevman	0:38ceb79fef03	1632
kevman	0:38ceb79fef03	1633	/* MPU Memory Attribute Indirection Register 0 Definitions */
kevman	0:38ceb79fef03	1634	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
kevman	0:38ceb79fef03	1635	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
kevman	0:38ceb79fef03	1636
kevman	0:38ceb79fef03	1637	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
kevman	0:38ceb79fef03	1638	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
kevman	0:38ceb79fef03	1639
kevman	0:38ceb79fef03	1640	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
kevman	0:38ceb79fef03	1641	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
kevman	0:38ceb79fef03	1642
kevman	0:38ceb79fef03	1643	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
kevman	0:38ceb79fef03	1644	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
kevman	0:38ceb79fef03	1645
kevman	0:38ceb79fef03	1646	/* MPU Memory Attribute Indirection Register 1 Definitions */
kevman	0:38ceb79fef03	1647	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
kevman	0:38ceb79fef03	1648	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
kevman	0:38ceb79fef03	1649
kevman	0:38ceb79fef03	1650	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
kevman	0:38ceb79fef03	1651	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
kevman	0:38ceb79fef03	1652
kevman	0:38ceb79fef03	1653	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
kevman	0:38ceb79fef03	1654	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
kevman	0:38ceb79fef03	1655
kevman	0:38ceb79fef03	1656	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
kevman	0:38ceb79fef03	1657	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
kevman	0:38ceb79fef03	1658
kevman	0:38ceb79fef03	1659	/@} end of group CMSIS_MPU /
kevman	0:38ceb79fef03	1660	#endif
kevman	0:38ceb79fef03	1661
kevman	0:38ceb79fef03	1662
kevman	0:38ceb79fef03	1663	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kevman	0:38ceb79fef03	1664	/**
kevman	0:38ceb79fef03	1665	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1666	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
kevman	0:38ceb79fef03	1667	\brief Type definitions for the Security Attribution Unit (SAU)
kevman	0:38ceb79fef03	1668	@{
kevman	0:38ceb79fef03	1669	*/
kevman	0:38ceb79fef03	1670
kevman	0:38ceb79fef03	1671	/**
kevman	0:38ceb79fef03	1672	\brief Structure type to access the Security Attribution Unit (SAU).
kevman	0:38ceb79fef03	1673	*/
kevman	0:38ceb79fef03	1674	typedef struct
kevman	0:38ceb79fef03	1675	{
kevman	0:38ceb79fef03	1676	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
kevman	0:38ceb79fef03	1677	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
kevman	0:38ceb79fef03	1678	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
kevman	0:38ceb79fef03	1679	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
kevman	0:38ceb79fef03	1680	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
kevman	0:38ceb79fef03	1681	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
kevman	0:38ceb79fef03	1682	#else
kevman	0:38ceb79fef03	1683	uint32_t RESERVED0[3];
kevman	0:38ceb79fef03	1684	#endif
kevman	0:38ceb79fef03	1685	__IOM uint32_t SFSR; /!< Offset: 0x014 (R/W) Secure Fault Status Register /
kevman	0:38ceb79fef03	1686	__IOM uint32_t SFAR; /!< Offset: 0x018 (R/W) Secure Fault Address Register /
kevman	0:38ceb79fef03	1687	} SAU_Type;
kevman	0:38ceb79fef03	1688
kevman	0:38ceb79fef03	1689	/* SAU Control Register Definitions */
kevman	0:38ceb79fef03	1690	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
kevman	0:38ceb79fef03	1691	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
kevman	0:38ceb79fef03	1692
kevman	0:38ceb79fef03	1693	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
kevman	0:38ceb79fef03	1694	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
kevman	0:38ceb79fef03	1695
kevman	0:38ceb79fef03	1696	/* SAU Type Register Definitions */
kevman	0:38ceb79fef03	1697	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
kevman	0:38ceb79fef03	1698	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
kevman	0:38ceb79fef03	1699
kevman	0:38ceb79fef03	1700	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
kevman	0:38ceb79fef03	1701	/* SAU Region Number Register Definitions */
kevman	0:38ceb79fef03	1702	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
kevman	0:38ceb79fef03	1703	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
kevman	0:38ceb79fef03	1704
kevman	0:38ceb79fef03	1705	/* SAU Region Base Address Register Definitions */
kevman	0:38ceb79fef03	1706	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
kevman	0:38ceb79fef03	1707	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
kevman	0:38ceb79fef03	1708
kevman	0:38ceb79fef03	1709	/* SAU Region Limit Address Register Definitions */
kevman	0:38ceb79fef03	1710	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
kevman	0:38ceb79fef03	1711	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
kevman	0:38ceb79fef03	1712
kevman	0:38ceb79fef03	1713	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
kevman	0:38ceb79fef03	1714	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
kevman	0:38ceb79fef03	1715
kevman	0:38ceb79fef03	1716	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
kevman	0:38ceb79fef03	1717	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
kevman	0:38ceb79fef03	1718
kevman	0:38ceb79fef03	1719	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
kevman	0:38ceb79fef03	1720
kevman	0:38ceb79fef03	1721	/* Secure Fault Status Register Definitions */
kevman	0:38ceb79fef03	1722	#define SAU_SFSR_LSERR_Pos 7U /!< SAU SFSR: LSERR Position /
kevman	0:38ceb79fef03	1723	#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /!< SAU SFSR: LSERR Mask /
kevman	0:38ceb79fef03	1724
kevman	0:38ceb79fef03	1725	#define SAU_SFSR_SFARVALID_Pos 6U /!< SAU SFSR: SFARVALID Position /
kevman	0:38ceb79fef03	1726	#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /!< SAU SFSR: SFARVALID Mask /
kevman	0:38ceb79fef03	1727
kevman	0:38ceb79fef03	1728	#define SAU_SFSR_LSPERR_Pos 5U /!< SAU SFSR: LSPERR Position /
kevman	0:38ceb79fef03	1729	#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /!< SAU SFSR: LSPERR Mask /
kevman	0:38ceb79fef03	1730
kevman	0:38ceb79fef03	1731	#define SAU_SFSR_INVTRAN_Pos 4U /!< SAU SFSR: INVTRAN Position /
kevman	0:38ceb79fef03	1732	#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /!< SAU SFSR: INVTRAN Mask /
kevman	0:38ceb79fef03	1733
kevman	0:38ceb79fef03	1734	#define SAU_SFSR_AUVIOL_Pos 3U /!< SAU SFSR: AUVIOL Position /
kevman	0:38ceb79fef03	1735	#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /!< SAU SFSR: AUVIOL Mask /
kevman	0:38ceb79fef03	1736
kevman	0:38ceb79fef03	1737	#define SAU_SFSR_INVER_Pos 2U /!< SAU SFSR: INVER Position /
kevman	0:38ceb79fef03	1738	#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /!< SAU SFSR: INVER Mask /
kevman	0:38ceb79fef03	1739
kevman	0:38ceb79fef03	1740	#define SAU_SFSR_INVIS_Pos 1U /!< SAU SFSR: INVIS Position /
kevman	0:38ceb79fef03	1741	#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /!< SAU SFSR: INVIS Mask /
kevman	0:38ceb79fef03	1742
kevman	0:38ceb79fef03	1743	#define SAU_SFSR_INVEP_Pos 0U /!< SAU SFSR: INVEP Position /
kevman	0:38ceb79fef03	1744	#define SAU_SFSR_INVEP_Msk (1UL /<< SAU_SFSR_INVEP_Pos/) /!< SAU SFSR: INVEP Mask /
kevman	0:38ceb79fef03	1745
kevman	0:38ceb79fef03	1746	/@} end of group CMSIS_SAU /
kevman	0:38ceb79fef03	1747	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kevman	0:38ceb79fef03	1748
kevman	0:38ceb79fef03	1749
kevman	0:38ceb79fef03	1750	/**
kevman	0:38ceb79fef03	1751	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1752	\defgroup CMSIS_FPU Floating Point Unit (FPU)
kevman	0:38ceb79fef03	1753	\brief Type definitions for the Floating Point Unit (FPU)
kevman	0:38ceb79fef03	1754	@{
kevman	0:38ceb79fef03	1755	*/
kevman	0:38ceb79fef03	1756
kevman	0:38ceb79fef03	1757	/**
kevman	0:38ceb79fef03	1758	\brief Structure type to access the Floating Point Unit (FPU).
kevman	0:38ceb79fef03	1759	*/
kevman	0:38ceb79fef03	1760	typedef struct
kevman	0:38ceb79fef03	1761	{
kevman	0:38ceb79fef03	1762	uint32_t RESERVED0[1U];
kevman	0:38ceb79fef03	1763	__IOM uint32_t FPCCR; /!< Offset: 0x004 (R/W) Floating-Point Context Control Register /
kevman	0:38ceb79fef03	1764	__IOM uint32_t FPCAR; /!< Offset: 0x008 (R/W) Floating-Point Context Address Register /
kevman	0:38ceb79fef03	1765	__IOM uint32_t FPDSCR; /!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register /
kevman	0:38ceb79fef03	1766	__IM uint32_t MVFR0; /!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 /
kevman	0:38ceb79fef03	1767	__IM uint32_t MVFR1; /!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 /
kevman	0:38ceb79fef03	1768	} FPU_Type;
kevman	0:38ceb79fef03	1769
kevman	0:38ceb79fef03	1770	/* Floating-Point Context Control Register Definitions */
kevman	0:38ceb79fef03	1771	#define FPU_FPCCR_ASPEN_Pos 31U /!< FPCCR: ASPEN bit Position /
kevman	0:38ceb79fef03	1772	#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /!< FPCCR: ASPEN bit Mask /
kevman	0:38ceb79fef03	1773
kevman	0:38ceb79fef03	1774	#define FPU_FPCCR_LSPEN_Pos 30U /!< FPCCR: LSPEN Position /
kevman	0:38ceb79fef03	1775	#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /!< FPCCR: LSPEN bit Mask /
kevman	0:38ceb79fef03	1776
kevman	0:38ceb79fef03	1777	#define FPU_FPCCR_LSPENS_Pos 29U /!< FPCCR: LSPENS Position /
kevman	0:38ceb79fef03	1778	#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /!< FPCCR: LSPENS bit Mask /
kevman	0:38ceb79fef03	1779
kevman	0:38ceb79fef03	1780	#define FPU_FPCCR_CLRONRET_Pos 28U /!< FPCCR: CLRONRET Position /
kevman	0:38ceb79fef03	1781	#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /!< FPCCR: CLRONRET bit Mask /
kevman	0:38ceb79fef03	1782
kevman	0:38ceb79fef03	1783	#define FPU_FPCCR_CLRONRETS_Pos 27U /!< FPCCR: CLRONRETS Position /
kevman	0:38ceb79fef03	1784	#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /!< FPCCR: CLRONRETS bit Mask /
kevman	0:38ceb79fef03	1785
kevman	0:38ceb79fef03	1786	#define FPU_FPCCR_TS_Pos 26U /!< FPCCR: TS Position /
kevman	0:38ceb79fef03	1787	#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /!< FPCCR: TS bit Mask /
kevman	0:38ceb79fef03	1788
kevman	0:38ceb79fef03	1789	#define FPU_FPCCR_UFRDY_Pos 10U /!< FPCCR: UFRDY Position /
kevman	0:38ceb79fef03	1790	#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /!< FPCCR: UFRDY bit Mask /
kevman	0:38ceb79fef03	1791
kevman	0:38ceb79fef03	1792	#define FPU_FPCCR_SPLIMVIOL_Pos 9U /!< FPCCR: SPLIMVIOL Position /
kevman	0:38ceb79fef03	1793	#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /!< FPCCR: SPLIMVIOL bit Mask /
kevman	0:38ceb79fef03	1794
kevman	0:38ceb79fef03	1795	#define FPU_FPCCR_MONRDY_Pos 8U /!< FPCCR: MONRDY Position /
kevman	0:38ceb79fef03	1796	#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /!< FPCCR: MONRDY bit Mask /
kevman	0:38ceb79fef03	1797
kevman	0:38ceb79fef03	1798	#define FPU_FPCCR_SFRDY_Pos 7U /!< FPCCR: SFRDY Position /
kevman	0:38ceb79fef03	1799	#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /!< FPCCR: SFRDY bit Mask /
kevman	0:38ceb79fef03	1800
kevman	0:38ceb79fef03	1801	#define FPU_FPCCR_BFRDY_Pos 6U /!< FPCCR: BFRDY Position /
kevman	0:38ceb79fef03	1802	#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /!< FPCCR: BFRDY bit Mask /
kevman	0:38ceb79fef03	1803
kevman	0:38ceb79fef03	1804	#define FPU_FPCCR_MMRDY_Pos 5U /!< FPCCR: MMRDY Position /
kevman	0:38ceb79fef03	1805	#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /!< FPCCR: MMRDY bit Mask /
kevman	0:38ceb79fef03	1806
kevman	0:38ceb79fef03	1807	#define FPU_FPCCR_HFRDY_Pos 4U /!< FPCCR: HFRDY Position /
kevman	0:38ceb79fef03	1808	#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /!< FPCCR: HFRDY bit Mask /
kevman	0:38ceb79fef03	1809
kevman	0:38ceb79fef03	1810	#define FPU_FPCCR_THREAD_Pos 3U /!< FPCCR: processor mode bit Position /
kevman	0:38ceb79fef03	1811	#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /!< FPCCR: processor mode active bit Mask /
kevman	0:38ceb79fef03	1812
kevman	0:38ceb79fef03	1813	#define FPU_FPCCR_S_Pos 2U /!< FPCCR: Security status of the FP context bit Position /
kevman	0:38ceb79fef03	1814	#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /!< FPCCR: Security status of the FP context bit Mask /
kevman	0:38ceb79fef03	1815
kevman	0:38ceb79fef03	1816	#define FPU_FPCCR_USER_Pos 1U /!< FPCCR: privilege level bit Position /
kevman	0:38ceb79fef03	1817	#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /!< FPCCR: privilege level bit Mask /
kevman	0:38ceb79fef03	1818
kevman	0:38ceb79fef03	1819	#define FPU_FPCCR_LSPACT_Pos 0U /!< FPCCR: Lazy state preservation active bit Position /
kevman	0:38ceb79fef03	1820	#define FPU_FPCCR_LSPACT_Msk (1UL /<< FPU_FPCCR_LSPACT_Pos/) /!< FPCCR: Lazy state preservation active bit Mask /
kevman	0:38ceb79fef03	1821
kevman	0:38ceb79fef03	1822	/* Floating-Point Context Address Register Definitions */
kevman	0:38ceb79fef03	1823	#define FPU_FPCAR_ADDRESS_Pos 3U /!< FPCAR: ADDRESS bit Position /
kevman	0:38ceb79fef03	1824	#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /!< FPCAR: ADDRESS bit Mask /
kevman	0:38ceb79fef03	1825
kevman	0:38ceb79fef03	1826	/* Floating-Point Default Status Control Register Definitions */
kevman	0:38ceb79fef03	1827	#define FPU_FPDSCR_AHP_Pos 26U /!< FPDSCR: AHP bit Position /
kevman	0:38ceb79fef03	1828	#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /!< FPDSCR: AHP bit Mask /
kevman	0:38ceb79fef03	1829
kevman	0:38ceb79fef03	1830	#define FPU_FPDSCR_DN_Pos 25U /!< FPDSCR: DN bit Position /
kevman	0:38ceb79fef03	1831	#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /!< FPDSCR: DN bit Mask /
kevman	0:38ceb79fef03	1832
kevman	0:38ceb79fef03	1833	#define FPU_FPDSCR_FZ_Pos 24U /!< FPDSCR: FZ bit Position /
kevman	0:38ceb79fef03	1834	#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /!< FPDSCR: FZ bit Mask /
kevman	0:38ceb79fef03	1835
kevman	0:38ceb79fef03	1836	#define FPU_FPDSCR_RMode_Pos 22U /!< FPDSCR: RMode bit Position /
kevman	0:38ceb79fef03	1837	#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /!< FPDSCR: RMode bit Mask /
kevman	0:38ceb79fef03	1838
kevman	0:38ceb79fef03	1839	/* Media and FP Feature Register 0 Definitions */
kevman	0:38ceb79fef03	1840	#define FPU_MVFR0_FP_rounding_modes_Pos 28U /!< MVFR0: FP rounding modes bits Position /
kevman	0:38ceb79fef03	1841	#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /!< MVFR0: FP rounding modes bits Mask /
kevman	0:38ceb79fef03	1842
kevman	0:38ceb79fef03	1843	#define FPU_MVFR0_Short_vectors_Pos 24U /!< MVFR0: Short vectors bits Position /
kevman	0:38ceb79fef03	1844	#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /!< MVFR0: Short vectors bits Mask /
kevman	0:38ceb79fef03	1845
kevman	0:38ceb79fef03	1846	#define FPU_MVFR0_Square_root_Pos 20U /!< MVFR0: Square root bits Position /
kevman	0:38ceb79fef03	1847	#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /!< MVFR0: Square root bits Mask /
kevman	0:38ceb79fef03	1848
kevman	0:38ceb79fef03	1849	#define FPU_MVFR0_Divide_Pos 16U /!< MVFR0: Divide bits Position /
kevman	0:38ceb79fef03	1850	#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /!< MVFR0: Divide bits Mask /
kevman	0:38ceb79fef03	1851
kevman	0:38ceb79fef03	1852	#define FPU_MVFR0_FP_excep_trapping_Pos 12U /!< MVFR0: FP exception trapping bits Position /
kevman	0:38ceb79fef03	1853	#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /!< MVFR0: FP exception trapping bits Mask /
kevman	0:38ceb79fef03	1854
kevman	0:38ceb79fef03	1855	#define FPU_MVFR0_Double_precision_Pos 8U /!< MVFR0: Double-precision bits Position /
kevman	0:38ceb79fef03	1856	#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /!< MVFR0: Double-precision bits Mask /
kevman	0:38ceb79fef03	1857
kevman	0:38ceb79fef03	1858	#define FPU_MVFR0_Single_precision_Pos 4U /!< MVFR0: Single-precision bits Position /
kevman	0:38ceb79fef03	1859	#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /!< MVFR0: Single-precision bits Mask /
kevman	0:38ceb79fef03	1860
kevman	0:38ceb79fef03	1861	#define FPU_MVFR0_A_SIMD_registers_Pos 0U /!< MVFR0: A_SIMD registers bits Position /
kevman	0:38ceb79fef03	1862	#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /<< FPU_MVFR0_A_SIMD_registers_Pos/) /!< MVFR0: A_SIMD registers bits Mask /
kevman	0:38ceb79fef03	1863
kevman	0:38ceb79fef03	1864	/* Media and FP Feature Register 1 Definitions */
kevman	0:38ceb79fef03	1865	#define FPU_MVFR1_FP_fused_MAC_Pos 28U /!< MVFR1: FP fused MAC bits Position /
kevman	0:38ceb79fef03	1866	#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /!< MVFR1: FP fused MAC bits Mask /
kevman	0:38ceb79fef03	1867
kevman	0:38ceb79fef03	1868	#define FPU_MVFR1_FP_HPFP_Pos 24U /!< MVFR1: FP HPFP bits Position /
kevman	0:38ceb79fef03	1869	#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /!< MVFR1: FP HPFP bits Mask /
kevman	0:38ceb79fef03	1870
kevman	0:38ceb79fef03	1871	#define FPU_MVFR1_D_NaN_mode_Pos 4U /!< MVFR1: D_NaN mode bits Position /
kevman	0:38ceb79fef03	1872	#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /!< MVFR1: D_NaN mode bits Mask /
kevman	0:38ceb79fef03	1873
kevman	0:38ceb79fef03	1874	#define FPU_MVFR1_FtZ_mode_Pos 0U /!< MVFR1: FtZ mode bits Position /
kevman	0:38ceb79fef03	1875	#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /<< FPU_MVFR1_FtZ_mode_Pos/) /!< MVFR1: FtZ mode bits Mask /
kevman	0:38ceb79fef03	1876
kevman	0:38ceb79fef03	1877	/@} end of group CMSIS_FPU /
kevman	0:38ceb79fef03	1878
kevman	0:38ceb79fef03	1879
kevman	0:38ceb79fef03	1880	/**
kevman	0:38ceb79fef03	1881	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	1882	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
kevman	0:38ceb79fef03	1883	\brief Type definitions for the Core Debug Registers
kevman	0:38ceb79fef03	1884	@{
kevman	0:38ceb79fef03	1885	*/
kevman	0:38ceb79fef03	1886
kevman	0:38ceb79fef03	1887	/**
kevman	0:38ceb79fef03	1888	\brief Structure type to access the Core Debug Register (CoreDebug).
kevman	0:38ceb79fef03	1889	*/
kevman	0:38ceb79fef03	1890	typedef struct
kevman	0:38ceb79fef03	1891	{
kevman	0:38ceb79fef03	1892	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
kevman	0:38ceb79fef03	1893	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
kevman	0:38ceb79fef03	1894	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
kevman	0:38ceb79fef03	1895	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
kevman	0:38ceb79fef03	1896	uint32_t RESERVED4[1U];
kevman	0:38ceb79fef03	1897	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
kevman	0:38ceb79fef03	1898	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
kevman	0:38ceb79fef03	1899	} CoreDebug_Type;
kevman	0:38ceb79fef03	1900
kevman	0:38ceb79fef03	1901	/* Debug Halting Control and Status Register Definitions */
kevman	0:38ceb79fef03	1902	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
kevman	0:38ceb79fef03	1903	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
kevman	0:38ceb79fef03	1904
kevman	0:38ceb79fef03	1905	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
kevman	0:38ceb79fef03	1906	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
kevman	0:38ceb79fef03	1907
kevman	0:38ceb79fef03	1908	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
kevman	0:38ceb79fef03	1909	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
kevman	0:38ceb79fef03	1910
kevman	0:38ceb79fef03	1911	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
kevman	0:38ceb79fef03	1912	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
kevman	0:38ceb79fef03	1913
kevman	0:38ceb79fef03	1914	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
kevman	0:38ceb79fef03	1915	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
kevman	0:38ceb79fef03	1916
kevman	0:38ceb79fef03	1917	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
kevman	0:38ceb79fef03	1918	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
kevman	0:38ceb79fef03	1919
kevman	0:38ceb79fef03	1920	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
kevman	0:38ceb79fef03	1921	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
kevman	0:38ceb79fef03	1922
kevman	0:38ceb79fef03	1923	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
kevman	0:38ceb79fef03	1924	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
kevman	0:38ceb79fef03	1925
kevman	0:38ceb79fef03	1926	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /!< CoreDebug DHCSR: C_SNAPSTALL Position /
kevman	0:38ceb79fef03	1927	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
kevman	0:38ceb79fef03	1928
kevman	0:38ceb79fef03	1929	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
kevman	0:38ceb79fef03	1930	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
kevman	0:38ceb79fef03	1931
kevman	0:38ceb79fef03	1932	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
kevman	0:38ceb79fef03	1933	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
kevman	0:38ceb79fef03	1934
kevman	0:38ceb79fef03	1935	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
kevman	0:38ceb79fef03	1936	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
kevman	0:38ceb79fef03	1937
kevman	0:38ceb79fef03	1938	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
kevman	0:38ceb79fef03	1939	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
kevman	0:38ceb79fef03	1940
kevman	0:38ceb79fef03	1941	/* Debug Core Register Selector Register Definitions */
kevman	0:38ceb79fef03	1942	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
kevman	0:38ceb79fef03	1943	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
kevman	0:38ceb79fef03	1944
kevman	0:38ceb79fef03	1945	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
kevman	0:38ceb79fef03	1946	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
kevman	0:38ceb79fef03	1947
kevman	0:38ceb79fef03	1948	/* Debug Exception and Monitor Control Register Definitions */
kevman	0:38ceb79fef03	1949	#define CoreDebug_DEMCR_TRCENA_Pos 24U /!< CoreDebug DEMCR: TRCENA Position /
kevman	0:38ceb79fef03	1950	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
kevman	0:38ceb79fef03	1951
kevman	0:38ceb79fef03	1952	#define CoreDebug_DEMCR_MON_REQ_Pos 19U /!< CoreDebug DEMCR: MON_REQ Position /
kevman	0:38ceb79fef03	1953	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
kevman	0:38ceb79fef03	1954
kevman	0:38ceb79fef03	1955	#define CoreDebug_DEMCR_MON_STEP_Pos 18U /!< CoreDebug DEMCR: MON_STEP Position /
kevman	0:38ceb79fef03	1956	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
kevman	0:38ceb79fef03	1957
kevman	0:38ceb79fef03	1958	#define CoreDebug_DEMCR_MON_PEND_Pos 17U /!< CoreDebug DEMCR: MON_PEND Position /
kevman	0:38ceb79fef03	1959	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
kevman	0:38ceb79fef03	1960
kevman	0:38ceb79fef03	1961	#define CoreDebug_DEMCR_MON_EN_Pos 16U /!< CoreDebug DEMCR: MON_EN Position /
kevman	0:38ceb79fef03	1962	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
kevman	0:38ceb79fef03	1963
kevman	0:38ceb79fef03	1964	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
kevman	0:38ceb79fef03	1965	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
kevman	0:38ceb79fef03	1966
kevman	0:38ceb79fef03	1967	#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /!< CoreDebug DEMCR: VC_INTERR Position /
kevman	0:38ceb79fef03	1968	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
kevman	0:38ceb79fef03	1969
kevman	0:38ceb79fef03	1970	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /!< CoreDebug DEMCR: VC_BUSERR Position /
kevman	0:38ceb79fef03	1971	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
kevman	0:38ceb79fef03	1972
kevman	0:38ceb79fef03	1973	#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /!< CoreDebug DEMCR: VC_STATERR Position /
kevman	0:38ceb79fef03	1974	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
kevman	0:38ceb79fef03	1975
kevman	0:38ceb79fef03	1976	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /!< CoreDebug DEMCR: VC_CHKERR Position /
kevman	0:38ceb79fef03	1977	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
kevman	0:38ceb79fef03	1978
kevman	0:38ceb79fef03	1979	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /!< CoreDebug DEMCR: VC_NOCPERR Position /
kevman	0:38ceb79fef03	1980	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
kevman	0:38ceb79fef03	1981
kevman	0:38ceb79fef03	1982	#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /!< CoreDebug DEMCR: VC_MMERR Position /
kevman	0:38ceb79fef03	1983	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
kevman	0:38ceb79fef03	1984
kevman	0:38ceb79fef03	1985	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
kevman	0:38ceb79fef03	1986	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
kevman	0:38ceb79fef03	1987
kevman	0:38ceb79fef03	1988	/* Debug Authentication Control Register Definitions */
kevman	0:38ceb79fef03	1989	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
kevman	0:38ceb79fef03	1990	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
kevman	0:38ceb79fef03	1991
kevman	0:38ceb79fef03	1992	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
kevman	0:38ceb79fef03	1993	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
kevman	0:38ceb79fef03	1994
kevman	0:38ceb79fef03	1995	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
kevman	0:38ceb79fef03	1996	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
kevman	0:38ceb79fef03	1997
kevman	0:38ceb79fef03	1998	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
kevman	0:38ceb79fef03	1999	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
kevman	0:38ceb79fef03	2000
kevman	0:38ceb79fef03	2001	/* Debug Security Control and Status Register Definitions */
kevman	0:38ceb79fef03	2002	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
kevman	0:38ceb79fef03	2003	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
kevman	0:38ceb79fef03	2004
kevman	0:38ceb79fef03	2005	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
kevman	0:38ceb79fef03	2006	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
kevman	0:38ceb79fef03	2007
kevman	0:38ceb79fef03	2008	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
kevman	0:38ceb79fef03	2009	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
kevman	0:38ceb79fef03	2010
kevman	0:38ceb79fef03	2011	/@} end of group CMSIS_CoreDebug /
kevman	0:38ceb79fef03	2012
kevman	0:38ceb79fef03	2013
kevman	0:38ceb79fef03	2014	/**
kevman	0:38ceb79fef03	2015	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	2016	\defgroup CMSIS_core_bitfield Core register bit field macros
kevman	0:38ceb79fef03	2017	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
kevman	0:38ceb79fef03	2018	@{
kevman	0:38ceb79fef03	2019	*/
kevman	0:38ceb79fef03	2020
kevman	0:38ceb79fef03	2021	/**
kevman	0:38ceb79fef03	2022	\brief Mask and shift a bit field value for use in a register bit range.
kevman	0:38ceb79fef03	2023	\param[in] field Name of the register bit field.
kevman	0:38ceb79fef03	2024	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
kevman	0:38ceb79fef03	2025	\return Masked and shifted value.
kevman	0:38ceb79fef03	2026	*/
kevman	0:38ceb79fef03	2027	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
kevman	0:38ceb79fef03	2028
kevman	0:38ceb79fef03	2029	/**
kevman	0:38ceb79fef03	2030	\brief Mask and shift a register value to extract a bit filed value.
kevman	0:38ceb79fef03	2031	\param[in] field Name of the register bit field.
kevman	0:38ceb79fef03	2032	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
kevman	0:38ceb79fef03	2033	\return Masked and shifted bit field value.
kevman	0:38ceb79fef03	2034	*/
kevman	0:38ceb79fef03	2035	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
kevman	0:38ceb79fef03	2036
kevman	0:38ceb79fef03	2037	/@} end of group CMSIS_core_bitfield /
kevman	0:38ceb79fef03	2038
kevman	0:38ceb79fef03	2039
kevman	0:38ceb79fef03	2040	/**
kevman	0:38ceb79fef03	2041	\ingroup CMSIS_core_register
kevman	0:38ceb79fef03	2042	\defgroup CMSIS_core_base Core Definitions
kevman	0:38ceb79fef03	2043	\brief Definitions for base addresses, unions, and structures.
kevman	0:38ceb79fef03	2044	@{
kevman	0:38ceb79fef03	2045	*/
kevman	0:38ceb79fef03	2046
kevman	0:38ceb79fef03	2047	/* Memory mapping of Core Hardware */
kevman	0:38ceb79fef03	2048	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
kevman	0:38ceb79fef03	2049	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
kevman	0:38ceb79fef03	2050	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
kevman	0:38ceb79fef03	2051	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
kevman	0:38ceb79fef03	2052	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
kevman	0:38ceb79fef03	2053	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
kevman	0:38ceb79fef03	2054	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
kevman	0:38ceb79fef03	2055	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
kevman	0:38ceb79fef03	2056
kevman	0:38ceb79fef03	2057	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
kevman	0:38ceb79fef03	2058	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
kevman	0:38ceb79fef03	2059	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
kevman	0:38ceb79fef03	2060	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
kevman	0:38ceb79fef03	2061	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
kevman	0:38ceb79fef03	2062	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
kevman	0:38ceb79fef03	2063	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
kevman	0:38ceb79fef03	2064	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
kevman	0:38ceb79fef03	2065
kevman	0:38ceb79fef03	2066	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman	0:38ceb79fef03	2067	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
kevman	0:38ceb79fef03	2068	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
kevman	0:38ceb79fef03	2069	#endif
kevman	0:38ceb79fef03	2070
kevman	0:38ceb79fef03	2071	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kevman	0:38ceb79fef03	2072	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
kevman	0:38ceb79fef03	2073	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
kevman	0:38ceb79fef03	2074	#endif
kevman	0:38ceb79fef03	2075
kevman	0:38ceb79fef03	2076	#define FPU_BASE (SCS_BASE + 0x0F30UL) /!< Floating Point Unit /
kevman	0:38ceb79fef03	2077	#define FPU ((FPU_Type ) FPU_BASE ) /!< Floating Point Unit */
kevman	0:38ceb79fef03	2078
kevman	0:38ceb79fef03	2079	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kevman	0:38ceb79fef03	2080	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
kevman	0:38ceb79fef03	2081	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
kevman	0:38ceb79fef03	2082	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
kevman	0:38ceb79fef03	2083	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
kevman	0:38ceb79fef03	2084	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
kevman	0:38ceb79fef03	2085
kevman	0:38ceb79fef03	2086	#define SCnSCB_NS ((SCnSCB_Type ) SCS_BASE_NS ) /!< System control Register not in SCB(non-secure address space) */
kevman	0:38ceb79fef03	2087	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
kevman	0:38ceb79fef03	2088	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
kevman	0:38ceb79fef03	2089	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
kevman	0:38ceb79fef03	2090	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
kevman	0:38ceb79fef03	2091
kevman	0:38ceb79fef03	2092	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman	0:38ceb79fef03	2093	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
kevman	0:38ceb79fef03	2094	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
kevman	0:38ceb79fef03	2095	#endif
kevman	0:38ceb79fef03	2096
kevman	0:38ceb79fef03	2097	#define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /!< Floating Point Unit (non-secure address space) /
kevman	0:38ceb79fef03	2098	#define FPU_NS ((FPU_Type ) FPU_BASE_NS ) /!< Floating Point Unit (non-secure address space) */
kevman	0:38ceb79fef03	2099
kevman	0:38ceb79fef03	2100	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kevman	0:38ceb79fef03	2101	/@} /
kevman	0:38ceb79fef03	2102
kevman	0:38ceb79fef03	2103
kevman	0:38ceb79fef03	2104
kevman	0:38ceb79fef03	2105	/*******************************************************************************
kevman	0:38ceb79fef03	2106	* Hardware Abstraction Layer
kevman	0:38ceb79fef03	2107	Core Function Interface contains:
kevman	0:38ceb79fef03	2108	- Core NVIC Functions
kevman	0:38ceb79fef03	2109	- Core SysTick Functions
kevman	0:38ceb79fef03	2110	- Core Debug Functions
kevman	0:38ceb79fef03	2111	- Core Register Access Functions
kevman	0:38ceb79fef03	2112	******************************************************************************/
kevman	0:38ceb79fef03	2113	/**
kevman	0:38ceb79fef03	2114	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
kevman	0:38ceb79fef03	2115	*/
kevman	0:38ceb79fef03	2116
kevman	0:38ceb79fef03	2117
kevman	0:38ceb79fef03	2118
kevman	0:38ceb79fef03	2119	/* ########################## NVIC functions #################################### */
kevman	0:38ceb79fef03	2120	/**
kevman	0:38ceb79fef03	2121	\ingroup CMSIS_Core_FunctionInterface
kevman	0:38ceb79fef03	2122	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
kevman	0:38ceb79fef03	2123	\brief Functions that manage interrupts and exceptions via the NVIC.
kevman	0:38ceb79fef03	2124	@{
kevman	0:38ceb79fef03	2125	*/
kevman	0:38ceb79fef03	2126
kevman	0:38ceb79fef03	2127	#ifdef CMSIS_NVIC_VIRTUAL
kevman	0:38ceb79fef03	2128	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
kevman	0:38ceb79fef03	2129	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
kevman	0:38ceb79fef03	2130	#endif
kevman	0:38ceb79fef03	2131	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
kevman	0:38ceb79fef03	2132	#else
kevman	0:38ceb79fef03	2133	#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
kevman	0:38ceb79fef03	2134	#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
kevman	0:38ceb79fef03	2135	#define NVIC_EnableIRQ __NVIC_EnableIRQ
kevman	0:38ceb79fef03	2136	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
kevman	0:38ceb79fef03	2137	#define NVIC_DisableIRQ __NVIC_DisableIRQ
kevman	0:38ceb79fef03	2138	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
kevman	0:38ceb79fef03	2139	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
kevman	0:38ceb79fef03	2140	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
kevman	0:38ceb79fef03	2141	#define NVIC_GetActive __NVIC_GetActive
kevman	0:38ceb79fef03	2142	#define NVIC_SetPriority __NVIC_SetPriority
kevman	0:38ceb79fef03	2143	#define NVIC_GetPriority __NVIC_GetPriority
kevman	0:38ceb79fef03	2144	#define NVIC_SystemReset __NVIC_SystemReset
kevman	0:38ceb79fef03	2145	#endif /* CMSIS_NVIC_VIRTUAL */
kevman	0:38ceb79fef03	2146
kevman	0:38ceb79fef03	2147	#ifdef CMSIS_VECTAB_VIRTUAL
kevman	0:38ceb79fef03	2148	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kevman	0:38ceb79fef03	2149	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
kevman	0:38ceb79fef03	2150	#endif
kevman	0:38ceb79fef03	2151	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kevman	0:38ceb79fef03	2152	#else
kevman	0:38ceb79fef03	2153	#define NVIC_SetVector __NVIC_SetVector
kevman	0:38ceb79fef03	2154	#define NVIC_GetVector __NVIC_GetVector
kevman	0:38ceb79fef03	2155	#endif /* (CMSIS_VECTAB_VIRTUAL) */
kevman	0:38ceb79fef03	2156
kevman	0:38ceb79fef03	2157	#define NVIC_USER_IRQ_OFFSET 16
kevman	0:38ceb79fef03	2158
kevman	0:38ceb79fef03	2159
kevman	0:38ceb79fef03	2160	/* Special LR values for Secure/Non-Secure call handling and exception handling */
kevman	0:38ceb79fef03	2161
kevman	0:38ceb79fef03	2162	/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
kevman	0:38ceb79fef03	2163	#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
kevman	0:38ceb79fef03	2164
kevman	0:38ceb79fef03	2165	/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
kevman	0:38ceb79fef03	2166	#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
kevman	0:38ceb79fef03	2167	#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
kevman	0:38ceb79fef03	2168	#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
kevman	0:38ceb79fef03	2169	#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
kevman	0:38ceb79fef03	2170	#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
kevman	0:38ceb79fef03	2171	#define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
kevman	0:38ceb79fef03	2172	#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
kevman	0:38ceb79fef03	2173
kevman	0:38ceb79fef03	2174	/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
kevman	0:38ceb79fef03	2175	#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
kevman	0:38ceb79fef03	2176	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
kevman	0:38ceb79fef03	2177	#else
kevman	0:38ceb79fef03	2178	#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
kevman	0:38ceb79fef03	2179	#endif
kevman	0:38ceb79fef03	2180
kevman	0:38ceb79fef03	2181
kevman	0:38ceb79fef03	2182	/**
kevman	0:38ceb79fef03	2183	\brief Set Priority Grouping
kevman	0:38ceb79fef03	2184	\details Sets the priority grouping field using the required unlock sequence.
kevman	0:38ceb79fef03	2185	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
kevman	0:38ceb79fef03	2186	Only values from 0..7 are used.
kevman	0:38ceb79fef03	2187	In case of a conflict between priority grouping and available
kevman	0:38ceb79fef03	2188	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kevman	0:38ceb79fef03	2189	\param [in] PriorityGroup Priority grouping field.
kevman	0:38ceb79fef03	2190	*/
kevman	0:38ceb79fef03	2191	__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
kevman	0:38ceb79fef03	2192	{
kevman	0:38ceb79fef03	2193	uint32_t reg_value;
kevman	0:38ceb79fef03	2194	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kevman	0:38ceb79fef03	2195
kevman	0:38ceb79fef03	2196	reg_value = SCB->AIRCR; /* read old register configuration */
kevman	0:38ceb79fef03	2197	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
kevman	0:38ceb79fef03	2198	reg_value = (reg_value \|
kevman	0:38ceb79fef03	2199	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kevman	0:38ceb79fef03	2200	(PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
kevman	0:38ceb79fef03	2201	SCB->AIRCR = reg_value;
kevman	0:38ceb79fef03	2202	}
kevman	0:38ceb79fef03	2203
kevman	0:38ceb79fef03	2204
kevman	0:38ceb79fef03	2205	/**
kevman	0:38ceb79fef03	2206	\brief Get Priority Grouping
kevman	0:38ceb79fef03	2207	\details Reads the priority grouping field from the NVIC Interrupt Controller.
kevman	0:38ceb79fef03	2208	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
kevman	0:38ceb79fef03	2209	*/
kevman	0:38ceb79fef03	2210	__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
kevman	0:38ceb79fef03	2211	{
kevman	0:38ceb79fef03	2212	return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
kevman	0:38ceb79fef03	2213	}
kevman	0:38ceb79fef03	2214
kevman	0:38ceb79fef03	2215
kevman	0:38ceb79fef03	2216	/**
kevman	0:38ceb79fef03	2217	\brief Enable Interrupt
kevman	0:38ceb79fef03	2218	\details Enables a device specific interrupt in the NVIC interrupt controller.
kevman	0:38ceb79fef03	2219	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2220	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2221	*/
kevman	0:38ceb79fef03	2222	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2223	{
kevman	0:38ceb79fef03	2224	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2225	{
kevman	0:38ceb79fef03	2226	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman	0:38ceb79fef03	2227	}
kevman	0:38ceb79fef03	2228	}
kevman	0:38ceb79fef03	2229
kevman	0:38ceb79fef03	2230
kevman	0:38ceb79fef03	2231	/**
kevman	0:38ceb79fef03	2232	\brief Get Interrupt Enable status
kevman	0:38ceb79fef03	2233	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
kevman	0:38ceb79fef03	2234	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2235	\return 0 Interrupt is not enabled.
kevman	0:38ceb79fef03	2236	\return 1 Interrupt is enabled.
kevman	0:38ceb79fef03	2237	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2238	*/
kevman	0:38ceb79fef03	2239	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2240	{
kevman	0:38ceb79fef03	2241	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2242	{
kevman	0:38ceb79fef03	2243	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2244	}
kevman	0:38ceb79fef03	2245	else
kevman	0:38ceb79fef03	2246	{
kevman	0:38ceb79fef03	2247	return(0U);
kevman	0:38ceb79fef03	2248	}
kevman	0:38ceb79fef03	2249	}
kevman	0:38ceb79fef03	2250
kevman	0:38ceb79fef03	2251
kevman	0:38ceb79fef03	2252	/**
kevman	0:38ceb79fef03	2253	\brief Disable Interrupt
kevman	0:38ceb79fef03	2254	\details Disables a device specific interrupt in the NVIC interrupt controller.
kevman	0:38ceb79fef03	2255	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2256	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2257	*/
kevman	0:38ceb79fef03	2258	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2259	{
kevman	0:38ceb79fef03	2260	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2261	{
kevman	0:38ceb79fef03	2262	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman	0:38ceb79fef03	2263	__DSB();
kevman	0:38ceb79fef03	2264	__ISB();
kevman	0:38ceb79fef03	2265	}
kevman	0:38ceb79fef03	2266	}
kevman	0:38ceb79fef03	2267
kevman	0:38ceb79fef03	2268
kevman	0:38ceb79fef03	2269	/**
kevman	0:38ceb79fef03	2270	\brief Get Pending Interrupt
kevman	0:38ceb79fef03	2271	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
kevman	0:38ceb79fef03	2272	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2273	\return 0 Interrupt status is not pending.
kevman	0:38ceb79fef03	2274	\return 1 Interrupt status is pending.
kevman	0:38ceb79fef03	2275	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2276	*/
kevman	0:38ceb79fef03	2277	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2278	{
kevman	0:38ceb79fef03	2279	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2280	{
kevman	0:38ceb79fef03	2281	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2282	}
kevman	0:38ceb79fef03	2283	else
kevman	0:38ceb79fef03	2284	{
kevman	0:38ceb79fef03	2285	return(0U);
kevman	0:38ceb79fef03	2286	}
kevman	0:38ceb79fef03	2287	}
kevman	0:38ceb79fef03	2288
kevman	0:38ceb79fef03	2289
kevman	0:38ceb79fef03	2290	/**
kevman	0:38ceb79fef03	2291	\brief Set Pending Interrupt
kevman	0:38ceb79fef03	2292	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
kevman	0:38ceb79fef03	2293	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2294	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2295	*/
kevman	0:38ceb79fef03	2296	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2297	{
kevman	0:38ceb79fef03	2298	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2299	{
kevman	0:38ceb79fef03	2300	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman	0:38ceb79fef03	2301	}
kevman	0:38ceb79fef03	2302	}
kevman	0:38ceb79fef03	2303
kevman	0:38ceb79fef03	2304
kevman	0:38ceb79fef03	2305	/**
kevman	0:38ceb79fef03	2306	\brief Clear Pending Interrupt
kevman	0:38ceb79fef03	2307	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
kevman	0:38ceb79fef03	2308	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2309	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2310	*/
kevman	0:38ceb79fef03	2311	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2312	{
kevman	0:38ceb79fef03	2313	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2314	{
kevman	0:38ceb79fef03	2315	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman	0:38ceb79fef03	2316	}
kevman	0:38ceb79fef03	2317	}
kevman	0:38ceb79fef03	2318
kevman	0:38ceb79fef03	2319
kevman	0:38ceb79fef03	2320	/**
kevman	0:38ceb79fef03	2321	\brief Get Active Interrupt
kevman	0:38ceb79fef03	2322	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
kevman	0:38ceb79fef03	2323	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2324	\return 0 Interrupt status is not active.
kevman	0:38ceb79fef03	2325	\return 1 Interrupt status is active.
kevman	0:38ceb79fef03	2326	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2327	*/
kevman	0:38ceb79fef03	2328	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2329	{
kevman	0:38ceb79fef03	2330	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2331	{
kevman	0:38ceb79fef03	2332	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2333	}
kevman	0:38ceb79fef03	2334	else
kevman	0:38ceb79fef03	2335	{
kevman	0:38ceb79fef03	2336	return(0U);
kevman	0:38ceb79fef03	2337	}
kevman	0:38ceb79fef03	2338	}
kevman	0:38ceb79fef03	2339
kevman	0:38ceb79fef03	2340
kevman	0:38ceb79fef03	2341	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kevman	0:38ceb79fef03	2342	/**
kevman	0:38ceb79fef03	2343	\brief Get Interrupt Target State
kevman	0:38ceb79fef03	2344	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kevman	0:38ceb79fef03	2345	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2346	\return 0 if interrupt is assigned to Secure
kevman	0:38ceb79fef03	2347	\return 1 if interrupt is assigned to Non Secure
kevman	0:38ceb79fef03	2348	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2349	*/
kevman	0:38ceb79fef03	2350	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2351	{
kevman	0:38ceb79fef03	2352	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2353	{
kevman	0:38ceb79fef03	2354	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2355	}
kevman	0:38ceb79fef03	2356	else
kevman	0:38ceb79fef03	2357	{
kevman	0:38ceb79fef03	2358	return(0U);
kevman	0:38ceb79fef03	2359	}
kevman	0:38ceb79fef03	2360	}
kevman	0:38ceb79fef03	2361
kevman	0:38ceb79fef03	2362
kevman	0:38ceb79fef03	2363	/**
kevman	0:38ceb79fef03	2364	\brief Set Interrupt Target State
kevman	0:38ceb79fef03	2365	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kevman	0:38ceb79fef03	2366	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2367	\return 0 if interrupt is assigned to Secure
kevman	0:38ceb79fef03	2368	1 if interrupt is assigned to Non Secure
kevman	0:38ceb79fef03	2369	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2370	*/
kevman	0:38ceb79fef03	2371	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2372	{
kevman	0:38ceb79fef03	2373	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2374	{
kevman	0:38ceb79fef03	2375	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
kevman	0:38ceb79fef03	2376	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2377	}
kevman	0:38ceb79fef03	2378	else
kevman	0:38ceb79fef03	2379	{
kevman	0:38ceb79fef03	2380	return(0U);
kevman	0:38ceb79fef03	2381	}
kevman	0:38ceb79fef03	2382	}
kevman	0:38ceb79fef03	2383
kevman	0:38ceb79fef03	2384
kevman	0:38ceb79fef03	2385	/**
kevman	0:38ceb79fef03	2386	\brief Clear Interrupt Target State
kevman	0:38ceb79fef03	2387	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
kevman	0:38ceb79fef03	2388	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2389	\return 0 if interrupt is assigned to Secure
kevman	0:38ceb79fef03	2390	1 if interrupt is assigned to Non Secure
kevman	0:38ceb79fef03	2391	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2392	*/
kevman	0:38ceb79fef03	2393	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2394	{
kevman	0:38ceb79fef03	2395	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2396	{
kevman	0:38ceb79fef03	2397	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
kevman	0:38ceb79fef03	2398	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2399	}
kevman	0:38ceb79fef03	2400	else
kevman	0:38ceb79fef03	2401	{
kevman	0:38ceb79fef03	2402	return(0U);
kevman	0:38ceb79fef03	2403	}
kevman	0:38ceb79fef03	2404	}
kevman	0:38ceb79fef03	2405	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kevman	0:38ceb79fef03	2406
kevman	0:38ceb79fef03	2407
kevman	0:38ceb79fef03	2408	/**
kevman	0:38ceb79fef03	2409	\brief Set Interrupt Priority
kevman	0:38ceb79fef03	2410	\details Sets the priority of a device specific interrupt or a processor exception.
kevman	0:38ceb79fef03	2411	The interrupt number can be positive to specify a device specific interrupt,
kevman	0:38ceb79fef03	2412	or negative to specify a processor exception.
kevman	0:38ceb79fef03	2413	\param [in] IRQn Interrupt number.
kevman	0:38ceb79fef03	2414	\param [in] priority Priority to set.
kevman	0:38ceb79fef03	2415	\note The priority cannot be set for every processor exception.
kevman	0:38ceb79fef03	2416	*/
kevman	0:38ceb79fef03	2417	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
kevman	0:38ceb79fef03	2418	{
kevman	0:38ceb79fef03	2419	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2420	{
kevman	0:38ceb79fef03	2421	NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kevman	0:38ceb79fef03	2422	}
kevman	0:38ceb79fef03	2423	else
kevman	0:38ceb79fef03	2424	{
kevman	0:38ceb79fef03	2425	SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kevman	0:38ceb79fef03	2426	}
kevman	0:38ceb79fef03	2427	}
kevman	0:38ceb79fef03	2428
kevman	0:38ceb79fef03	2429
kevman	0:38ceb79fef03	2430	/**
kevman	0:38ceb79fef03	2431	\brief Get Interrupt Priority
kevman	0:38ceb79fef03	2432	\details Reads the priority of a device specific interrupt or a processor exception.
kevman	0:38ceb79fef03	2433	The interrupt number can be positive to specify a device specific interrupt,
kevman	0:38ceb79fef03	2434	or negative to specify a processor exception.
kevman	0:38ceb79fef03	2435	\param [in] IRQn Interrupt number.
kevman	0:38ceb79fef03	2436	\return Interrupt Priority.
kevman	0:38ceb79fef03	2437	Value is aligned automatically to the implemented priority bits of the microcontroller.
kevman	0:38ceb79fef03	2438	*/
kevman	0:38ceb79fef03	2439	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2440	{
kevman	0:38ceb79fef03	2441
kevman	0:38ceb79fef03	2442	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2443	{
kevman	0:38ceb79fef03	2444	return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
kevman	0:38ceb79fef03	2445	}
kevman	0:38ceb79fef03	2446	else
kevman	0:38ceb79fef03	2447	{
kevman	0:38ceb79fef03	2448	return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
kevman	0:38ceb79fef03	2449	}
kevman	0:38ceb79fef03	2450	}
kevman	0:38ceb79fef03	2451
kevman	0:38ceb79fef03	2452
kevman	0:38ceb79fef03	2453	/**
kevman	0:38ceb79fef03	2454	\brief Encode Priority
kevman	0:38ceb79fef03	2455	\details Encodes the priority for an interrupt with the given priority group,
kevman	0:38ceb79fef03	2456	preemptive priority value, and subpriority value.
kevman	0:38ceb79fef03	2457	In case of a conflict between priority grouping and available
kevman	0:38ceb79fef03	2458	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kevman	0:38ceb79fef03	2459	\param [in] PriorityGroup Used priority group.
kevman	0:38ceb79fef03	2460	\param [in] PreemptPriority Preemptive priority value (starting from 0).
kevman	0:38ceb79fef03	2461	\param [in] SubPriority Subpriority value (starting from 0).
kevman	0:38ceb79fef03	2462	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
kevman	0:38ceb79fef03	2463	*/
kevman	0:38ceb79fef03	2464	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
kevman	0:38ceb79fef03	2465	{
kevman	0:38ceb79fef03	2466	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kevman	0:38ceb79fef03	2467	uint32_t PreemptPriorityBits;
kevman	0:38ceb79fef03	2468	uint32_t SubPriorityBits;
kevman	0:38ceb79fef03	2469
kevman	0:38ceb79fef03	2470	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kevman	0:38ceb79fef03	2471	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kevman	0:38ceb79fef03	2472
kevman	0:38ceb79fef03	2473	return (
kevman	0:38ceb79fef03	2474	((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) \|
kevman	0:38ceb79fef03	2475	((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
kevman	0:38ceb79fef03	2476	);
kevman	0:38ceb79fef03	2477	}
kevman	0:38ceb79fef03	2478
kevman	0:38ceb79fef03	2479
kevman	0:38ceb79fef03	2480	/**
kevman	0:38ceb79fef03	2481	\brief Decode Priority
kevman	0:38ceb79fef03	2482	\details Decodes an interrupt priority value with a given priority group to
kevman	0:38ceb79fef03	2483	preemptive priority value and subpriority value.
kevman	0:38ceb79fef03	2484	In case of a conflict between priority grouping and available
kevman	0:38ceb79fef03	2485	priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
kevman	0:38ceb79fef03	2486	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
kevman	0:38ceb79fef03	2487	\param [in] PriorityGroup Used priority group.
kevman	0:38ceb79fef03	2488	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
kevman	0:38ceb79fef03	2489	\param [out] pSubPriority Subpriority value (starting from 0).
kevman	0:38ceb79fef03	2490	*/
kevman	0:38ceb79fef03	2491	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
kevman	0:38ceb79fef03	2492	{
kevman	0:38ceb79fef03	2493	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kevman	0:38ceb79fef03	2494	uint32_t PreemptPriorityBits;
kevman	0:38ceb79fef03	2495	uint32_t SubPriorityBits;
kevman	0:38ceb79fef03	2496
kevman	0:38ceb79fef03	2497	PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kevman	0:38ceb79fef03	2498	SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kevman	0:38ceb79fef03	2499
kevman	0:38ceb79fef03	2500	*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
kevman	0:38ceb79fef03	2501	*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
kevman	0:38ceb79fef03	2502	}
kevman	0:38ceb79fef03	2503
kevman	0:38ceb79fef03	2504
kevman	0:38ceb79fef03	2505	/**
kevman	0:38ceb79fef03	2506	\brief Set Interrupt Vector
kevman	0:38ceb79fef03	2507	\details Sets an interrupt vector in SRAM based interrupt vector table.
kevman	0:38ceb79fef03	2508	The interrupt number can be positive to specify a device specific interrupt,
kevman	0:38ceb79fef03	2509	or negative to specify a processor exception.
kevman	0:38ceb79fef03	2510	VTOR must been relocated to SRAM before.
kevman	0:38ceb79fef03	2511	\param [in] IRQn Interrupt number
kevman	0:38ceb79fef03	2512	\param [in] vector Address of interrupt handler function
kevman	0:38ceb79fef03	2513	*/
kevman	0:38ceb79fef03	2514	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
kevman	0:38ceb79fef03	2515	{
kevman	0:38ceb79fef03	2516	uint32_t vectors = (uint32_t )SCB->VTOR;
kevman	0:38ceb79fef03	2517	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
kevman	0:38ceb79fef03	2518	}
kevman	0:38ceb79fef03	2519
kevman	0:38ceb79fef03	2520
kevman	0:38ceb79fef03	2521	/**
kevman	0:38ceb79fef03	2522	\brief Get Interrupt Vector
kevman	0:38ceb79fef03	2523	\details Reads an interrupt vector from interrupt vector table.
kevman	0:38ceb79fef03	2524	The interrupt number can be positive to specify a device specific interrupt,
kevman	0:38ceb79fef03	2525	or negative to specify a processor exception.
kevman	0:38ceb79fef03	2526	\param [in] IRQn Interrupt number.
kevman	0:38ceb79fef03	2527	\return Address of interrupt handler function
kevman	0:38ceb79fef03	2528	*/
kevman	0:38ceb79fef03	2529	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2530	{
kevman	0:38ceb79fef03	2531	uint32_t vectors = (uint32_t )SCB->VTOR;
kevman	0:38ceb79fef03	2532	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
kevman	0:38ceb79fef03	2533	}
kevman	0:38ceb79fef03	2534
kevman	0:38ceb79fef03	2535
kevman	0:38ceb79fef03	2536	/**
kevman	0:38ceb79fef03	2537	\brief System Reset
kevman	0:38ceb79fef03	2538	\details Initiates a system reset request to reset the MCU.
kevman	0:38ceb79fef03	2539	*/
kevman	0:38ceb79fef03	2540	__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
kevman	0:38ceb79fef03	2541	{
kevman	0:38ceb79fef03	2542	__DSB(); /* Ensure all outstanding memory accesses included
kevman	0:38ceb79fef03	2543	buffered write are completed before reset */
kevman	0:38ceb79fef03	2544	SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kevman	0:38ceb79fef03	2545	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
kevman	0:38ceb79fef03	2546	SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
kevman	0:38ceb79fef03	2547	__DSB(); /* Ensure completion of memory access */
kevman	0:38ceb79fef03	2548
kevman	0:38ceb79fef03	2549	for(;;) /* wait until reset */
kevman	0:38ceb79fef03	2550	{
kevman	0:38ceb79fef03	2551	__NOP();
kevman	0:38ceb79fef03	2552	}
kevman	0:38ceb79fef03	2553	}
kevman	0:38ceb79fef03	2554
kevman	0:38ceb79fef03	2555	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kevman	0:38ceb79fef03	2556	/**
kevman	0:38ceb79fef03	2557	\brief Set Priority Grouping (non-secure)
kevman	0:38ceb79fef03	2558	\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
kevman	0:38ceb79fef03	2559	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
kevman	0:38ceb79fef03	2560	Only values from 0..7 are used.
kevman	0:38ceb79fef03	2561	In case of a conflict between priority grouping and available
kevman	0:38ceb79fef03	2562	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kevman	0:38ceb79fef03	2563	\param [in] PriorityGroup Priority grouping field.
kevman	0:38ceb79fef03	2564	*/
kevman	0:38ceb79fef03	2565	__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
kevman	0:38ceb79fef03	2566	{
kevman	0:38ceb79fef03	2567	uint32_t reg_value;
kevman	0:38ceb79fef03	2568	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kevman	0:38ceb79fef03	2569
kevman	0:38ceb79fef03	2570	reg_value = SCB_NS->AIRCR; /* read old register configuration */
kevman	0:38ceb79fef03	2571	reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
kevman	0:38ceb79fef03	2572	reg_value = (reg_value \|
kevman	0:38ceb79fef03	2573	((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
kevman	0:38ceb79fef03	2574	(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
kevman	0:38ceb79fef03	2575	SCB_NS->AIRCR = reg_value;
kevman	0:38ceb79fef03	2576	}
kevman	0:38ceb79fef03	2577
kevman	0:38ceb79fef03	2578
kevman	0:38ceb79fef03	2579	/**
kevman	0:38ceb79fef03	2580	\brief Get Priority Grouping (non-secure)
kevman	0:38ceb79fef03	2581	\details Reads the priority grouping field from the non-secure NVIC when in secure state.
kevman	0:38ceb79fef03	2582	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
kevman	0:38ceb79fef03	2583	*/
kevman	0:38ceb79fef03	2584	__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
kevman	0:38ceb79fef03	2585	{
kevman	0:38ceb79fef03	2586	return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
kevman	0:38ceb79fef03	2587	}
kevman	0:38ceb79fef03	2588
kevman	0:38ceb79fef03	2589
kevman	0:38ceb79fef03	2590	/**
kevman	0:38ceb79fef03	2591	\brief Enable Interrupt (non-secure)
kevman	0:38ceb79fef03	2592	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
kevman	0:38ceb79fef03	2593	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2594	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2595	*/
kevman	0:38ceb79fef03	2596	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2597	{
kevman	0:38ceb79fef03	2598	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2599	{
kevman	0:38ceb79fef03	2600	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman	0:38ceb79fef03	2601	}
kevman	0:38ceb79fef03	2602	}
kevman	0:38ceb79fef03	2603
kevman	0:38ceb79fef03	2604
kevman	0:38ceb79fef03	2605	/**
kevman	0:38ceb79fef03	2606	\brief Get Interrupt Enable status (non-secure)
kevman	0:38ceb79fef03	2607	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
kevman	0:38ceb79fef03	2608	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2609	\return 0 Interrupt is not enabled.
kevman	0:38ceb79fef03	2610	\return 1 Interrupt is enabled.
kevman	0:38ceb79fef03	2611	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2612	*/
kevman	0:38ceb79fef03	2613	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2614	{
kevman	0:38ceb79fef03	2615	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2616	{
kevman	0:38ceb79fef03	2617	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2618	}
kevman	0:38ceb79fef03	2619	else
kevman	0:38ceb79fef03	2620	{
kevman	0:38ceb79fef03	2621	return(0U);
kevman	0:38ceb79fef03	2622	}
kevman	0:38ceb79fef03	2623	}
kevman	0:38ceb79fef03	2624
kevman	0:38ceb79fef03	2625
kevman	0:38ceb79fef03	2626	/**
kevman	0:38ceb79fef03	2627	\brief Disable Interrupt (non-secure)
kevman	0:38ceb79fef03	2628	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
kevman	0:38ceb79fef03	2629	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2630	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2631	*/
kevman	0:38ceb79fef03	2632	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2633	{
kevman	0:38ceb79fef03	2634	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2635	{
kevman	0:38ceb79fef03	2636	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman	0:38ceb79fef03	2637	}
kevman	0:38ceb79fef03	2638	}
kevman	0:38ceb79fef03	2639
kevman	0:38ceb79fef03	2640
kevman	0:38ceb79fef03	2641	/**
kevman	0:38ceb79fef03	2642	\brief Get Pending Interrupt (non-secure)
kevman	0:38ceb79fef03	2643	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
kevman	0:38ceb79fef03	2644	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2645	\return 0 Interrupt status is not pending.
kevman	0:38ceb79fef03	2646	\return 1 Interrupt status is pending.
kevman	0:38ceb79fef03	2647	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2648	*/
kevman	0:38ceb79fef03	2649	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2650	{
kevman	0:38ceb79fef03	2651	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2652	{
kevman	0:38ceb79fef03	2653	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2654	}
kevman	0:38ceb79fef03	2655	else
kevman	0:38ceb79fef03	2656	{
kevman	0:38ceb79fef03	2657	return(0U);
kevman	0:38ceb79fef03	2658	}
kevman	0:38ceb79fef03	2659	}
kevman	0:38ceb79fef03	2660
kevman	0:38ceb79fef03	2661
kevman	0:38ceb79fef03	2662	/**
kevman	0:38ceb79fef03	2663	\brief Set Pending Interrupt (non-secure)
kevman	0:38ceb79fef03	2664	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
kevman	0:38ceb79fef03	2665	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2666	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2667	*/
kevman	0:38ceb79fef03	2668	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2669	{
kevman	0:38ceb79fef03	2670	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2671	{
kevman	0:38ceb79fef03	2672	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman	0:38ceb79fef03	2673	}
kevman	0:38ceb79fef03	2674	}
kevman	0:38ceb79fef03	2675
kevman	0:38ceb79fef03	2676
kevman	0:38ceb79fef03	2677	/**
kevman	0:38ceb79fef03	2678	\brief Clear Pending Interrupt (non-secure)
kevman	0:38ceb79fef03	2679	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
kevman	0:38ceb79fef03	2680	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2681	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2682	*/
kevman	0:38ceb79fef03	2683	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2684	{
kevman	0:38ceb79fef03	2685	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2686	{
kevman	0:38ceb79fef03	2687	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman	0:38ceb79fef03	2688	}
kevman	0:38ceb79fef03	2689	}
kevman	0:38ceb79fef03	2690
kevman	0:38ceb79fef03	2691
kevman	0:38ceb79fef03	2692	/**
kevman	0:38ceb79fef03	2693	\brief Get Active Interrupt (non-secure)
kevman	0:38ceb79fef03	2694	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
kevman	0:38ceb79fef03	2695	\param [in] IRQn Device specific interrupt number.
kevman	0:38ceb79fef03	2696	\return 0 Interrupt status is not active.
kevman	0:38ceb79fef03	2697	\return 1 Interrupt status is active.
kevman	0:38ceb79fef03	2698	\note IRQn must not be negative.
kevman	0:38ceb79fef03	2699	*/
kevman	0:38ceb79fef03	2700	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2701	{
kevman	0:38ceb79fef03	2702	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2703	{
kevman	0:38ceb79fef03	2704	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman	0:38ceb79fef03	2705	}
kevman	0:38ceb79fef03	2706	else
kevman	0:38ceb79fef03	2707	{
kevman	0:38ceb79fef03	2708	return(0U);
kevman	0:38ceb79fef03	2709	}
kevman	0:38ceb79fef03	2710	}
kevman	0:38ceb79fef03	2711
kevman	0:38ceb79fef03	2712
kevman	0:38ceb79fef03	2713	/**
kevman	0:38ceb79fef03	2714	\brief Set Interrupt Priority (non-secure)
kevman	0:38ceb79fef03	2715	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
kevman	0:38ceb79fef03	2716	The interrupt number can be positive to specify a device specific interrupt,
kevman	0:38ceb79fef03	2717	or negative to specify a processor exception.
kevman	0:38ceb79fef03	2718	\param [in] IRQn Interrupt number.
kevman	0:38ceb79fef03	2719	\param [in] priority Priority to set.
kevman	0:38ceb79fef03	2720	\note The priority cannot be set for every non-secure processor exception.
kevman	0:38ceb79fef03	2721	*/
kevman	0:38ceb79fef03	2722	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
kevman	0:38ceb79fef03	2723	{
kevman	0:38ceb79fef03	2724	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2725	{
kevman	0:38ceb79fef03	2726	NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kevman	0:38ceb79fef03	2727	}
kevman	0:38ceb79fef03	2728	else
kevman	0:38ceb79fef03	2729	{
kevman	0:38ceb79fef03	2730	SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kevman	0:38ceb79fef03	2731	}
kevman	0:38ceb79fef03	2732	}
kevman	0:38ceb79fef03	2733
kevman	0:38ceb79fef03	2734
kevman	0:38ceb79fef03	2735	/**
kevman	0:38ceb79fef03	2736	\brief Get Interrupt Priority (non-secure)
kevman	0:38ceb79fef03	2737	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
kevman	0:38ceb79fef03	2738	The interrupt number can be positive to specify a device specific interrupt,
kevman	0:38ceb79fef03	2739	or negative to specify a processor exception.
kevman	0:38ceb79fef03	2740	\param [in] IRQn Interrupt number.
kevman	0:38ceb79fef03	2741	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
kevman	0:38ceb79fef03	2742	*/
kevman	0:38ceb79fef03	2743	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
kevman	0:38ceb79fef03	2744	{
kevman	0:38ceb79fef03	2745
kevman	0:38ceb79fef03	2746	if ((int32_t)(IRQn) >= 0)
kevman	0:38ceb79fef03	2747	{
kevman	0:38ceb79fef03	2748	return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
kevman	0:38ceb79fef03	2749	}
kevman	0:38ceb79fef03	2750	else
kevman	0:38ceb79fef03	2751	{
kevman	0:38ceb79fef03	2752	return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
kevman	0:38ceb79fef03	2753	}
kevman	0:38ceb79fef03	2754	}
kevman	0:38ceb79fef03	2755	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
kevman	0:38ceb79fef03	2756
kevman	0:38ceb79fef03	2757	/@} end of CMSIS_Core_NVICFunctions /
kevman	0:38ceb79fef03	2758
kevman	0:38ceb79fef03	2759	/* ########################## MPU functions #################################### */
kevman	0:38ceb79fef03	2760
kevman	0:38ceb79fef03	2761	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman	0:38ceb79fef03	2762
kevman	0:38ceb79fef03	2763	#include "mpu_armv8.h"
kevman	0:38ceb79fef03	2764
kevman	0:38ceb79fef03	2765	#endif
kevman	0:38ceb79fef03	2766
kevman	0:38ceb79fef03	2767	/* ########################## FPU functions #################################### */
kevman	0:38ceb79fef03	2768	/**
kevman	0:38ceb79fef03	2769	\ingroup CMSIS_Core_FunctionInterface
kevman	0:38ceb79fef03	2770	\defgroup CMSIS_Core_FpuFunctions FPU Functions
kevman	0:38ceb79fef03	2771	\brief Function that provides FPU type.
kevman	0:38ceb79fef03	2772	@{
kevman	0:38ceb79fef03	2773	*/
kevman	0:38ceb79fef03	2774
kevman	0:38ceb79fef03	2775	/**
kevman	0:38ceb79fef03	2776	\brief get FPU type
kevman	0:38ceb79fef03	2777	\details returns the FPU type
kevman	0:38ceb79fef03	2778	\returns
kevman	0:38ceb79fef03	2779	- \b 0: No FPU
kevman	0:38ceb79fef03	2780	- \b 1: Single precision FPU
kevman	0:38ceb79fef03	2781	- \b 2: Double + Single precision FPU
kevman	0:38ceb79fef03	2782	*/
kevman	0:38ceb79fef03	2783	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
kevman	0:38ceb79fef03	2784	{
kevman	0:38ceb79fef03	2785	uint32_t mvfr0;
kevman	0:38ceb79fef03	2786
kevman	0:38ceb79fef03	2787	mvfr0 = FPU->MVFR0;
kevman	0:38ceb79fef03	2788	if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x220U)
kevman	0:38ceb79fef03	2789	{
kevman	0:38ceb79fef03	2790	return 2U; /* Double + Single precision FPU */
kevman	0:38ceb79fef03	2791	}
kevman	0:38ceb79fef03	2792	else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk \| FPU_MVFR0_Double_precision_Msk)) == 0x020U)
kevman	0:38ceb79fef03	2793	{
kevman	0:38ceb79fef03	2794	return 1U; /* Single precision FPU */
kevman	0:38ceb79fef03	2795	}
kevman	0:38ceb79fef03	2796	else
kevman	0:38ceb79fef03	2797	{
kevman	0:38ceb79fef03	2798	return 0U; /* No FPU */
kevman	0:38ceb79fef03	2799	}
kevman	0:38ceb79fef03	2800	}
kevman	0:38ceb79fef03	2801
kevman	0:38ceb79fef03	2802
kevman	0:38ceb79fef03	2803	/@} end of CMSIS_Core_FpuFunctions /
kevman	0:38ceb79fef03	2804
kevman	0:38ceb79fef03	2805
kevman	0:38ceb79fef03	2806
kevman	0:38ceb79fef03	2807	/* ########################## SAU functions #################################### */
kevman	0:38ceb79fef03	2808	/**
kevman	0:38ceb79fef03	2809	\ingroup CMSIS_Core_FunctionInterface
kevman	0:38ceb79fef03	2810	\defgroup CMSIS_Core_SAUFunctions SAU Functions
kevman	0:38ceb79fef03	2811	\brief Functions that configure the SAU.
kevman	0:38ceb79fef03	2812	@{
kevman	0:38ceb79fef03	2813	*/
kevman	0:38ceb79fef03	2814
kevman	0:38ceb79fef03	2815	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kevman	0:38ceb79fef03	2816
kevman	0:38ceb79fef03	2817	/**
kevman	0:38ceb79fef03	2818	\brief Enable SAU
kevman	0:38ceb79fef03	2819	\details Enables the Security Attribution Unit (SAU).
kevman	0:38ceb79fef03	2820	*/
kevman	0:38ceb79fef03	2821	__STATIC_INLINE void TZ_SAU_Enable(void)
kevman	0:38ceb79fef03	2822	{
kevman	0:38ceb79fef03	2823	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
kevman	0:38ceb79fef03	2824	}
kevman	0:38ceb79fef03	2825
kevman	0:38ceb79fef03	2826
kevman	0:38ceb79fef03	2827
kevman	0:38ceb79fef03	2828	/**
kevman	0:38ceb79fef03	2829	\brief Disable SAU
kevman	0:38ceb79fef03	2830	\details Disables the Security Attribution Unit (SAU).
kevman	0:38ceb79fef03	2831	*/
kevman	0:38ceb79fef03	2832	__STATIC_INLINE void TZ_SAU_Disable(void)
kevman	0:38ceb79fef03	2833	{
kevman	0:38ceb79fef03	2834	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
kevman	0:38ceb79fef03	2835	}
kevman	0:38ceb79fef03	2836
kevman	0:38ceb79fef03	2837	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kevman	0:38ceb79fef03	2838
kevman	0:38ceb79fef03	2839	/@} end of CMSIS_Core_SAUFunctions /
kevman	0:38ceb79fef03	2840
kevman	0:38ceb79fef03	2841
kevman	0:38ceb79fef03	2842
kevman	0:38ceb79fef03	2843
kevman	0:38ceb79fef03	2844	/* ################################## SysTick function ############################################ */
kevman	0:38ceb79fef03	2845	/**
kevman	0:38ceb79fef03	2846	\ingroup CMSIS_Core_FunctionInterface
kevman	0:38ceb79fef03	2847	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
kevman	0:38ceb79fef03	2848	\brief Functions that configure the System.
kevman	0:38ceb79fef03	2849	@{
kevman	0:38ceb79fef03	2850	*/
kevman	0:38ceb79fef03	2851
kevman	0:38ceb79fef03	2852	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
kevman	0:38ceb79fef03	2853
kevman	0:38ceb79fef03	2854	/**
kevman	0:38ceb79fef03	2855	\brief System Tick Configuration
kevman	0:38ceb79fef03	2856	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
kevman	0:38ceb79fef03	2857	Counter is in free running mode to generate periodic interrupts.
kevman	0:38ceb79fef03	2858	\param [in] ticks Number of ticks between two interrupts.
kevman	0:38ceb79fef03	2859	\return 0 Function succeeded.
kevman	0:38ceb79fef03	2860	\return 1 Function failed.
kevman	0:38ceb79fef03	2861	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kevman	0:38ceb79fef03	2862	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
kevman	0:38ceb79fef03	2863	must contain a vendor-specific implementation of this function.
kevman	0:38ceb79fef03	2864	*/
kevman	0:38ceb79fef03	2865	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
kevman	0:38ceb79fef03	2866	{
kevman	0:38ceb79fef03	2867	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kevman	0:38ceb79fef03	2868	{
kevman	0:38ceb79fef03	2869	return (1UL); /* Reload value impossible */
kevman	0:38ceb79fef03	2870	}
kevman	0:38ceb79fef03	2871
kevman	0:38ceb79fef03	2872	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kevman	0:38ceb79fef03	2873	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kevman	0:38ceb79fef03	2874	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
kevman	0:38ceb79fef03	2875	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
kevman	0:38ceb79fef03	2876	SysTick_CTRL_TICKINT_Msk \|
kevman	0:38ceb79fef03	2877	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kevman	0:38ceb79fef03	2878	return (0UL); /* Function successful */
kevman	0:38ceb79fef03	2879	}
kevman	0:38ceb79fef03	2880
kevman	0:38ceb79fef03	2881	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
kevman	0:38ceb79fef03	2882	/**
kevman	0:38ceb79fef03	2883	\brief System Tick Configuration (non-secure)
kevman	0:38ceb79fef03	2884	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
kevman	0:38ceb79fef03	2885	Counter is in free running mode to generate periodic interrupts.
kevman	0:38ceb79fef03	2886	\param [in] ticks Number of ticks between two interrupts.
kevman	0:38ceb79fef03	2887	\return 0 Function succeeded.
kevman	0:38ceb79fef03	2888	\return 1 Function failed.
kevman	0:38ceb79fef03	2889	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kevman	0:38ceb79fef03	2890	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
kevman	0:38ceb79fef03	2891	must contain a vendor-specific implementation of this function.
kevman	0:38ceb79fef03	2892
kevman	0:38ceb79fef03	2893	*/
kevman	0:38ceb79fef03	2894	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
kevman	0:38ceb79fef03	2895	{
kevman	0:38ceb79fef03	2896	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kevman	0:38ceb79fef03	2897	{
kevman	0:38ceb79fef03	2898	return (1UL); /* Reload value impossible */
kevman	0:38ceb79fef03	2899	}
kevman	0:38ceb79fef03	2900
kevman	0:38ceb79fef03	2901	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kevman	0:38ceb79fef03	2902	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kevman	0:38ceb79fef03	2903	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
kevman	0:38ceb79fef03	2904	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
kevman	0:38ceb79fef03	2905	SysTick_CTRL_TICKINT_Msk \|
kevman	0:38ceb79fef03	2906	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kevman	0:38ceb79fef03	2907	return (0UL); /* Function successful */
kevman	0:38ceb79fef03	2908	}
kevman	0:38ceb79fef03	2909	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
kevman	0:38ceb79fef03	2910
kevman	0:38ceb79fef03	2911	#endif
kevman	0:38ceb79fef03	2912
kevman	0:38ceb79fef03	2913	/@} end of CMSIS_Core_SysTickFunctions /
kevman	0:38ceb79fef03	2914
kevman	0:38ceb79fef03	2915
kevman	0:38ceb79fef03	2916
kevman	0:38ceb79fef03	2917	/* ##################################### Debug In/Output function ########################################### */
kevman	0:38ceb79fef03	2918	/**
kevman	0:38ceb79fef03	2919	\ingroup CMSIS_Core_FunctionInterface
kevman	0:38ceb79fef03	2920	\defgroup CMSIS_core_DebugFunctions ITM Functions
kevman	0:38ceb79fef03	2921	\brief Functions that access the ITM debug interface.
kevman	0:38ceb79fef03	2922	@{
kevman	0:38ceb79fef03	2923	*/
kevman	0:38ceb79fef03	2924
kevman	0:38ceb79fef03	2925	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
kevman	0:38ceb79fef03	2926	#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
kevman	0:38ceb79fef03	2927
kevman	0:38ceb79fef03	2928
kevman	0:38ceb79fef03	2929	/**
kevman	0:38ceb79fef03	2930	\brief ITM Send Character
kevman	0:38ceb79fef03	2931	\details Transmits a character via the ITM channel 0, and
kevman	0:38ceb79fef03	2932	\li Just returns when no debugger is connected that has booked the output.
kevman	0:38ceb79fef03	2933	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
kevman	0:38ceb79fef03	2934	\param [in] ch Character to transmit.
kevman	0:38ceb79fef03	2935	\returns Character to transmit.
kevman	0:38ceb79fef03	2936	*/
kevman	0:38ceb79fef03	2937	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
kevman	0:38ceb79fef03	2938	{
kevman	0:38ceb79fef03	2939	if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
kevman	0:38ceb79fef03	2940	((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
kevman	0:38ceb79fef03	2941	{
kevman	0:38ceb79fef03	2942	while (ITM->PORT[0U].u32 == 0UL)
kevman	0:38ceb79fef03	2943	{
kevman	0:38ceb79fef03	2944	__NOP();
kevman	0:38ceb79fef03	2945	}
kevman	0:38ceb79fef03	2946	ITM->PORT[0U].u8 = (uint8_t)ch;
kevman	0:38ceb79fef03	2947	}
kevman	0:38ceb79fef03	2948	return (ch);
kevman	0:38ceb79fef03	2949	}
kevman	0:38ceb79fef03	2950
kevman	0:38ceb79fef03	2951
kevman	0:38ceb79fef03	2952	/**
kevman	0:38ceb79fef03	2953	\brief ITM Receive Character
kevman	0:38ceb79fef03	2954	\details Inputs a character via the external variable \ref ITM_RxBuffer.
kevman	0:38ceb79fef03	2955	\return Received character.
kevman	0:38ceb79fef03	2956	\return -1 No character pending.
kevman	0:38ceb79fef03	2957	*/
kevman	0:38ceb79fef03	2958	__STATIC_INLINE int32_t ITM_ReceiveChar (void)
kevman	0:38ceb79fef03	2959	{
kevman	0:38ceb79fef03	2960	int32_t ch = -1; /* no character available */
kevman	0:38ceb79fef03	2961
kevman	0:38ceb79fef03	2962	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
kevman	0:38ceb79fef03	2963	{
kevman	0:38ceb79fef03	2964	ch = ITM_RxBuffer;
kevman	0:38ceb79fef03	2965	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
kevman	0:38ceb79fef03	2966	}
kevman	0:38ceb79fef03	2967
kevman	0:38ceb79fef03	2968	return (ch);
kevman	0:38ceb79fef03	2969	}
kevman	0:38ceb79fef03	2970
kevman	0:38ceb79fef03	2971
kevman	0:38ceb79fef03	2972	/**
kevman	0:38ceb79fef03	2973	\brief ITM Check Character
kevman	0:38ceb79fef03	2974	\details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
kevman	0:38ceb79fef03	2975	\return 0 No character available.
kevman	0:38ceb79fef03	2976	\return 1 Character available.
kevman	0:38ceb79fef03	2977	*/
kevman	0:38ceb79fef03	2978	__STATIC_INLINE int32_t ITM_CheckChar (void)
kevman	0:38ceb79fef03	2979	{
kevman	0:38ceb79fef03	2980
kevman	0:38ceb79fef03	2981	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
kevman	0:38ceb79fef03	2982	{
kevman	0:38ceb79fef03	2983	return (0); /* no character available */
kevman	0:38ceb79fef03	2984	}
kevman	0:38ceb79fef03	2985	else
kevman	0:38ceb79fef03	2986	{
kevman	0:38ceb79fef03	2987	return (1); /* character available */
kevman	0:38ceb79fef03	2988	}
kevman	0:38ceb79fef03	2989	}
kevman	0:38ceb79fef03	2990
kevman	0:38ceb79fef03	2991	/@} end of CMSIS_core_DebugFunctions /
kevman	0:38ceb79fef03	2992
kevman	0:38ceb79fef03	2993
kevman	0:38ceb79fef03	2994
kevman	0:38ceb79fef03	2995
kevman	0:38ceb79fef03	2996	#ifdef __cplusplus
kevman	0:38ceb79fef03	2997	}
kevman	0:38ceb79fef03	2998	#endif
kevman	0:38ceb79fef03	2999
kevman	0:38ceb79fef03	3000	#endif /* __CORE_CM33_H_DEPENDANT */
kevman	0:38ceb79fef03	3001
kevman	0:38ceb79fef03	3002	#endif /* __CMSIS_GENERIC */

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Type:	Library
Created:	30 Oct 2019
Imports:	1
Forks:	0
Commits:	3
Dependents:	0
Dependencies:	0
Followers:	1

This repository is Public (Unlisted).

cmsis/TARGET_CORTEX_M/core_cm33.h@2:7aab896b1a3b, 2019-03-13 (annotated)

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