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cmsis/TARGET_CORTEX_M/core_sc000.h@0:38ceb79fef03, 2018-11-28 (annotated)

Committer:
kevman
Date:
Wed Nov 28 15:10:15 2018 +0000
Revision:
0:38ceb79fef03
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kevman 0:38ceb79fef03 1 /**************************************************************************//**
kevman 0:38ceb79fef03 2 * @file core_sc000.h
kevman 0:38ceb79fef03 3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
kevman 0:38ceb79fef03 4 * @version V5.0.5
kevman 0:38ceb79fef03 5 * @date 28. May 2018
kevman 0:38ceb79fef03 6 ******************************************************************************/
kevman 0:38ceb79fef03 7 /*
kevman 0:38ceb79fef03 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
kevman 0:38ceb79fef03 9 *
kevman 0:38ceb79fef03 10 * SPDX-License-Identifier: Apache-2.0
kevman 0:38ceb79fef03 11 *
kevman 0:38ceb79fef03 12 * Licensed under the Apache License, Version 2.0 (the License); you may
kevman 0:38ceb79fef03 13 * not use this file except in compliance with the License.
kevman 0:38ceb79fef03 14 * You may obtain a copy of the License at
kevman 0:38ceb79fef03 15 *
kevman 0:38ceb79fef03 16 * www.apache.org/licenses/LICENSE-2.0
kevman 0:38ceb79fef03 17 *
kevman 0:38ceb79fef03 18 * Unless required by applicable law or agreed to in writing, software
kevman 0:38ceb79fef03 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
kevman 0:38ceb79fef03 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kevman 0:38ceb79fef03 21 * See the License for the specific language governing permissions and
kevman 0:38ceb79fef03 22 * limitations under the License.
kevman 0:38ceb79fef03 23 */
kevman 0:38ceb79fef03 24
kevman 0:38ceb79fef03 25 #if defined ( __ICCARM__ )
kevman 0:38ceb79fef03 26 #pragma system_include /* treat file as system include file for MISRA check */
kevman 0:38ceb79fef03 27 #elif defined (__clang__)
kevman 0:38ceb79fef03 28 #pragma clang system_header /* treat file as system include file */
kevman 0:38ceb79fef03 29 #endif
kevman 0:38ceb79fef03 30
kevman 0:38ceb79fef03 31 #ifndef __CORE_SC000_H_GENERIC
kevman 0:38ceb79fef03 32 #define __CORE_SC000_H_GENERIC
kevman 0:38ceb79fef03 33
kevman 0:38ceb79fef03 34 #include <stdint.h>
kevman 0:38ceb79fef03 35
kevman 0:38ceb79fef03 36 #ifdef __cplusplus
kevman 0:38ceb79fef03 37 extern "C" {
kevman 0:38ceb79fef03 38 #endif
kevman 0:38ceb79fef03 39
kevman 0:38ceb79fef03 40 /**
kevman 0:38ceb79fef03 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
kevman 0:38ceb79fef03 42 CMSIS violates the following MISRA-C:2004 rules:
kevman 0:38ceb79fef03 43
kevman 0:38ceb79fef03 44 \li Required Rule 8.5, object/function definition in header file.<br>
kevman 0:38ceb79fef03 45 Function definitions in header files are used to allow 'inlining'.
kevman 0:38ceb79fef03 46
kevman 0:38ceb79fef03 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
kevman 0:38ceb79fef03 48 Unions are used for effective representation of core registers.
kevman 0:38ceb79fef03 49
kevman 0:38ceb79fef03 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
kevman 0:38ceb79fef03 51 Function-like macros are used to allow more efficient code.
kevman 0:38ceb79fef03 52 */
kevman 0:38ceb79fef03 53
kevman 0:38ceb79fef03 54
kevman 0:38ceb79fef03 55 /*******************************************************************************
kevman 0:38ceb79fef03 56 * CMSIS definitions
kevman 0:38ceb79fef03 57 ******************************************************************************/
kevman 0:38ceb79fef03 58 /**
kevman 0:38ceb79fef03 59 \ingroup SC000
kevman 0:38ceb79fef03 60 @{
kevman 0:38ceb79fef03 61 */
kevman 0:38ceb79fef03 62
kevman 0:38ceb79fef03 63 #include "cmsis_version.h"
kevman 0:38ceb79fef03 64
kevman 0:38ceb79fef03 65 /* CMSIS SC000 definitions */
kevman 0:38ceb79fef03 66 #define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
kevman 0:38ceb79fef03 67 #define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
kevman 0:38ceb79fef03 68 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
kevman 0:38ceb79fef03 69 __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
kevman 0:38ceb79fef03 70
kevman 0:38ceb79fef03 71 #define __CORTEX_SC (000U) /*!< Cortex secure core */
kevman 0:38ceb79fef03 72
kevman 0:38ceb79fef03 73 /** __FPU_USED indicates whether an FPU is used or not.
kevman 0:38ceb79fef03 74 This core does not support an FPU at all
kevman 0:38ceb79fef03 75 */
kevman 0:38ceb79fef03 76 #define __FPU_USED 0U
kevman 0:38ceb79fef03 77
kevman 0:38ceb79fef03 78 #if defined ( __CC_ARM )
kevman 0:38ceb79fef03 79 #if defined __TARGET_FPU_VFP
kevman 0:38ceb79fef03 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 81 #endif
kevman 0:38ceb79fef03 82
kevman 0:38ceb79fef03 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
kevman 0:38ceb79fef03 84 #if defined __ARM_PCS_VFP
kevman 0:38ceb79fef03 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 86 #endif
kevman 0:38ceb79fef03 87
kevman 0:38ceb79fef03 88 #elif defined ( __GNUC__ )
kevman 0:38ceb79fef03 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
kevman 0:38ceb79fef03 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 91 #endif
kevman 0:38ceb79fef03 92
kevman 0:38ceb79fef03 93 #elif defined ( __ICCARM__ )
kevman 0:38ceb79fef03 94 #if defined __ARMVFP__
kevman 0:38ceb79fef03 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 96 #endif
kevman 0:38ceb79fef03 97
kevman 0:38ceb79fef03 98 #elif defined ( __TI_ARM__ )
kevman 0:38ceb79fef03 99 #if defined __TI_VFP_SUPPORT__
kevman 0:38ceb79fef03 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 101 #endif
kevman 0:38ceb79fef03 102
kevman 0:38ceb79fef03 103 #elif defined ( __TASKING__ )
kevman 0:38ceb79fef03 104 #if defined __FPU_VFP__
kevman 0:38ceb79fef03 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 106 #endif
kevman 0:38ceb79fef03 107
kevman 0:38ceb79fef03 108 #elif defined ( __CSMC__ )
kevman 0:38ceb79fef03 109 #if ( __CSMC__ & 0x400U)
kevman 0:38ceb79fef03 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 111 #endif
kevman 0:38ceb79fef03 112
kevman 0:38ceb79fef03 113 #endif
kevman 0:38ceb79fef03 114
kevman 0:38ceb79fef03 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
kevman 0:38ceb79fef03 116
kevman 0:38ceb79fef03 117
kevman 0:38ceb79fef03 118 #ifdef __cplusplus
kevman 0:38ceb79fef03 119 }
kevman 0:38ceb79fef03 120 #endif
kevman 0:38ceb79fef03 121
kevman 0:38ceb79fef03 122 #endif /* __CORE_SC000_H_GENERIC */
kevman 0:38ceb79fef03 123
kevman 0:38ceb79fef03 124 #ifndef __CMSIS_GENERIC
kevman 0:38ceb79fef03 125
kevman 0:38ceb79fef03 126 #ifndef __CORE_SC000_H_DEPENDANT
kevman 0:38ceb79fef03 127 #define __CORE_SC000_H_DEPENDANT
kevman 0:38ceb79fef03 128
kevman 0:38ceb79fef03 129 #ifdef __cplusplus
kevman 0:38ceb79fef03 130 extern "C" {
kevman 0:38ceb79fef03 131 #endif
kevman 0:38ceb79fef03 132
kevman 0:38ceb79fef03 133 /* check device defines and use defaults */
kevman 0:38ceb79fef03 134 #if defined __CHECK_DEVICE_DEFINES
kevman 0:38ceb79fef03 135 #ifndef __SC000_REV
kevman 0:38ceb79fef03 136 #define __SC000_REV 0x0000U
kevman 0:38ceb79fef03 137 #warning "__SC000_REV not defined in device header file; using default!"
kevman 0:38ceb79fef03 138 #endif
kevman 0:38ceb79fef03 139
kevman 0:38ceb79fef03 140 #ifndef __MPU_PRESENT
kevman 0:38ceb79fef03 141 #define __MPU_PRESENT 0U
kevman 0:38ceb79fef03 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
kevman 0:38ceb79fef03 143 #endif
kevman 0:38ceb79fef03 144
kevman 0:38ceb79fef03 145 #ifndef __NVIC_PRIO_BITS
kevman 0:38ceb79fef03 146 #define __NVIC_PRIO_BITS 2U
kevman 0:38ceb79fef03 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
kevman 0:38ceb79fef03 148 #endif
kevman 0:38ceb79fef03 149
kevman 0:38ceb79fef03 150 #ifndef __Vendor_SysTickConfig
kevman 0:38ceb79fef03 151 #define __Vendor_SysTickConfig 0U
kevman 0:38ceb79fef03 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
kevman 0:38ceb79fef03 153 #endif
kevman 0:38ceb79fef03 154 #endif
kevman 0:38ceb79fef03 155
kevman 0:38ceb79fef03 156 /* IO definitions (access restrictions to peripheral registers) */
kevman 0:38ceb79fef03 157 /**
kevman 0:38ceb79fef03 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
kevman 0:38ceb79fef03 159
kevman 0:38ceb79fef03 160 <strong>IO Type Qualifiers</strong> are used
kevman 0:38ceb79fef03 161 \li to specify the access to peripheral variables.
kevman 0:38ceb79fef03 162 \li for automatic generation of peripheral register debug information.
kevman 0:38ceb79fef03 163 */
kevman 0:38ceb79fef03 164 #ifdef __cplusplus
kevman 0:38ceb79fef03 165 #define __I volatile /*!< Defines 'read only' permissions */
kevman 0:38ceb79fef03 166 #else
kevman 0:38ceb79fef03 167 #define __I volatile const /*!< Defines 'read only' permissions */
kevman 0:38ceb79fef03 168 #endif
kevman 0:38ceb79fef03 169 #define __O volatile /*!< Defines 'write only' permissions */
kevman 0:38ceb79fef03 170 #define __IO volatile /*!< Defines 'read / write' permissions */
kevman 0:38ceb79fef03 171
kevman 0:38ceb79fef03 172 /* following defines should be used for structure members */
kevman 0:38ceb79fef03 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
kevman 0:38ceb79fef03 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
kevman 0:38ceb79fef03 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
kevman 0:38ceb79fef03 176
kevman 0:38ceb79fef03 177 /*@} end of group SC000 */
kevman 0:38ceb79fef03 178
kevman 0:38ceb79fef03 179
kevman 0:38ceb79fef03 180
kevman 0:38ceb79fef03 181 /*******************************************************************************
kevman 0:38ceb79fef03 182 * Register Abstraction
kevman 0:38ceb79fef03 183 Core Register contain:
kevman 0:38ceb79fef03 184 - Core Register
kevman 0:38ceb79fef03 185 - Core NVIC Register
kevman 0:38ceb79fef03 186 - Core SCB Register
kevman 0:38ceb79fef03 187 - Core SysTick Register
kevman 0:38ceb79fef03 188 - Core MPU Register
kevman 0:38ceb79fef03 189 ******************************************************************************/
kevman 0:38ceb79fef03 190 /**
kevman 0:38ceb79fef03 191 \defgroup CMSIS_core_register Defines and Type Definitions
kevman 0:38ceb79fef03 192 \brief Type definitions and defines for Cortex-M processor based devices.
kevman 0:38ceb79fef03 193 */
kevman 0:38ceb79fef03 194
kevman 0:38ceb79fef03 195 /**
kevman 0:38ceb79fef03 196 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 197 \defgroup CMSIS_CORE Status and Control Registers
kevman 0:38ceb79fef03 198 \brief Core Register type definitions.
kevman 0:38ceb79fef03 199 @{
kevman 0:38ceb79fef03 200 */
kevman 0:38ceb79fef03 201
kevman 0:38ceb79fef03 202 /**
kevman 0:38ceb79fef03 203 \brief Union type to access the Application Program Status Register (APSR).
kevman 0:38ceb79fef03 204 */
kevman 0:38ceb79fef03 205 typedef union
kevman 0:38ceb79fef03 206 {
kevman 0:38ceb79fef03 207 struct
kevman 0:38ceb79fef03 208 {
kevman 0:38ceb79fef03 209 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
kevman 0:38ceb79fef03 210 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
kevman 0:38ceb79fef03 211 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
kevman 0:38ceb79fef03 212 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
kevman 0:38ceb79fef03 213 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
kevman 0:38ceb79fef03 214 } b; /*!< Structure used for bit access */
kevman 0:38ceb79fef03 215 uint32_t w; /*!< Type used for word access */
kevman 0:38ceb79fef03 216 } APSR_Type;
kevman 0:38ceb79fef03 217
kevman 0:38ceb79fef03 218 /* APSR Register Definitions */
kevman 0:38ceb79fef03 219 #define APSR_N_Pos 31U /*!< APSR: N Position */
kevman 0:38ceb79fef03 220 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
kevman 0:38ceb79fef03 221
kevman 0:38ceb79fef03 222 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
kevman 0:38ceb79fef03 223 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
kevman 0:38ceb79fef03 224
kevman 0:38ceb79fef03 225 #define APSR_C_Pos 29U /*!< APSR: C Position */
kevman 0:38ceb79fef03 226 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
kevman 0:38ceb79fef03 227
kevman 0:38ceb79fef03 228 #define APSR_V_Pos 28U /*!< APSR: V Position */
kevman 0:38ceb79fef03 229 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
kevman 0:38ceb79fef03 230
kevman 0:38ceb79fef03 231
kevman 0:38ceb79fef03 232 /**
kevman 0:38ceb79fef03 233 \brief Union type to access the Interrupt Program Status Register (IPSR).
kevman 0:38ceb79fef03 234 */
kevman 0:38ceb79fef03 235 typedef union
kevman 0:38ceb79fef03 236 {
kevman 0:38ceb79fef03 237 struct
kevman 0:38ceb79fef03 238 {
kevman 0:38ceb79fef03 239 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
kevman 0:38ceb79fef03 240 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
kevman 0:38ceb79fef03 241 } b; /*!< Structure used for bit access */
kevman 0:38ceb79fef03 242 uint32_t w; /*!< Type used for word access */
kevman 0:38ceb79fef03 243 } IPSR_Type;
kevman 0:38ceb79fef03 244
kevman 0:38ceb79fef03 245 /* IPSR Register Definitions */
kevman 0:38ceb79fef03 246 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
kevman 0:38ceb79fef03 247 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
kevman 0:38ceb79fef03 248
kevman 0:38ceb79fef03 249
kevman 0:38ceb79fef03 250 /**
kevman 0:38ceb79fef03 251 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
kevman 0:38ceb79fef03 252 */
kevman 0:38ceb79fef03 253 typedef union
kevman 0:38ceb79fef03 254 {
kevman 0:38ceb79fef03 255 struct
kevman 0:38ceb79fef03 256 {
kevman 0:38ceb79fef03 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
kevman 0:38ceb79fef03 258 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
kevman 0:38ceb79fef03 259 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
kevman 0:38ceb79fef03 260 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
kevman 0:38ceb79fef03 261 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
kevman 0:38ceb79fef03 262 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
kevman 0:38ceb79fef03 263 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
kevman 0:38ceb79fef03 264 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
kevman 0:38ceb79fef03 265 } b; /*!< Structure used for bit access */
kevman 0:38ceb79fef03 266 uint32_t w; /*!< Type used for word access */
kevman 0:38ceb79fef03 267 } xPSR_Type;
kevman 0:38ceb79fef03 268
kevman 0:38ceb79fef03 269 /* xPSR Register Definitions */
kevman 0:38ceb79fef03 270 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
kevman 0:38ceb79fef03 271 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
kevman 0:38ceb79fef03 272
kevman 0:38ceb79fef03 273 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
kevman 0:38ceb79fef03 274 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
kevman 0:38ceb79fef03 275
kevman 0:38ceb79fef03 276 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
kevman 0:38ceb79fef03 277 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
kevman 0:38ceb79fef03 278
kevman 0:38ceb79fef03 279 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
kevman 0:38ceb79fef03 280 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
kevman 0:38ceb79fef03 281
kevman 0:38ceb79fef03 282 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
kevman 0:38ceb79fef03 283 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
kevman 0:38ceb79fef03 284
kevman 0:38ceb79fef03 285 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
kevman 0:38ceb79fef03 286 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
kevman 0:38ceb79fef03 287
kevman 0:38ceb79fef03 288
kevman 0:38ceb79fef03 289 /**
kevman 0:38ceb79fef03 290 \brief Union type to access the Control Registers (CONTROL).
kevman 0:38ceb79fef03 291 */
kevman 0:38ceb79fef03 292 typedef union
kevman 0:38ceb79fef03 293 {
kevman 0:38ceb79fef03 294 struct
kevman 0:38ceb79fef03 295 {
kevman 0:38ceb79fef03 296 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
kevman 0:38ceb79fef03 297 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
kevman 0:38ceb79fef03 298 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
kevman 0:38ceb79fef03 299 } b; /*!< Structure used for bit access */
kevman 0:38ceb79fef03 300 uint32_t w; /*!< Type used for word access */
kevman 0:38ceb79fef03 301 } CONTROL_Type;
kevman 0:38ceb79fef03 302
kevman 0:38ceb79fef03 303 /* CONTROL Register Definitions */
kevman 0:38ceb79fef03 304 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
kevman 0:38ceb79fef03 305 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
kevman 0:38ceb79fef03 306
kevman 0:38ceb79fef03 307 /*@} end of group CMSIS_CORE */
kevman 0:38ceb79fef03 308
kevman 0:38ceb79fef03 309
kevman 0:38ceb79fef03 310 /**
kevman 0:38ceb79fef03 311 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 312 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
kevman 0:38ceb79fef03 313 \brief Type definitions for the NVIC Registers
kevman 0:38ceb79fef03 314 @{
kevman 0:38ceb79fef03 315 */
kevman 0:38ceb79fef03 316
kevman 0:38ceb79fef03 317 /**
kevman 0:38ceb79fef03 318 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
kevman 0:38ceb79fef03 319 */
kevman 0:38ceb79fef03 320 typedef struct
kevman 0:38ceb79fef03 321 {
kevman 0:38ceb79fef03 322 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
kevman 0:38ceb79fef03 323 uint32_t RESERVED0[31U];
kevman 0:38ceb79fef03 324 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
kevman 0:38ceb79fef03 325 uint32_t RSERVED1[31U];
kevman 0:38ceb79fef03 326 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
kevman 0:38ceb79fef03 327 uint32_t RESERVED2[31U];
kevman 0:38ceb79fef03 328 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
kevman 0:38ceb79fef03 329 uint32_t RESERVED3[31U];
kevman 0:38ceb79fef03 330 uint32_t RESERVED4[64U];
kevman 0:38ceb79fef03 331 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
kevman 0:38ceb79fef03 332 } NVIC_Type;
kevman 0:38ceb79fef03 333
kevman 0:38ceb79fef03 334 /*@} end of group CMSIS_NVIC */
kevman 0:38ceb79fef03 335
kevman 0:38ceb79fef03 336
kevman 0:38ceb79fef03 337 /**
kevman 0:38ceb79fef03 338 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 339 \defgroup CMSIS_SCB System Control Block (SCB)
kevman 0:38ceb79fef03 340 \brief Type definitions for the System Control Block Registers
kevman 0:38ceb79fef03 341 @{
kevman 0:38ceb79fef03 342 */
kevman 0:38ceb79fef03 343
kevman 0:38ceb79fef03 344 /**
kevman 0:38ceb79fef03 345 \brief Structure type to access the System Control Block (SCB).
kevman 0:38ceb79fef03 346 */
kevman 0:38ceb79fef03 347 typedef struct
kevman 0:38ceb79fef03 348 {
kevman 0:38ceb79fef03 349 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
kevman 0:38ceb79fef03 350 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
kevman 0:38ceb79fef03 351 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
kevman 0:38ceb79fef03 352 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
kevman 0:38ceb79fef03 353 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
kevman 0:38ceb79fef03 354 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
kevman 0:38ceb79fef03 355 uint32_t RESERVED0[1U];
kevman 0:38ceb79fef03 356 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
kevman 0:38ceb79fef03 357 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
kevman 0:38ceb79fef03 358 uint32_t RESERVED1[154U];
kevman 0:38ceb79fef03 359 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
kevman 0:38ceb79fef03 360 } SCB_Type;
kevman 0:38ceb79fef03 361
kevman 0:38ceb79fef03 362 /* SCB CPUID Register Definitions */
kevman 0:38ceb79fef03 363 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
kevman 0:38ceb79fef03 364 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
kevman 0:38ceb79fef03 365
kevman 0:38ceb79fef03 366 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
kevman 0:38ceb79fef03 367 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
kevman 0:38ceb79fef03 368
kevman 0:38ceb79fef03 369 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
kevman 0:38ceb79fef03 370 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
kevman 0:38ceb79fef03 371
kevman 0:38ceb79fef03 372 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
kevman 0:38ceb79fef03 373 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
kevman 0:38ceb79fef03 374
kevman 0:38ceb79fef03 375 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
kevman 0:38ceb79fef03 376 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
kevman 0:38ceb79fef03 377
kevman 0:38ceb79fef03 378 /* SCB Interrupt Control State Register Definitions */
kevman 0:38ceb79fef03 379 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
kevman 0:38ceb79fef03 380 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
kevman 0:38ceb79fef03 381
kevman 0:38ceb79fef03 382 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
kevman 0:38ceb79fef03 383 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
kevman 0:38ceb79fef03 384
kevman 0:38ceb79fef03 385 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
kevman 0:38ceb79fef03 386 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
kevman 0:38ceb79fef03 387
kevman 0:38ceb79fef03 388 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
kevman 0:38ceb79fef03 389 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
kevman 0:38ceb79fef03 390
kevman 0:38ceb79fef03 391 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
kevman 0:38ceb79fef03 392 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
kevman 0:38ceb79fef03 393
kevman 0:38ceb79fef03 394 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
kevman 0:38ceb79fef03 395 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
kevman 0:38ceb79fef03 396
kevman 0:38ceb79fef03 397 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
kevman 0:38ceb79fef03 398 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
kevman 0:38ceb79fef03 399
kevman 0:38ceb79fef03 400 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
kevman 0:38ceb79fef03 401 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
kevman 0:38ceb79fef03 402
kevman 0:38ceb79fef03 403 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
kevman 0:38ceb79fef03 404 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
kevman 0:38ceb79fef03 405
kevman 0:38ceb79fef03 406 /* SCB Interrupt Control State Register Definitions */
kevman 0:38ceb79fef03 407 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
kevman 0:38ceb79fef03 408 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
kevman 0:38ceb79fef03 409
kevman 0:38ceb79fef03 410 /* SCB Application Interrupt and Reset Control Register Definitions */
kevman 0:38ceb79fef03 411 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
kevman 0:38ceb79fef03 412 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
kevman 0:38ceb79fef03 413
kevman 0:38ceb79fef03 414 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
kevman 0:38ceb79fef03 415 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
kevman 0:38ceb79fef03 416
kevman 0:38ceb79fef03 417 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
kevman 0:38ceb79fef03 418 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
kevman 0:38ceb79fef03 419
kevman 0:38ceb79fef03 420 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
kevman 0:38ceb79fef03 421 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
kevman 0:38ceb79fef03 422
kevman 0:38ceb79fef03 423 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
kevman 0:38ceb79fef03 424 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
kevman 0:38ceb79fef03 425
kevman 0:38ceb79fef03 426 /* SCB System Control Register Definitions */
kevman 0:38ceb79fef03 427 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
kevman 0:38ceb79fef03 428 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
kevman 0:38ceb79fef03 429
kevman 0:38ceb79fef03 430 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
kevman 0:38ceb79fef03 431 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
kevman 0:38ceb79fef03 432
kevman 0:38ceb79fef03 433 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
kevman 0:38ceb79fef03 434 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
kevman 0:38ceb79fef03 435
kevman 0:38ceb79fef03 436 /* SCB Configuration Control Register Definitions */
kevman 0:38ceb79fef03 437 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
kevman 0:38ceb79fef03 438 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
kevman 0:38ceb79fef03 439
kevman 0:38ceb79fef03 440 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
kevman 0:38ceb79fef03 441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
kevman 0:38ceb79fef03 442
kevman 0:38ceb79fef03 443 /* SCB System Handler Control and State Register Definitions */
kevman 0:38ceb79fef03 444 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
kevman 0:38ceb79fef03 445 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
kevman 0:38ceb79fef03 446
kevman 0:38ceb79fef03 447 /*@} end of group CMSIS_SCB */
kevman 0:38ceb79fef03 448
kevman 0:38ceb79fef03 449
kevman 0:38ceb79fef03 450 /**
kevman 0:38ceb79fef03 451 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 452 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
kevman 0:38ceb79fef03 453 \brief Type definitions for the System Control and ID Register not in the SCB
kevman 0:38ceb79fef03 454 @{
kevman 0:38ceb79fef03 455 */
kevman 0:38ceb79fef03 456
kevman 0:38ceb79fef03 457 /**
kevman 0:38ceb79fef03 458 \brief Structure type to access the System Control and ID Register not in the SCB.
kevman 0:38ceb79fef03 459 */
kevman 0:38ceb79fef03 460 typedef struct
kevman 0:38ceb79fef03 461 {
kevman 0:38ceb79fef03 462 uint32_t RESERVED0[2U];
kevman 0:38ceb79fef03 463 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
kevman 0:38ceb79fef03 464 } SCnSCB_Type;
kevman 0:38ceb79fef03 465
kevman 0:38ceb79fef03 466 /* Auxiliary Control Register Definitions */
kevman 0:38ceb79fef03 467 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
kevman 0:38ceb79fef03 468 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
kevman 0:38ceb79fef03 469
kevman 0:38ceb79fef03 470 /*@} end of group CMSIS_SCnotSCB */
kevman 0:38ceb79fef03 471
kevman 0:38ceb79fef03 472
kevman 0:38ceb79fef03 473 /**
kevman 0:38ceb79fef03 474 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 475 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
kevman 0:38ceb79fef03 476 \brief Type definitions for the System Timer Registers.
kevman 0:38ceb79fef03 477 @{
kevman 0:38ceb79fef03 478 */
kevman 0:38ceb79fef03 479
kevman 0:38ceb79fef03 480 /**
kevman 0:38ceb79fef03 481 \brief Structure type to access the System Timer (SysTick).
kevman 0:38ceb79fef03 482 */
kevman 0:38ceb79fef03 483 typedef struct
kevman 0:38ceb79fef03 484 {
kevman 0:38ceb79fef03 485 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
kevman 0:38ceb79fef03 486 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
kevman 0:38ceb79fef03 487 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
kevman 0:38ceb79fef03 488 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
kevman 0:38ceb79fef03 489 } SysTick_Type;
kevman 0:38ceb79fef03 490
kevman 0:38ceb79fef03 491 /* SysTick Control / Status Register Definitions */
kevman 0:38ceb79fef03 492 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
kevman 0:38ceb79fef03 493 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
kevman 0:38ceb79fef03 494
kevman 0:38ceb79fef03 495 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
kevman 0:38ceb79fef03 496 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
kevman 0:38ceb79fef03 497
kevman 0:38ceb79fef03 498 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
kevman 0:38ceb79fef03 499 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
kevman 0:38ceb79fef03 500
kevman 0:38ceb79fef03 501 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
kevman 0:38ceb79fef03 502 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
kevman 0:38ceb79fef03 503
kevman 0:38ceb79fef03 504 /* SysTick Reload Register Definitions */
kevman 0:38ceb79fef03 505 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
kevman 0:38ceb79fef03 506 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
kevman 0:38ceb79fef03 507
kevman 0:38ceb79fef03 508 /* SysTick Current Register Definitions */
kevman 0:38ceb79fef03 509 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
kevman 0:38ceb79fef03 510 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
kevman 0:38ceb79fef03 511
kevman 0:38ceb79fef03 512 /* SysTick Calibration Register Definitions */
kevman 0:38ceb79fef03 513 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
kevman 0:38ceb79fef03 514 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
kevman 0:38ceb79fef03 515
kevman 0:38ceb79fef03 516 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
kevman 0:38ceb79fef03 517 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
kevman 0:38ceb79fef03 518
kevman 0:38ceb79fef03 519 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
kevman 0:38ceb79fef03 520 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
kevman 0:38ceb79fef03 521
kevman 0:38ceb79fef03 522 /*@} end of group CMSIS_SysTick */
kevman 0:38ceb79fef03 523
kevman 0:38ceb79fef03 524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman 0:38ceb79fef03 525 /**
kevman 0:38ceb79fef03 526 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
kevman 0:38ceb79fef03 528 \brief Type definitions for the Memory Protection Unit (MPU)
kevman 0:38ceb79fef03 529 @{
kevman 0:38ceb79fef03 530 */
kevman 0:38ceb79fef03 531
kevman 0:38ceb79fef03 532 /**
kevman 0:38ceb79fef03 533 \brief Structure type to access the Memory Protection Unit (MPU).
kevman 0:38ceb79fef03 534 */
kevman 0:38ceb79fef03 535 typedef struct
kevman 0:38ceb79fef03 536 {
kevman 0:38ceb79fef03 537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
kevman 0:38ceb79fef03 538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
kevman 0:38ceb79fef03 539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
kevman 0:38ceb79fef03 540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
kevman 0:38ceb79fef03 541 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
kevman 0:38ceb79fef03 542 } MPU_Type;
kevman 0:38ceb79fef03 543
kevman 0:38ceb79fef03 544 /* MPU Type Register Definitions */
kevman 0:38ceb79fef03 545 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
kevman 0:38ceb79fef03 546 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
kevman 0:38ceb79fef03 547
kevman 0:38ceb79fef03 548 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
kevman 0:38ceb79fef03 549 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
kevman 0:38ceb79fef03 550
kevman 0:38ceb79fef03 551 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
kevman 0:38ceb79fef03 552 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
kevman 0:38ceb79fef03 553
kevman 0:38ceb79fef03 554 /* MPU Control Register Definitions */
kevman 0:38ceb79fef03 555 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
kevman 0:38ceb79fef03 556 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
kevman 0:38ceb79fef03 557
kevman 0:38ceb79fef03 558 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
kevman 0:38ceb79fef03 559 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
kevman 0:38ceb79fef03 560
kevman 0:38ceb79fef03 561 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
kevman 0:38ceb79fef03 562 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
kevman 0:38ceb79fef03 563
kevman 0:38ceb79fef03 564 /* MPU Region Number Register Definitions */
kevman 0:38ceb79fef03 565 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
kevman 0:38ceb79fef03 566 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
kevman 0:38ceb79fef03 567
kevman 0:38ceb79fef03 568 /* MPU Region Base Address Register Definitions */
kevman 0:38ceb79fef03 569 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
kevman 0:38ceb79fef03 570 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
kevman 0:38ceb79fef03 571
kevman 0:38ceb79fef03 572 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
kevman 0:38ceb79fef03 573 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
kevman 0:38ceb79fef03 574
kevman 0:38ceb79fef03 575 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
kevman 0:38ceb79fef03 576 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
kevman 0:38ceb79fef03 577
kevman 0:38ceb79fef03 578 /* MPU Region Attribute and Size Register Definitions */
kevman 0:38ceb79fef03 579 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
kevman 0:38ceb79fef03 580 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
kevman 0:38ceb79fef03 581
kevman 0:38ceb79fef03 582 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
kevman 0:38ceb79fef03 583 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
kevman 0:38ceb79fef03 584
kevman 0:38ceb79fef03 585 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
kevman 0:38ceb79fef03 586 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
kevman 0:38ceb79fef03 587
kevman 0:38ceb79fef03 588 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
kevman 0:38ceb79fef03 589 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
kevman 0:38ceb79fef03 590
kevman 0:38ceb79fef03 591 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
kevman 0:38ceb79fef03 592 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
kevman 0:38ceb79fef03 593
kevman 0:38ceb79fef03 594 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
kevman 0:38ceb79fef03 595 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
kevman 0:38ceb79fef03 596
kevman 0:38ceb79fef03 597 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
kevman 0:38ceb79fef03 598 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
kevman 0:38ceb79fef03 599
kevman 0:38ceb79fef03 600 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
kevman 0:38ceb79fef03 601 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
kevman 0:38ceb79fef03 602
kevman 0:38ceb79fef03 603 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
kevman 0:38ceb79fef03 604 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
kevman 0:38ceb79fef03 605
kevman 0:38ceb79fef03 606 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
kevman 0:38ceb79fef03 607 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
kevman 0:38ceb79fef03 608
kevman 0:38ceb79fef03 609 /*@} end of group CMSIS_MPU */
kevman 0:38ceb79fef03 610 #endif
kevman 0:38ceb79fef03 611
kevman 0:38ceb79fef03 612
kevman 0:38ceb79fef03 613 /**
kevman 0:38ceb79fef03 614 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 615 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
kevman 0:38ceb79fef03 616 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
kevman 0:38ceb79fef03 617 Therefore they are not covered by the SC000 header file.
kevman 0:38ceb79fef03 618 @{
kevman 0:38ceb79fef03 619 */
kevman 0:38ceb79fef03 620 /*@} end of group CMSIS_CoreDebug */
kevman 0:38ceb79fef03 621
kevman 0:38ceb79fef03 622
kevman 0:38ceb79fef03 623 /**
kevman 0:38ceb79fef03 624 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 625 \defgroup CMSIS_core_bitfield Core register bit field macros
kevman 0:38ceb79fef03 626 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
kevman 0:38ceb79fef03 627 @{
kevman 0:38ceb79fef03 628 */
kevman 0:38ceb79fef03 629
kevman 0:38ceb79fef03 630 /**
kevman 0:38ceb79fef03 631 \brief Mask and shift a bit field value for use in a register bit range.
kevman 0:38ceb79fef03 632 \param[in] field Name of the register bit field.
kevman 0:38ceb79fef03 633 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
kevman 0:38ceb79fef03 634 \return Masked and shifted value.
kevman 0:38ceb79fef03 635 */
kevman 0:38ceb79fef03 636 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
kevman 0:38ceb79fef03 637
kevman 0:38ceb79fef03 638 /**
kevman 0:38ceb79fef03 639 \brief Mask and shift a register value to extract a bit filed value.
kevman 0:38ceb79fef03 640 \param[in] field Name of the register bit field.
kevman 0:38ceb79fef03 641 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
kevman 0:38ceb79fef03 642 \return Masked and shifted bit field value.
kevman 0:38ceb79fef03 643 */
kevman 0:38ceb79fef03 644 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
kevman 0:38ceb79fef03 645
kevman 0:38ceb79fef03 646 /*@} end of group CMSIS_core_bitfield */
kevman 0:38ceb79fef03 647
kevman 0:38ceb79fef03 648
kevman 0:38ceb79fef03 649 /**
kevman 0:38ceb79fef03 650 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 651 \defgroup CMSIS_core_base Core Definitions
kevman 0:38ceb79fef03 652 \brief Definitions for base addresses, unions, and structures.
kevman 0:38ceb79fef03 653 @{
kevman 0:38ceb79fef03 654 */
kevman 0:38ceb79fef03 655
kevman 0:38ceb79fef03 656 /* Memory mapping of Core Hardware */
kevman 0:38ceb79fef03 657 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
kevman 0:38ceb79fef03 658 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
kevman 0:38ceb79fef03 659 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
kevman 0:38ceb79fef03 660 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
kevman 0:38ceb79fef03 661
kevman 0:38ceb79fef03 662 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
kevman 0:38ceb79fef03 663 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
kevman 0:38ceb79fef03 664 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
kevman 0:38ceb79fef03 665 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
kevman 0:38ceb79fef03 666
kevman 0:38ceb79fef03 667 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman 0:38ceb79fef03 668 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
kevman 0:38ceb79fef03 669 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
kevman 0:38ceb79fef03 670 #endif
kevman 0:38ceb79fef03 671
kevman 0:38ceb79fef03 672 /*@} */
kevman 0:38ceb79fef03 673
kevman 0:38ceb79fef03 674
kevman 0:38ceb79fef03 675
kevman 0:38ceb79fef03 676 /*******************************************************************************
kevman 0:38ceb79fef03 677 * Hardware Abstraction Layer
kevman 0:38ceb79fef03 678 Core Function Interface contains:
kevman 0:38ceb79fef03 679 - Core NVIC Functions
kevman 0:38ceb79fef03 680 - Core SysTick Functions
kevman 0:38ceb79fef03 681 - Core Register Access Functions
kevman 0:38ceb79fef03 682 ******************************************************************************/
kevman 0:38ceb79fef03 683 /**
kevman 0:38ceb79fef03 684 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
kevman 0:38ceb79fef03 685 */
kevman 0:38ceb79fef03 686
kevman 0:38ceb79fef03 687
kevman 0:38ceb79fef03 688
kevman 0:38ceb79fef03 689 /* ########################## NVIC functions #################################### */
kevman 0:38ceb79fef03 690 /**
kevman 0:38ceb79fef03 691 \ingroup CMSIS_Core_FunctionInterface
kevman 0:38ceb79fef03 692 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
kevman 0:38ceb79fef03 693 \brief Functions that manage interrupts and exceptions via the NVIC.
kevman 0:38ceb79fef03 694 @{
kevman 0:38ceb79fef03 695 */
kevman 0:38ceb79fef03 696
kevman 0:38ceb79fef03 697 #ifdef CMSIS_NVIC_VIRTUAL
kevman 0:38ceb79fef03 698 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
kevman 0:38ceb79fef03 699 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
kevman 0:38ceb79fef03 700 #endif
kevman 0:38ceb79fef03 701 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
kevman 0:38ceb79fef03 702 #else
kevman 0:38ceb79fef03 703 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */
kevman 0:38ceb79fef03 704 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */
kevman 0:38ceb79fef03 705 #define NVIC_EnableIRQ __NVIC_EnableIRQ
kevman 0:38ceb79fef03 706 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
kevman 0:38ceb79fef03 707 #define NVIC_DisableIRQ __NVIC_DisableIRQ
kevman 0:38ceb79fef03 708 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
kevman 0:38ceb79fef03 709 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
kevman 0:38ceb79fef03 710 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
kevman 0:38ceb79fef03 711 /*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */
kevman 0:38ceb79fef03 712 #define NVIC_SetPriority __NVIC_SetPriority
kevman 0:38ceb79fef03 713 #define NVIC_GetPriority __NVIC_GetPriority
kevman 0:38ceb79fef03 714 #define NVIC_SystemReset __NVIC_SystemReset
kevman 0:38ceb79fef03 715 #endif /* CMSIS_NVIC_VIRTUAL */
kevman 0:38ceb79fef03 716
kevman 0:38ceb79fef03 717 #ifdef CMSIS_VECTAB_VIRTUAL
kevman 0:38ceb79fef03 718 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kevman 0:38ceb79fef03 719 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
kevman 0:38ceb79fef03 720 #endif
kevman 0:38ceb79fef03 721 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kevman 0:38ceb79fef03 722 #else
kevman 0:38ceb79fef03 723 #define NVIC_SetVector __NVIC_SetVector
kevman 0:38ceb79fef03 724 #define NVIC_GetVector __NVIC_GetVector
kevman 0:38ceb79fef03 725 #endif /* (CMSIS_VECTAB_VIRTUAL) */
kevman 0:38ceb79fef03 726
kevman 0:38ceb79fef03 727 #define NVIC_USER_IRQ_OFFSET 16
kevman 0:38ceb79fef03 728
kevman 0:38ceb79fef03 729
kevman 0:38ceb79fef03 730 /* The following EXC_RETURN values are saved the LR on exception entry */
kevman 0:38ceb79fef03 731 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
kevman 0:38ceb79fef03 732 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
kevman 0:38ceb79fef03 733 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
kevman 0:38ceb79fef03 734
kevman 0:38ceb79fef03 735
kevman 0:38ceb79fef03 736 /* Interrupt Priorities are WORD accessible only under Armv6-M */
kevman 0:38ceb79fef03 737 /* The following MACROS handle generation of the register offset and byte masks */
kevman 0:38ceb79fef03 738 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
kevman 0:38ceb79fef03 739 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
kevman 0:38ceb79fef03 740 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
kevman 0:38ceb79fef03 741
kevman 0:38ceb79fef03 742
kevman 0:38ceb79fef03 743 /**
kevman 0:38ceb79fef03 744 \brief Enable Interrupt
kevman 0:38ceb79fef03 745 \details Enables a device specific interrupt in the NVIC interrupt controller.
kevman 0:38ceb79fef03 746 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 747 \note IRQn must not be negative.
kevman 0:38ceb79fef03 748 */
kevman 0:38ceb79fef03 749 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 750 {
kevman 0:38ceb79fef03 751 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 752 {
kevman 0:38ceb79fef03 753 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman 0:38ceb79fef03 754 }
kevman 0:38ceb79fef03 755 }
kevman 0:38ceb79fef03 756
kevman 0:38ceb79fef03 757
kevman 0:38ceb79fef03 758 /**
kevman 0:38ceb79fef03 759 \brief Get Interrupt Enable status
kevman 0:38ceb79fef03 760 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
kevman 0:38ceb79fef03 761 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 762 \return 0 Interrupt is not enabled.
kevman 0:38ceb79fef03 763 \return 1 Interrupt is enabled.
kevman 0:38ceb79fef03 764 \note IRQn must not be negative.
kevman 0:38ceb79fef03 765 */
kevman 0:38ceb79fef03 766 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 767 {
kevman 0:38ceb79fef03 768 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 769 {
kevman 0:38ceb79fef03 770 return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman 0:38ceb79fef03 771 }
kevman 0:38ceb79fef03 772 else
kevman 0:38ceb79fef03 773 {
kevman 0:38ceb79fef03 774 return(0U);
kevman 0:38ceb79fef03 775 }
kevman 0:38ceb79fef03 776 }
kevman 0:38ceb79fef03 777
kevman 0:38ceb79fef03 778
kevman 0:38ceb79fef03 779 /**
kevman 0:38ceb79fef03 780 \brief Disable Interrupt
kevman 0:38ceb79fef03 781 \details Disables a device specific interrupt in the NVIC interrupt controller.
kevman 0:38ceb79fef03 782 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 783 \note IRQn must not be negative.
kevman 0:38ceb79fef03 784 */
kevman 0:38ceb79fef03 785 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 786 {
kevman 0:38ceb79fef03 787 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 788 {
kevman 0:38ceb79fef03 789 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman 0:38ceb79fef03 790 __DSB();
kevman 0:38ceb79fef03 791 __ISB();
kevman 0:38ceb79fef03 792 }
kevman 0:38ceb79fef03 793 }
kevman 0:38ceb79fef03 794
kevman 0:38ceb79fef03 795
kevman 0:38ceb79fef03 796 /**
kevman 0:38ceb79fef03 797 \brief Get Pending Interrupt
kevman 0:38ceb79fef03 798 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
kevman 0:38ceb79fef03 799 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 800 \return 0 Interrupt status is not pending.
kevman 0:38ceb79fef03 801 \return 1 Interrupt status is pending.
kevman 0:38ceb79fef03 802 \note IRQn must not be negative.
kevman 0:38ceb79fef03 803 */
kevman 0:38ceb79fef03 804 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 805 {
kevman 0:38ceb79fef03 806 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 807 {
kevman 0:38ceb79fef03 808 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman 0:38ceb79fef03 809 }
kevman 0:38ceb79fef03 810 else
kevman 0:38ceb79fef03 811 {
kevman 0:38ceb79fef03 812 return(0U);
kevman 0:38ceb79fef03 813 }
kevman 0:38ceb79fef03 814 }
kevman 0:38ceb79fef03 815
kevman 0:38ceb79fef03 816
kevman 0:38ceb79fef03 817 /**
kevman 0:38ceb79fef03 818 \brief Set Pending Interrupt
kevman 0:38ceb79fef03 819 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
kevman 0:38ceb79fef03 820 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 821 \note IRQn must not be negative.
kevman 0:38ceb79fef03 822 */
kevman 0:38ceb79fef03 823 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 824 {
kevman 0:38ceb79fef03 825 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 826 {
kevman 0:38ceb79fef03 827 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman 0:38ceb79fef03 828 }
kevman 0:38ceb79fef03 829 }
kevman 0:38ceb79fef03 830
kevman 0:38ceb79fef03 831
kevman 0:38ceb79fef03 832 /**
kevman 0:38ceb79fef03 833 \brief Clear Pending Interrupt
kevman 0:38ceb79fef03 834 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
kevman 0:38ceb79fef03 835 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 836 \note IRQn must not be negative.
kevman 0:38ceb79fef03 837 */
kevman 0:38ceb79fef03 838 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 839 {
kevman 0:38ceb79fef03 840 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 841 {
kevman 0:38ceb79fef03 842 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman 0:38ceb79fef03 843 }
kevman 0:38ceb79fef03 844 }
kevman 0:38ceb79fef03 845
kevman 0:38ceb79fef03 846
kevman 0:38ceb79fef03 847 /**
kevman 0:38ceb79fef03 848 \brief Set Interrupt Priority
kevman 0:38ceb79fef03 849 \details Sets the priority of a device specific interrupt or a processor exception.
kevman 0:38ceb79fef03 850 The interrupt number can be positive to specify a device specific interrupt,
kevman 0:38ceb79fef03 851 or negative to specify a processor exception.
kevman 0:38ceb79fef03 852 \param [in] IRQn Interrupt number.
kevman 0:38ceb79fef03 853 \param [in] priority Priority to set.
kevman 0:38ceb79fef03 854 \note The priority cannot be set for every processor exception.
kevman 0:38ceb79fef03 855 */
kevman 0:38ceb79fef03 856 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
kevman 0:38ceb79fef03 857 {
kevman 0:38ceb79fef03 858 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 859 {
kevman 0:38ceb79fef03 860 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
kevman 0:38ceb79fef03 861 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
kevman 0:38ceb79fef03 862 }
kevman 0:38ceb79fef03 863 else
kevman 0:38ceb79fef03 864 {
kevman 0:38ceb79fef03 865 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
kevman 0:38ceb79fef03 866 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
kevman 0:38ceb79fef03 867 }
kevman 0:38ceb79fef03 868 }
kevman 0:38ceb79fef03 869
kevman 0:38ceb79fef03 870
kevman 0:38ceb79fef03 871 /**
kevman 0:38ceb79fef03 872 \brief Get Interrupt Priority
kevman 0:38ceb79fef03 873 \details Reads the priority of a device specific interrupt or a processor exception.
kevman 0:38ceb79fef03 874 The interrupt number can be positive to specify a device specific interrupt,
kevman 0:38ceb79fef03 875 or negative to specify a processor exception.
kevman 0:38ceb79fef03 876 \param [in] IRQn Interrupt number.
kevman 0:38ceb79fef03 877 \return Interrupt Priority.
kevman 0:38ceb79fef03 878 Value is aligned automatically to the implemented priority bits of the microcontroller.
kevman 0:38ceb79fef03 879 */
kevman 0:38ceb79fef03 880 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
kevman 0:38ceb79fef03 881 {
kevman 0:38ceb79fef03 882
kevman 0:38ceb79fef03 883 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 884 {
kevman 0:38ceb79fef03 885 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
kevman 0:38ceb79fef03 886 }
kevman 0:38ceb79fef03 887 else
kevman 0:38ceb79fef03 888 {
kevman 0:38ceb79fef03 889 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
kevman 0:38ceb79fef03 890 }
kevman 0:38ceb79fef03 891 }
kevman 0:38ceb79fef03 892
kevman 0:38ceb79fef03 893
kevman 0:38ceb79fef03 894 /**
kevman 0:38ceb79fef03 895 \brief Set Interrupt Vector
kevman 0:38ceb79fef03 896 \details Sets an interrupt vector in SRAM based interrupt vector table.
kevman 0:38ceb79fef03 897 The interrupt number can be positive to specify a device specific interrupt,
kevman 0:38ceb79fef03 898 or negative to specify a processor exception.
kevman 0:38ceb79fef03 899 VTOR must been relocated to SRAM before.
kevman 0:38ceb79fef03 900 \param [in] IRQn Interrupt number
kevman 0:38ceb79fef03 901 \param [in] vector Address of interrupt handler function
kevman 0:38ceb79fef03 902 */
kevman 0:38ceb79fef03 903 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
kevman 0:38ceb79fef03 904 {
kevman 0:38ceb79fef03 905 uint32_t *vectors = (uint32_t *)SCB->VTOR;
kevman 0:38ceb79fef03 906 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
kevman 0:38ceb79fef03 907 }
kevman 0:38ceb79fef03 908
kevman 0:38ceb79fef03 909
kevman 0:38ceb79fef03 910 /**
kevman 0:38ceb79fef03 911 \brief Get Interrupt Vector
kevman 0:38ceb79fef03 912 \details Reads an interrupt vector from interrupt vector table.
kevman 0:38ceb79fef03 913 The interrupt number can be positive to specify a device specific interrupt,
kevman 0:38ceb79fef03 914 or negative to specify a processor exception.
kevman 0:38ceb79fef03 915 \param [in] IRQn Interrupt number.
kevman 0:38ceb79fef03 916 \return Address of interrupt handler function
kevman 0:38ceb79fef03 917 */
kevman 0:38ceb79fef03 918 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
kevman 0:38ceb79fef03 919 {
kevman 0:38ceb79fef03 920 uint32_t *vectors = (uint32_t *)SCB->VTOR;
kevman 0:38ceb79fef03 921 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
kevman 0:38ceb79fef03 922 }
kevman 0:38ceb79fef03 923
kevman 0:38ceb79fef03 924
kevman 0:38ceb79fef03 925 /**
kevman 0:38ceb79fef03 926 \brief System Reset
kevman 0:38ceb79fef03 927 \details Initiates a system reset request to reset the MCU.
kevman 0:38ceb79fef03 928 */
kevman 0:38ceb79fef03 929 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
kevman 0:38ceb79fef03 930 {
kevman 0:38ceb79fef03 931 __DSB(); /* Ensure all outstanding memory accesses included
kevman 0:38ceb79fef03 932 buffered write are completed before reset */
kevman 0:38ceb79fef03 933 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
kevman 0:38ceb79fef03 934 SCB_AIRCR_SYSRESETREQ_Msk);
kevman 0:38ceb79fef03 935 __DSB(); /* Ensure completion of memory access */
kevman 0:38ceb79fef03 936
kevman 0:38ceb79fef03 937 for(;;) /* wait until reset */
kevman 0:38ceb79fef03 938 {
kevman 0:38ceb79fef03 939 __NOP();
kevman 0:38ceb79fef03 940 }
kevman 0:38ceb79fef03 941 }
kevman 0:38ceb79fef03 942
kevman 0:38ceb79fef03 943 /*@} end of CMSIS_Core_NVICFunctions */
kevman 0:38ceb79fef03 944
kevman 0:38ceb79fef03 945
kevman 0:38ceb79fef03 946 /* ########################## FPU functions #################################### */
kevman 0:38ceb79fef03 947 /**
kevman 0:38ceb79fef03 948 \ingroup CMSIS_Core_FunctionInterface
kevman 0:38ceb79fef03 949 \defgroup CMSIS_Core_FpuFunctions FPU Functions
kevman 0:38ceb79fef03 950 \brief Function that provides FPU type.
kevman 0:38ceb79fef03 951 @{
kevman 0:38ceb79fef03 952 */
kevman 0:38ceb79fef03 953
kevman 0:38ceb79fef03 954 /**
kevman 0:38ceb79fef03 955 \brief get FPU type
kevman 0:38ceb79fef03 956 \details returns the FPU type
kevman 0:38ceb79fef03 957 \returns
kevman 0:38ceb79fef03 958 - \b 0: No FPU
kevman 0:38ceb79fef03 959 - \b 1: Single precision FPU
kevman 0:38ceb79fef03 960 - \b 2: Double + Single precision FPU
kevman 0:38ceb79fef03 961 */
kevman 0:38ceb79fef03 962 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
kevman 0:38ceb79fef03 963 {
kevman 0:38ceb79fef03 964 return 0U; /* No FPU */
kevman 0:38ceb79fef03 965 }
kevman 0:38ceb79fef03 966
kevman 0:38ceb79fef03 967
kevman 0:38ceb79fef03 968 /*@} end of CMSIS_Core_FpuFunctions */
kevman 0:38ceb79fef03 969
kevman 0:38ceb79fef03 970
kevman 0:38ceb79fef03 971
kevman 0:38ceb79fef03 972 /* ################################## SysTick function ############################################ */
kevman 0:38ceb79fef03 973 /**
kevman 0:38ceb79fef03 974 \ingroup CMSIS_Core_FunctionInterface
kevman 0:38ceb79fef03 975 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
kevman 0:38ceb79fef03 976 \brief Functions that configure the System.
kevman 0:38ceb79fef03 977 @{
kevman 0:38ceb79fef03 978 */
kevman 0:38ceb79fef03 979
kevman 0:38ceb79fef03 980 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
kevman 0:38ceb79fef03 981
kevman 0:38ceb79fef03 982 /**
kevman 0:38ceb79fef03 983 \brief System Tick Configuration
kevman 0:38ceb79fef03 984 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
kevman 0:38ceb79fef03 985 Counter is in free running mode to generate periodic interrupts.
kevman 0:38ceb79fef03 986 \param [in] ticks Number of ticks between two interrupts.
kevman 0:38ceb79fef03 987 \return 0 Function succeeded.
kevman 0:38ceb79fef03 988 \return 1 Function failed.
kevman 0:38ceb79fef03 989 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kevman 0:38ceb79fef03 990 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
kevman 0:38ceb79fef03 991 must contain a vendor-specific implementation of this function.
kevman 0:38ceb79fef03 992 */
kevman 0:38ceb79fef03 993 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
kevman 0:38ceb79fef03 994 {
kevman 0:38ceb79fef03 995 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kevman 0:38ceb79fef03 996 {
kevman 0:38ceb79fef03 997 return (1UL); /* Reload value impossible */
kevman 0:38ceb79fef03 998 }
kevman 0:38ceb79fef03 999
kevman 0:38ceb79fef03 1000 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kevman 0:38ceb79fef03 1001 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kevman 0:38ceb79fef03 1002 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
kevman 0:38ceb79fef03 1003 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
kevman 0:38ceb79fef03 1004 SysTick_CTRL_TICKINT_Msk |
kevman 0:38ceb79fef03 1005 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kevman 0:38ceb79fef03 1006 return (0UL); /* Function successful */
kevman 0:38ceb79fef03 1007 }
kevman 0:38ceb79fef03 1008
kevman 0:38ceb79fef03 1009 #endif
kevman 0:38ceb79fef03 1010
kevman 0:38ceb79fef03 1011 /*@} end of CMSIS_Core_SysTickFunctions */
kevman 0:38ceb79fef03 1012
kevman 0:38ceb79fef03 1013
kevman 0:38ceb79fef03 1014
kevman 0:38ceb79fef03 1015
kevman 0:38ceb79fef03 1016 #ifdef __cplusplus
kevman 0:38ceb79fef03 1017 }
kevman 0:38ceb79fef03 1018 #endif
kevman 0:38ceb79fef03 1019
kevman 0:38ceb79fef03 1020 #endif /* __CORE_SC000_H_DEPENDANT */
kevman 0:38ceb79fef03 1021
kevman 0:38ceb79fef03 1022 #endif /* __CMSIS_GENERIC */