Kev Mann / mbed-dev-OS5_10_4

RTC auf true

cmsis/TARGET_CORTEX_M/core_cm3.h@0:38ceb79fef03, 2018-11-28 (annotated)

Committer:
kevman
Date:
Wed Nov 28 15:10:15 2018 +0000
Revision:
0:38ceb79fef03
RTC modified

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kevman 0:38ceb79fef03 1 /**************************************************************************//**
kevman 0:38ceb79fef03 2 * @file core_cm3.h
kevman 0:38ceb79fef03 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
kevman 0:38ceb79fef03 4 * @version V5.0.8
kevman 0:38ceb79fef03 5 * @date 04. June 2018
kevman 0:38ceb79fef03 6 ******************************************************************************/
kevman 0:38ceb79fef03 7 /*
kevman 0:38ceb79fef03 8 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
kevman 0:38ceb79fef03 9 *
kevman 0:38ceb79fef03 10 * SPDX-License-Identifier: Apache-2.0
kevman 0:38ceb79fef03 11 *
kevman 0:38ceb79fef03 12 * Licensed under the Apache License, Version 2.0 (the License); you may
kevman 0:38ceb79fef03 13 * not use this file except in compliance with the License.
kevman 0:38ceb79fef03 14 * You may obtain a copy of the License at
kevman 0:38ceb79fef03 15 *
kevman 0:38ceb79fef03 16 * www.apache.org/licenses/LICENSE-2.0
kevman 0:38ceb79fef03 17 *
kevman 0:38ceb79fef03 18 * Unless required by applicable law or agreed to in writing, software
kevman 0:38ceb79fef03 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
kevman 0:38ceb79fef03 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kevman 0:38ceb79fef03 21 * See the License for the specific language governing permissions and
kevman 0:38ceb79fef03 22 * limitations under the License.
kevman 0:38ceb79fef03 23 */
kevman 0:38ceb79fef03 24
kevman 0:38ceb79fef03 25 #if defined ( __ICCARM__ )
kevman 0:38ceb79fef03 26 #pragma system_include /* treat file as system include file for MISRA check */
kevman 0:38ceb79fef03 27 #elif defined (__clang__)
kevman 0:38ceb79fef03 28 #pragma clang system_header /* treat file as system include file */
kevman 0:38ceb79fef03 29 #endif
kevman 0:38ceb79fef03 30
kevman 0:38ceb79fef03 31 #ifndef __CORE_CM3_H_GENERIC
kevman 0:38ceb79fef03 32 #define __CORE_CM3_H_GENERIC
kevman 0:38ceb79fef03 33
kevman 0:38ceb79fef03 34 #include <stdint.h>
kevman 0:38ceb79fef03 35
kevman 0:38ceb79fef03 36 #ifdef __cplusplus
kevman 0:38ceb79fef03 37 extern "C" {
kevman 0:38ceb79fef03 38 #endif
kevman 0:38ceb79fef03 39
kevman 0:38ceb79fef03 40 /**
kevman 0:38ceb79fef03 41 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
kevman 0:38ceb79fef03 42 CMSIS violates the following MISRA-C:2004 rules:
kevman 0:38ceb79fef03 43
kevman 0:38ceb79fef03 44 \li Required Rule 8.5, object/function definition in header file.<br>
kevman 0:38ceb79fef03 45 Function definitions in header files are used to allow 'inlining'.
kevman 0:38ceb79fef03 46
kevman 0:38ceb79fef03 47 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
kevman 0:38ceb79fef03 48 Unions are used for effective representation of core registers.
kevman 0:38ceb79fef03 49
kevman 0:38ceb79fef03 50 \li Advisory Rule 19.7, Function-like macro defined.<br>
kevman 0:38ceb79fef03 51 Function-like macros are used to allow more efficient code.
kevman 0:38ceb79fef03 52 */
kevman 0:38ceb79fef03 53
kevman 0:38ceb79fef03 54
kevman 0:38ceb79fef03 55 /*******************************************************************************
kevman 0:38ceb79fef03 56 * CMSIS definitions
kevman 0:38ceb79fef03 57 ******************************************************************************/
kevman 0:38ceb79fef03 58 /**
kevman 0:38ceb79fef03 59 \ingroup Cortex_M3
kevman 0:38ceb79fef03 60 @{
kevman 0:38ceb79fef03 61 */
kevman 0:38ceb79fef03 62
kevman 0:38ceb79fef03 63 #include "cmsis_version.h"
kevman 0:38ceb79fef03 64
kevman 0:38ceb79fef03 65 /* CMSIS CM3 definitions */
kevman 0:38ceb79fef03 66 #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
kevman 0:38ceb79fef03 67 #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
kevman 0:38ceb79fef03 68 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
kevman 0:38ceb79fef03 69 __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
kevman 0:38ceb79fef03 70
kevman 0:38ceb79fef03 71 #define __CORTEX_M (3U) /*!< Cortex-M Core */
kevman 0:38ceb79fef03 72
kevman 0:38ceb79fef03 73 /** __FPU_USED indicates whether an FPU is used or not.
kevman 0:38ceb79fef03 74 This core does not support an FPU at all
kevman 0:38ceb79fef03 75 */
kevman 0:38ceb79fef03 76 #define __FPU_USED 0U
kevman 0:38ceb79fef03 77
kevman 0:38ceb79fef03 78 #if defined ( __CC_ARM )
kevman 0:38ceb79fef03 79 #if defined __TARGET_FPU_VFP
kevman 0:38ceb79fef03 80 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 81 #endif
kevman 0:38ceb79fef03 82
kevman 0:38ceb79fef03 83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
kevman 0:38ceb79fef03 84 #if defined __ARM_PCS_VFP
kevman 0:38ceb79fef03 85 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 86 #endif
kevman 0:38ceb79fef03 87
kevman 0:38ceb79fef03 88 #elif defined ( __GNUC__ )
kevman 0:38ceb79fef03 89 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
kevman 0:38ceb79fef03 90 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 91 #endif
kevman 0:38ceb79fef03 92
kevman 0:38ceb79fef03 93 #elif defined ( __ICCARM__ )
kevman 0:38ceb79fef03 94 #if defined __ARMVFP__
kevman 0:38ceb79fef03 95 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 96 #endif
kevman 0:38ceb79fef03 97
kevman 0:38ceb79fef03 98 #elif defined ( __TI_ARM__ )
kevman 0:38ceb79fef03 99 #if defined __TI_VFP_SUPPORT__
kevman 0:38ceb79fef03 100 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 101 #endif
kevman 0:38ceb79fef03 102
kevman 0:38ceb79fef03 103 #elif defined ( __TASKING__ )
kevman 0:38ceb79fef03 104 #if defined __FPU_VFP__
kevman 0:38ceb79fef03 105 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 106 #endif
kevman 0:38ceb79fef03 107
kevman 0:38ceb79fef03 108 #elif defined ( __CSMC__ )
kevman 0:38ceb79fef03 109 #if ( __CSMC__ & 0x400U)
kevman 0:38ceb79fef03 110 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
kevman 0:38ceb79fef03 111 #endif
kevman 0:38ceb79fef03 112
kevman 0:38ceb79fef03 113 #endif
kevman 0:38ceb79fef03 114
kevman 0:38ceb79fef03 115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
kevman 0:38ceb79fef03 116
kevman 0:38ceb79fef03 117
kevman 0:38ceb79fef03 118 #ifdef __cplusplus
kevman 0:38ceb79fef03 119 }
kevman 0:38ceb79fef03 120 #endif
kevman 0:38ceb79fef03 121
kevman 0:38ceb79fef03 122 #endif /* __CORE_CM3_H_GENERIC */
kevman 0:38ceb79fef03 123
kevman 0:38ceb79fef03 124 #ifndef __CMSIS_GENERIC
kevman 0:38ceb79fef03 125
kevman 0:38ceb79fef03 126 #ifndef __CORE_CM3_H_DEPENDANT
kevman 0:38ceb79fef03 127 #define __CORE_CM3_H_DEPENDANT
kevman 0:38ceb79fef03 128
kevman 0:38ceb79fef03 129 #ifdef __cplusplus
kevman 0:38ceb79fef03 130 extern "C" {
kevman 0:38ceb79fef03 131 #endif
kevman 0:38ceb79fef03 132
kevman 0:38ceb79fef03 133 /* check device defines and use defaults */
kevman 0:38ceb79fef03 134 #if defined __CHECK_DEVICE_DEFINES
kevman 0:38ceb79fef03 135 #ifndef __CM3_REV
kevman 0:38ceb79fef03 136 #define __CM3_REV 0x0200U
kevman 0:38ceb79fef03 137 #warning "__CM3_REV not defined in device header file; using default!"
kevman 0:38ceb79fef03 138 #endif
kevman 0:38ceb79fef03 139
kevman 0:38ceb79fef03 140 #ifndef __MPU_PRESENT
kevman 0:38ceb79fef03 141 #define __MPU_PRESENT 0U
kevman 0:38ceb79fef03 142 #warning "__MPU_PRESENT not defined in device header file; using default!"
kevman 0:38ceb79fef03 143 #endif
kevman 0:38ceb79fef03 144
kevman 0:38ceb79fef03 145 #ifndef __NVIC_PRIO_BITS
kevman 0:38ceb79fef03 146 #define __NVIC_PRIO_BITS 3U
kevman 0:38ceb79fef03 147 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
kevman 0:38ceb79fef03 148 #endif
kevman 0:38ceb79fef03 149
kevman 0:38ceb79fef03 150 #ifndef __Vendor_SysTickConfig
kevman 0:38ceb79fef03 151 #define __Vendor_SysTickConfig 0U
kevman 0:38ceb79fef03 152 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
kevman 0:38ceb79fef03 153 #endif
kevman 0:38ceb79fef03 154 #endif
kevman 0:38ceb79fef03 155
kevman 0:38ceb79fef03 156 /* IO definitions (access restrictions to peripheral registers) */
kevman 0:38ceb79fef03 157 /**
kevman 0:38ceb79fef03 158 \defgroup CMSIS_glob_defs CMSIS Global Defines
kevman 0:38ceb79fef03 159
kevman 0:38ceb79fef03 160 <strong>IO Type Qualifiers</strong> are used
kevman 0:38ceb79fef03 161 \li to specify the access to peripheral variables.
kevman 0:38ceb79fef03 162 \li for automatic generation of peripheral register debug information.
kevman 0:38ceb79fef03 163 */
kevman 0:38ceb79fef03 164 #ifdef __cplusplus
kevman 0:38ceb79fef03 165 #define __I volatile /*!< Defines 'read only' permissions */
kevman 0:38ceb79fef03 166 #else
kevman 0:38ceb79fef03 167 #define __I volatile const /*!< Defines 'read only' permissions */
kevman 0:38ceb79fef03 168 #endif
kevman 0:38ceb79fef03 169 #define __O volatile /*!< Defines 'write only' permissions */
kevman 0:38ceb79fef03 170 #define __IO volatile /*!< Defines 'read / write' permissions */
kevman 0:38ceb79fef03 171
kevman 0:38ceb79fef03 172 /* following defines should be used for structure members */
kevman 0:38ceb79fef03 173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
kevman 0:38ceb79fef03 174 #define __OM volatile /*! Defines 'write only' structure member permissions */
kevman 0:38ceb79fef03 175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
kevman 0:38ceb79fef03 176
kevman 0:38ceb79fef03 177 /*@} end of group Cortex_M3 */
kevman 0:38ceb79fef03 178
kevman 0:38ceb79fef03 179
kevman 0:38ceb79fef03 180
kevman 0:38ceb79fef03 181 /*******************************************************************************
kevman 0:38ceb79fef03 182 * Register Abstraction
kevman 0:38ceb79fef03 183 Core Register contain:
kevman 0:38ceb79fef03 184 - Core Register
kevman 0:38ceb79fef03 185 - Core NVIC Register
kevman 0:38ceb79fef03 186 - Core SCB Register
kevman 0:38ceb79fef03 187 - Core SysTick Register
kevman 0:38ceb79fef03 188 - Core Debug Register
kevman 0:38ceb79fef03 189 - Core MPU Register
kevman 0:38ceb79fef03 190 ******************************************************************************/
kevman 0:38ceb79fef03 191 /**
kevman 0:38ceb79fef03 192 \defgroup CMSIS_core_register Defines and Type Definitions
kevman 0:38ceb79fef03 193 \brief Type definitions and defines for Cortex-M processor based devices.
kevman 0:38ceb79fef03 194 */
kevman 0:38ceb79fef03 195
kevman 0:38ceb79fef03 196 /**
kevman 0:38ceb79fef03 197 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 198 \defgroup CMSIS_CORE Status and Control Registers
kevman 0:38ceb79fef03 199 \brief Core Register type definitions.
kevman 0:38ceb79fef03 200 @{
kevman 0:38ceb79fef03 201 */
kevman 0:38ceb79fef03 202
kevman 0:38ceb79fef03 203 /**
kevman 0:38ceb79fef03 204 \brief Union type to access the Application Program Status Register (APSR).
kevman 0:38ceb79fef03 205 */
kevman 0:38ceb79fef03 206 typedef union
kevman 0:38ceb79fef03 207 {
kevman 0:38ceb79fef03 208 struct
kevman 0:38ceb79fef03 209 {
kevman 0:38ceb79fef03 210 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
kevman 0:38ceb79fef03 211 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
kevman 0:38ceb79fef03 212 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
kevman 0:38ceb79fef03 213 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
kevman 0:38ceb79fef03 214 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
kevman 0:38ceb79fef03 215 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
kevman 0:38ceb79fef03 216 } b; /*!< Structure used for bit access */
kevman 0:38ceb79fef03 217 uint32_t w; /*!< Type used for word access */
kevman 0:38ceb79fef03 218 } APSR_Type;
kevman 0:38ceb79fef03 219
kevman 0:38ceb79fef03 220 /* APSR Register Definitions */
kevman 0:38ceb79fef03 221 #define APSR_N_Pos 31U /*!< APSR: N Position */
kevman 0:38ceb79fef03 222 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
kevman 0:38ceb79fef03 223
kevman 0:38ceb79fef03 224 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
kevman 0:38ceb79fef03 225 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
kevman 0:38ceb79fef03 226
kevman 0:38ceb79fef03 227 #define APSR_C_Pos 29U /*!< APSR: C Position */
kevman 0:38ceb79fef03 228 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
kevman 0:38ceb79fef03 229
kevman 0:38ceb79fef03 230 #define APSR_V_Pos 28U /*!< APSR: V Position */
kevman 0:38ceb79fef03 231 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
kevman 0:38ceb79fef03 232
kevman 0:38ceb79fef03 233 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
kevman 0:38ceb79fef03 234 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
kevman 0:38ceb79fef03 235
kevman 0:38ceb79fef03 236
kevman 0:38ceb79fef03 237 /**
kevman 0:38ceb79fef03 238 \brief Union type to access the Interrupt Program Status Register (IPSR).
kevman 0:38ceb79fef03 239 */
kevman 0:38ceb79fef03 240 typedef union
kevman 0:38ceb79fef03 241 {
kevman 0:38ceb79fef03 242 struct
kevman 0:38ceb79fef03 243 {
kevman 0:38ceb79fef03 244 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
kevman 0:38ceb79fef03 245 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
kevman 0:38ceb79fef03 246 } b; /*!< Structure used for bit access */
kevman 0:38ceb79fef03 247 uint32_t w; /*!< Type used for word access */
kevman 0:38ceb79fef03 248 } IPSR_Type;
kevman 0:38ceb79fef03 249
kevman 0:38ceb79fef03 250 /* IPSR Register Definitions */
kevman 0:38ceb79fef03 251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
kevman 0:38ceb79fef03 252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
kevman 0:38ceb79fef03 253
kevman 0:38ceb79fef03 254
kevman 0:38ceb79fef03 255 /**
kevman 0:38ceb79fef03 256 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
kevman 0:38ceb79fef03 257 */
kevman 0:38ceb79fef03 258 typedef union
kevman 0:38ceb79fef03 259 {
kevman 0:38ceb79fef03 260 struct
kevman 0:38ceb79fef03 261 {
kevman 0:38ceb79fef03 262 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
kevman 0:38ceb79fef03 263 uint32_t _reserved0:1; /*!< bit: 9 Reserved */
kevman 0:38ceb79fef03 264 uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
kevman 0:38ceb79fef03 265 uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
kevman 0:38ceb79fef03 266 uint32_t T:1; /*!< bit: 24 Thumb bit */
kevman 0:38ceb79fef03 267 uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
kevman 0:38ceb79fef03 268 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
kevman 0:38ceb79fef03 269 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
kevman 0:38ceb79fef03 270 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
kevman 0:38ceb79fef03 271 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
kevman 0:38ceb79fef03 272 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
kevman 0:38ceb79fef03 273 } b; /*!< Structure used for bit access */
kevman 0:38ceb79fef03 274 uint32_t w; /*!< Type used for word access */
kevman 0:38ceb79fef03 275 } xPSR_Type;
kevman 0:38ceb79fef03 276
kevman 0:38ceb79fef03 277 /* xPSR Register Definitions */
kevman 0:38ceb79fef03 278 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
kevman 0:38ceb79fef03 279 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
kevman 0:38ceb79fef03 280
kevman 0:38ceb79fef03 281 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
kevman 0:38ceb79fef03 282 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
kevman 0:38ceb79fef03 283
kevman 0:38ceb79fef03 284 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
kevman 0:38ceb79fef03 285 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
kevman 0:38ceb79fef03 286
kevman 0:38ceb79fef03 287 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
kevman 0:38ceb79fef03 288 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
kevman 0:38ceb79fef03 289
kevman 0:38ceb79fef03 290 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
kevman 0:38ceb79fef03 291 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
kevman 0:38ceb79fef03 292
kevman 0:38ceb79fef03 293 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
kevman 0:38ceb79fef03 294 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
kevman 0:38ceb79fef03 295
kevman 0:38ceb79fef03 296 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
kevman 0:38ceb79fef03 297 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
kevman 0:38ceb79fef03 298
kevman 0:38ceb79fef03 299 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
kevman 0:38ceb79fef03 300 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
kevman 0:38ceb79fef03 301
kevman 0:38ceb79fef03 302 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
kevman 0:38ceb79fef03 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
kevman 0:38ceb79fef03 304
kevman 0:38ceb79fef03 305
kevman 0:38ceb79fef03 306 /**
kevman 0:38ceb79fef03 307 \brief Union type to access the Control Registers (CONTROL).
kevman 0:38ceb79fef03 308 */
kevman 0:38ceb79fef03 309 typedef union
kevman 0:38ceb79fef03 310 {
kevman 0:38ceb79fef03 311 struct
kevman 0:38ceb79fef03 312 {
kevman 0:38ceb79fef03 313 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
kevman 0:38ceb79fef03 314 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
kevman 0:38ceb79fef03 315 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
kevman 0:38ceb79fef03 316 } b; /*!< Structure used for bit access */
kevman 0:38ceb79fef03 317 uint32_t w; /*!< Type used for word access */
kevman 0:38ceb79fef03 318 } CONTROL_Type;
kevman 0:38ceb79fef03 319
kevman 0:38ceb79fef03 320 /* CONTROL Register Definitions */
kevman 0:38ceb79fef03 321 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
kevman 0:38ceb79fef03 322 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
kevman 0:38ceb79fef03 323
kevman 0:38ceb79fef03 324 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
kevman 0:38ceb79fef03 325 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
kevman 0:38ceb79fef03 326
kevman 0:38ceb79fef03 327 /*@} end of group CMSIS_CORE */
kevman 0:38ceb79fef03 328
kevman 0:38ceb79fef03 329
kevman 0:38ceb79fef03 330 /**
kevman 0:38ceb79fef03 331 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 332 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
kevman 0:38ceb79fef03 333 \brief Type definitions for the NVIC Registers
kevman 0:38ceb79fef03 334 @{
kevman 0:38ceb79fef03 335 */
kevman 0:38ceb79fef03 336
kevman 0:38ceb79fef03 337 /**
kevman 0:38ceb79fef03 338 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
kevman 0:38ceb79fef03 339 */
kevman 0:38ceb79fef03 340 typedef struct
kevman 0:38ceb79fef03 341 {
kevman 0:38ceb79fef03 342 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
kevman 0:38ceb79fef03 343 uint32_t RESERVED0[24U];
kevman 0:38ceb79fef03 344 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
kevman 0:38ceb79fef03 345 uint32_t RSERVED1[24U];
kevman 0:38ceb79fef03 346 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
kevman 0:38ceb79fef03 347 uint32_t RESERVED2[24U];
kevman 0:38ceb79fef03 348 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
kevman 0:38ceb79fef03 349 uint32_t RESERVED3[24U];
kevman 0:38ceb79fef03 350 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
kevman 0:38ceb79fef03 351 uint32_t RESERVED4[56U];
kevman 0:38ceb79fef03 352 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
kevman 0:38ceb79fef03 353 uint32_t RESERVED5[644U];
kevman 0:38ceb79fef03 354 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
kevman 0:38ceb79fef03 355 } NVIC_Type;
kevman 0:38ceb79fef03 356
kevman 0:38ceb79fef03 357 /* Software Triggered Interrupt Register Definitions */
kevman 0:38ceb79fef03 358 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
kevman 0:38ceb79fef03 359 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
kevman 0:38ceb79fef03 360
kevman 0:38ceb79fef03 361 /*@} end of group CMSIS_NVIC */
kevman 0:38ceb79fef03 362
kevman 0:38ceb79fef03 363
kevman 0:38ceb79fef03 364 /**
kevman 0:38ceb79fef03 365 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 366 \defgroup CMSIS_SCB System Control Block (SCB)
kevman 0:38ceb79fef03 367 \brief Type definitions for the System Control Block Registers
kevman 0:38ceb79fef03 368 @{
kevman 0:38ceb79fef03 369 */
kevman 0:38ceb79fef03 370
kevman 0:38ceb79fef03 371 /**
kevman 0:38ceb79fef03 372 \brief Structure type to access the System Control Block (SCB).
kevman 0:38ceb79fef03 373 */
kevman 0:38ceb79fef03 374 typedef struct
kevman 0:38ceb79fef03 375 {
kevman 0:38ceb79fef03 376 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
kevman 0:38ceb79fef03 377 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
kevman 0:38ceb79fef03 378 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
kevman 0:38ceb79fef03 379 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
kevman 0:38ceb79fef03 380 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
kevman 0:38ceb79fef03 381 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
kevman 0:38ceb79fef03 382 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
kevman 0:38ceb79fef03 383 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
kevman 0:38ceb79fef03 384 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
kevman 0:38ceb79fef03 385 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
kevman 0:38ceb79fef03 386 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
kevman 0:38ceb79fef03 387 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
kevman 0:38ceb79fef03 388 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
kevman 0:38ceb79fef03 389 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
kevman 0:38ceb79fef03 390 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
kevman 0:38ceb79fef03 391 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
kevman 0:38ceb79fef03 392 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
kevman 0:38ceb79fef03 393 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
kevman 0:38ceb79fef03 394 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
kevman 0:38ceb79fef03 395 uint32_t RESERVED0[5U];
kevman 0:38ceb79fef03 396 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
kevman 0:38ceb79fef03 397 } SCB_Type;
kevman 0:38ceb79fef03 398
kevman 0:38ceb79fef03 399 /* SCB CPUID Register Definitions */
kevman 0:38ceb79fef03 400 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
kevman 0:38ceb79fef03 401 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
kevman 0:38ceb79fef03 402
kevman 0:38ceb79fef03 403 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
kevman 0:38ceb79fef03 404 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
kevman 0:38ceb79fef03 405
kevman 0:38ceb79fef03 406 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
kevman 0:38ceb79fef03 407 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
kevman 0:38ceb79fef03 408
kevman 0:38ceb79fef03 409 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
kevman 0:38ceb79fef03 410 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
kevman 0:38ceb79fef03 411
kevman 0:38ceb79fef03 412 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
kevman 0:38ceb79fef03 413 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
kevman 0:38ceb79fef03 414
kevman 0:38ceb79fef03 415 /* SCB Interrupt Control State Register Definitions */
kevman 0:38ceb79fef03 416 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
kevman 0:38ceb79fef03 417 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
kevman 0:38ceb79fef03 418
kevman 0:38ceb79fef03 419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
kevman 0:38ceb79fef03 420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
kevman 0:38ceb79fef03 421
kevman 0:38ceb79fef03 422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
kevman 0:38ceb79fef03 423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
kevman 0:38ceb79fef03 424
kevman 0:38ceb79fef03 425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
kevman 0:38ceb79fef03 426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
kevman 0:38ceb79fef03 427
kevman 0:38ceb79fef03 428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
kevman 0:38ceb79fef03 429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
kevman 0:38ceb79fef03 430
kevman 0:38ceb79fef03 431 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
kevman 0:38ceb79fef03 432 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
kevman 0:38ceb79fef03 433
kevman 0:38ceb79fef03 434 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
kevman 0:38ceb79fef03 435 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
kevman 0:38ceb79fef03 436
kevman 0:38ceb79fef03 437 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
kevman 0:38ceb79fef03 438 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
kevman 0:38ceb79fef03 439
kevman 0:38ceb79fef03 440 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
kevman 0:38ceb79fef03 441 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
kevman 0:38ceb79fef03 442
kevman 0:38ceb79fef03 443 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
kevman 0:38ceb79fef03 444 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
kevman 0:38ceb79fef03 445
kevman 0:38ceb79fef03 446 /* SCB Vector Table Offset Register Definitions */
kevman 0:38ceb79fef03 447 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
kevman 0:38ceb79fef03 448 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
kevman 0:38ceb79fef03 449 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
kevman 0:38ceb79fef03 450
kevman 0:38ceb79fef03 451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
kevman 0:38ceb79fef03 452 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
kevman 0:38ceb79fef03 453 #else
kevman 0:38ceb79fef03 454 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
kevman 0:38ceb79fef03 455 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
kevman 0:38ceb79fef03 456 #endif
kevman 0:38ceb79fef03 457
kevman 0:38ceb79fef03 458 /* SCB Application Interrupt and Reset Control Register Definitions */
kevman 0:38ceb79fef03 459 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
kevman 0:38ceb79fef03 460 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
kevman 0:38ceb79fef03 461
kevman 0:38ceb79fef03 462 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
kevman 0:38ceb79fef03 463 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
kevman 0:38ceb79fef03 464
kevman 0:38ceb79fef03 465 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
kevman 0:38ceb79fef03 466 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
kevman 0:38ceb79fef03 467
kevman 0:38ceb79fef03 468 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
kevman 0:38ceb79fef03 469 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
kevman 0:38ceb79fef03 470
kevman 0:38ceb79fef03 471 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
kevman 0:38ceb79fef03 472 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
kevman 0:38ceb79fef03 473
kevman 0:38ceb79fef03 474 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
kevman 0:38ceb79fef03 475 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
kevman 0:38ceb79fef03 476
kevman 0:38ceb79fef03 477 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
kevman 0:38ceb79fef03 478 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
kevman 0:38ceb79fef03 479
kevman 0:38ceb79fef03 480 /* SCB System Control Register Definitions */
kevman 0:38ceb79fef03 481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
kevman 0:38ceb79fef03 482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
kevman 0:38ceb79fef03 483
kevman 0:38ceb79fef03 484 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
kevman 0:38ceb79fef03 485 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
kevman 0:38ceb79fef03 486
kevman 0:38ceb79fef03 487 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
kevman 0:38ceb79fef03 488 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
kevman 0:38ceb79fef03 489
kevman 0:38ceb79fef03 490 /* SCB Configuration Control Register Definitions */
kevman 0:38ceb79fef03 491 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
kevman 0:38ceb79fef03 492 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
kevman 0:38ceb79fef03 493
kevman 0:38ceb79fef03 494 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
kevman 0:38ceb79fef03 495 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
kevman 0:38ceb79fef03 496
kevman 0:38ceb79fef03 497 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
kevman 0:38ceb79fef03 498 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
kevman 0:38ceb79fef03 499
kevman 0:38ceb79fef03 500 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
kevman 0:38ceb79fef03 501 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
kevman 0:38ceb79fef03 502
kevman 0:38ceb79fef03 503 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
kevman 0:38ceb79fef03 504 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
kevman 0:38ceb79fef03 505
kevman 0:38ceb79fef03 506 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
kevman 0:38ceb79fef03 507 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
kevman 0:38ceb79fef03 508
kevman 0:38ceb79fef03 509 /* SCB System Handler Control and State Register Definitions */
kevman 0:38ceb79fef03 510 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
kevman 0:38ceb79fef03 511 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
kevman 0:38ceb79fef03 512
kevman 0:38ceb79fef03 513 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
kevman 0:38ceb79fef03 514 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
kevman 0:38ceb79fef03 515
kevman 0:38ceb79fef03 516 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
kevman 0:38ceb79fef03 517 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
kevman 0:38ceb79fef03 518
kevman 0:38ceb79fef03 519 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
kevman 0:38ceb79fef03 520 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
kevman 0:38ceb79fef03 521
kevman 0:38ceb79fef03 522 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
kevman 0:38ceb79fef03 523 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
kevman 0:38ceb79fef03 524
kevman 0:38ceb79fef03 525 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
kevman 0:38ceb79fef03 526 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
kevman 0:38ceb79fef03 527
kevman 0:38ceb79fef03 528 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
kevman 0:38ceb79fef03 529 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
kevman 0:38ceb79fef03 530
kevman 0:38ceb79fef03 531 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
kevman 0:38ceb79fef03 532 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
kevman 0:38ceb79fef03 533
kevman 0:38ceb79fef03 534 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
kevman 0:38ceb79fef03 535 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
kevman 0:38ceb79fef03 536
kevman 0:38ceb79fef03 537 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
kevman 0:38ceb79fef03 538 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
kevman 0:38ceb79fef03 539
kevman 0:38ceb79fef03 540 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
kevman 0:38ceb79fef03 541 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
kevman 0:38ceb79fef03 542
kevman 0:38ceb79fef03 543 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
kevman 0:38ceb79fef03 544 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
kevman 0:38ceb79fef03 545
kevman 0:38ceb79fef03 546 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
kevman 0:38ceb79fef03 547 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
kevman 0:38ceb79fef03 548
kevman 0:38ceb79fef03 549 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
kevman 0:38ceb79fef03 550 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
kevman 0:38ceb79fef03 551
kevman 0:38ceb79fef03 552 /* SCB Configurable Fault Status Register Definitions */
kevman 0:38ceb79fef03 553 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
kevman 0:38ceb79fef03 554 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
kevman 0:38ceb79fef03 555
kevman 0:38ceb79fef03 556 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
kevman 0:38ceb79fef03 557 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
kevman 0:38ceb79fef03 558
kevman 0:38ceb79fef03 559 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
kevman 0:38ceb79fef03 560 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
kevman 0:38ceb79fef03 561
kevman 0:38ceb79fef03 562 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
kevman 0:38ceb79fef03 563 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
kevman 0:38ceb79fef03 564 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
kevman 0:38ceb79fef03 565
kevman 0:38ceb79fef03 566 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
kevman 0:38ceb79fef03 567 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
kevman 0:38ceb79fef03 568
kevman 0:38ceb79fef03 569 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
kevman 0:38ceb79fef03 570 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
kevman 0:38ceb79fef03 571
kevman 0:38ceb79fef03 572 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
kevman 0:38ceb79fef03 573 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
kevman 0:38ceb79fef03 574
kevman 0:38ceb79fef03 575 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
kevman 0:38ceb79fef03 576 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
kevman 0:38ceb79fef03 577
kevman 0:38ceb79fef03 578 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
kevman 0:38ceb79fef03 579 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
kevman 0:38ceb79fef03 580 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
kevman 0:38ceb79fef03 581
kevman 0:38ceb79fef03 582 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
kevman 0:38ceb79fef03 583 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
kevman 0:38ceb79fef03 584
kevman 0:38ceb79fef03 585 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
kevman 0:38ceb79fef03 586 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
kevman 0:38ceb79fef03 587
kevman 0:38ceb79fef03 588 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
kevman 0:38ceb79fef03 589 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
kevman 0:38ceb79fef03 590
kevman 0:38ceb79fef03 591 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
kevman 0:38ceb79fef03 592 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
kevman 0:38ceb79fef03 593
kevman 0:38ceb79fef03 594 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
kevman 0:38ceb79fef03 595 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
kevman 0:38ceb79fef03 596
kevman 0:38ceb79fef03 597 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
kevman 0:38ceb79fef03 598 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
kevman 0:38ceb79fef03 599 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
kevman 0:38ceb79fef03 600
kevman 0:38ceb79fef03 601 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
kevman 0:38ceb79fef03 602 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
kevman 0:38ceb79fef03 603
kevman 0:38ceb79fef03 604 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
kevman 0:38ceb79fef03 605 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
kevman 0:38ceb79fef03 606
kevman 0:38ceb79fef03 607 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
kevman 0:38ceb79fef03 608 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
kevman 0:38ceb79fef03 609
kevman 0:38ceb79fef03 610 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
kevman 0:38ceb79fef03 611 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
kevman 0:38ceb79fef03 612
kevman 0:38ceb79fef03 613 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
kevman 0:38ceb79fef03 614 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
kevman 0:38ceb79fef03 615
kevman 0:38ceb79fef03 616 /* SCB Hard Fault Status Register Definitions */
kevman 0:38ceb79fef03 617 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
kevman 0:38ceb79fef03 618 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
kevman 0:38ceb79fef03 619
kevman 0:38ceb79fef03 620 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
kevman 0:38ceb79fef03 621 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
kevman 0:38ceb79fef03 622
kevman 0:38ceb79fef03 623 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
kevman 0:38ceb79fef03 624 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
kevman 0:38ceb79fef03 625
kevman 0:38ceb79fef03 626 /* SCB Debug Fault Status Register Definitions */
kevman 0:38ceb79fef03 627 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
kevman 0:38ceb79fef03 628 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
kevman 0:38ceb79fef03 629
kevman 0:38ceb79fef03 630 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
kevman 0:38ceb79fef03 631 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
kevman 0:38ceb79fef03 632
kevman 0:38ceb79fef03 633 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
kevman 0:38ceb79fef03 634 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
kevman 0:38ceb79fef03 635
kevman 0:38ceb79fef03 636 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
kevman 0:38ceb79fef03 637 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
kevman 0:38ceb79fef03 638
kevman 0:38ceb79fef03 639 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
kevman 0:38ceb79fef03 640 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
kevman 0:38ceb79fef03 641
kevman 0:38ceb79fef03 642 /*@} end of group CMSIS_SCB */
kevman 0:38ceb79fef03 643
kevman 0:38ceb79fef03 644
kevman 0:38ceb79fef03 645 /**
kevman 0:38ceb79fef03 646 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 647 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
kevman 0:38ceb79fef03 648 \brief Type definitions for the System Control and ID Register not in the SCB
kevman 0:38ceb79fef03 649 @{
kevman 0:38ceb79fef03 650 */
kevman 0:38ceb79fef03 651
kevman 0:38ceb79fef03 652 /**
kevman 0:38ceb79fef03 653 \brief Structure type to access the System Control and ID Register not in the SCB.
kevman 0:38ceb79fef03 654 */
kevman 0:38ceb79fef03 655 typedef struct
kevman 0:38ceb79fef03 656 {
kevman 0:38ceb79fef03 657 uint32_t RESERVED0[1U];
kevman 0:38ceb79fef03 658 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
kevman 0:38ceb79fef03 659 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
kevman 0:38ceb79fef03 660 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
kevman 0:38ceb79fef03 661 #else
kevman 0:38ceb79fef03 662 uint32_t RESERVED1[1U];
kevman 0:38ceb79fef03 663 #endif
kevman 0:38ceb79fef03 664 } SCnSCB_Type;
kevman 0:38ceb79fef03 665
kevman 0:38ceb79fef03 666 /* Interrupt Controller Type Register Definitions */
kevman 0:38ceb79fef03 667 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
kevman 0:38ceb79fef03 668 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
kevman 0:38ceb79fef03 669
kevman 0:38ceb79fef03 670 /* Auxiliary Control Register Definitions */
kevman 0:38ceb79fef03 671
kevman 0:38ceb79fef03 672 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
kevman 0:38ceb79fef03 673 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
kevman 0:38ceb79fef03 674
kevman 0:38ceb79fef03 675 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
kevman 0:38ceb79fef03 676 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
kevman 0:38ceb79fef03 677
kevman 0:38ceb79fef03 678 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
kevman 0:38ceb79fef03 679 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
kevman 0:38ceb79fef03 680
kevman 0:38ceb79fef03 681 /*@} end of group CMSIS_SCnotSCB */
kevman 0:38ceb79fef03 682
kevman 0:38ceb79fef03 683
kevman 0:38ceb79fef03 684 /**
kevman 0:38ceb79fef03 685 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 686 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
kevman 0:38ceb79fef03 687 \brief Type definitions for the System Timer Registers.
kevman 0:38ceb79fef03 688 @{
kevman 0:38ceb79fef03 689 */
kevman 0:38ceb79fef03 690
kevman 0:38ceb79fef03 691 /**
kevman 0:38ceb79fef03 692 \brief Structure type to access the System Timer (SysTick).
kevman 0:38ceb79fef03 693 */
kevman 0:38ceb79fef03 694 typedef struct
kevman 0:38ceb79fef03 695 {
kevman 0:38ceb79fef03 696 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
kevman 0:38ceb79fef03 697 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
kevman 0:38ceb79fef03 698 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
kevman 0:38ceb79fef03 699 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
kevman 0:38ceb79fef03 700 } SysTick_Type;
kevman 0:38ceb79fef03 701
kevman 0:38ceb79fef03 702 /* SysTick Control / Status Register Definitions */
kevman 0:38ceb79fef03 703 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
kevman 0:38ceb79fef03 704 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
kevman 0:38ceb79fef03 705
kevman 0:38ceb79fef03 706 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
kevman 0:38ceb79fef03 707 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
kevman 0:38ceb79fef03 708
kevman 0:38ceb79fef03 709 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
kevman 0:38ceb79fef03 710 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
kevman 0:38ceb79fef03 711
kevman 0:38ceb79fef03 712 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
kevman 0:38ceb79fef03 713 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
kevman 0:38ceb79fef03 714
kevman 0:38ceb79fef03 715 /* SysTick Reload Register Definitions */
kevman 0:38ceb79fef03 716 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
kevman 0:38ceb79fef03 717 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
kevman 0:38ceb79fef03 718
kevman 0:38ceb79fef03 719 /* SysTick Current Register Definitions */
kevman 0:38ceb79fef03 720 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
kevman 0:38ceb79fef03 721 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
kevman 0:38ceb79fef03 722
kevman 0:38ceb79fef03 723 /* SysTick Calibration Register Definitions */
kevman 0:38ceb79fef03 724 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
kevman 0:38ceb79fef03 725 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
kevman 0:38ceb79fef03 726
kevman 0:38ceb79fef03 727 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
kevman 0:38ceb79fef03 728 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
kevman 0:38ceb79fef03 729
kevman 0:38ceb79fef03 730 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
kevman 0:38ceb79fef03 731 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
kevman 0:38ceb79fef03 732
kevman 0:38ceb79fef03 733 /*@} end of group CMSIS_SysTick */
kevman 0:38ceb79fef03 734
kevman 0:38ceb79fef03 735
kevman 0:38ceb79fef03 736 /**
kevman 0:38ceb79fef03 737 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 738 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
kevman 0:38ceb79fef03 739 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
kevman 0:38ceb79fef03 740 @{
kevman 0:38ceb79fef03 741 */
kevman 0:38ceb79fef03 742
kevman 0:38ceb79fef03 743 /**
kevman 0:38ceb79fef03 744 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
kevman 0:38ceb79fef03 745 */
kevman 0:38ceb79fef03 746 typedef struct
kevman 0:38ceb79fef03 747 {
kevman 0:38ceb79fef03 748 __OM union
kevman 0:38ceb79fef03 749 {
kevman 0:38ceb79fef03 750 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
kevman 0:38ceb79fef03 751 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
kevman 0:38ceb79fef03 752 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
kevman 0:38ceb79fef03 753 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
kevman 0:38ceb79fef03 754 uint32_t RESERVED0[864U];
kevman 0:38ceb79fef03 755 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
kevman 0:38ceb79fef03 756 uint32_t RESERVED1[15U];
kevman 0:38ceb79fef03 757 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
kevman 0:38ceb79fef03 758 uint32_t RESERVED2[15U];
kevman 0:38ceb79fef03 759 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
kevman 0:38ceb79fef03 760 uint32_t RESERVED3[29U];
kevman 0:38ceb79fef03 761 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
kevman 0:38ceb79fef03 762 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
kevman 0:38ceb79fef03 763 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
kevman 0:38ceb79fef03 764 uint32_t RESERVED4[43U];
kevman 0:38ceb79fef03 765 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
kevman 0:38ceb79fef03 766 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
kevman 0:38ceb79fef03 767 uint32_t RESERVED5[6U];
kevman 0:38ceb79fef03 768 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
kevman 0:38ceb79fef03 769 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
kevman 0:38ceb79fef03 770 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
kevman 0:38ceb79fef03 771 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
kevman 0:38ceb79fef03 772 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
kevman 0:38ceb79fef03 773 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
kevman 0:38ceb79fef03 774 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
kevman 0:38ceb79fef03 775 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
kevman 0:38ceb79fef03 776 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
kevman 0:38ceb79fef03 777 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
kevman 0:38ceb79fef03 778 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
kevman 0:38ceb79fef03 779 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
kevman 0:38ceb79fef03 780 } ITM_Type;
kevman 0:38ceb79fef03 781
kevman 0:38ceb79fef03 782 /* ITM Trace Privilege Register Definitions */
kevman 0:38ceb79fef03 783 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
kevman 0:38ceb79fef03 784 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
kevman 0:38ceb79fef03 785
kevman 0:38ceb79fef03 786 /* ITM Trace Control Register Definitions */
kevman 0:38ceb79fef03 787 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
kevman 0:38ceb79fef03 788 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
kevman 0:38ceb79fef03 789
kevman 0:38ceb79fef03 790 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
kevman 0:38ceb79fef03 791 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
kevman 0:38ceb79fef03 792
kevman 0:38ceb79fef03 793 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
kevman 0:38ceb79fef03 794 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
kevman 0:38ceb79fef03 795
kevman 0:38ceb79fef03 796 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
kevman 0:38ceb79fef03 797 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
kevman 0:38ceb79fef03 798
kevman 0:38ceb79fef03 799 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
kevman 0:38ceb79fef03 800 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
kevman 0:38ceb79fef03 801
kevman 0:38ceb79fef03 802 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
kevman 0:38ceb79fef03 803 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
kevman 0:38ceb79fef03 804
kevman 0:38ceb79fef03 805 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
kevman 0:38ceb79fef03 806 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
kevman 0:38ceb79fef03 807
kevman 0:38ceb79fef03 808 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
kevman 0:38ceb79fef03 809 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
kevman 0:38ceb79fef03 810
kevman 0:38ceb79fef03 811 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
kevman 0:38ceb79fef03 812 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
kevman 0:38ceb79fef03 813
kevman 0:38ceb79fef03 814 /* ITM Integration Write Register Definitions */
kevman 0:38ceb79fef03 815 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
kevman 0:38ceb79fef03 816 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
kevman 0:38ceb79fef03 817
kevman 0:38ceb79fef03 818 /* ITM Integration Read Register Definitions */
kevman 0:38ceb79fef03 819 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
kevman 0:38ceb79fef03 820 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
kevman 0:38ceb79fef03 821
kevman 0:38ceb79fef03 822 /* ITM Integration Mode Control Register Definitions */
kevman 0:38ceb79fef03 823 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
kevman 0:38ceb79fef03 824 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
kevman 0:38ceb79fef03 825
kevman 0:38ceb79fef03 826 /* ITM Lock Status Register Definitions */
kevman 0:38ceb79fef03 827 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
kevman 0:38ceb79fef03 828 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
kevman 0:38ceb79fef03 829
kevman 0:38ceb79fef03 830 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
kevman 0:38ceb79fef03 831 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
kevman 0:38ceb79fef03 832
kevman 0:38ceb79fef03 833 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
kevman 0:38ceb79fef03 834 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
kevman 0:38ceb79fef03 835
kevman 0:38ceb79fef03 836 /*@}*/ /* end of group CMSIS_ITM */
kevman 0:38ceb79fef03 837
kevman 0:38ceb79fef03 838
kevman 0:38ceb79fef03 839 /**
kevman 0:38ceb79fef03 840 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 841 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
kevman 0:38ceb79fef03 842 \brief Type definitions for the Data Watchpoint and Trace (DWT)
kevman 0:38ceb79fef03 843 @{
kevman 0:38ceb79fef03 844 */
kevman 0:38ceb79fef03 845
kevman 0:38ceb79fef03 846 /**
kevman 0:38ceb79fef03 847 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
kevman 0:38ceb79fef03 848 */
kevman 0:38ceb79fef03 849 typedef struct
kevman 0:38ceb79fef03 850 {
kevman 0:38ceb79fef03 851 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
kevman 0:38ceb79fef03 852 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
kevman 0:38ceb79fef03 853 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
kevman 0:38ceb79fef03 854 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
kevman 0:38ceb79fef03 855 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
kevman 0:38ceb79fef03 856 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
kevman 0:38ceb79fef03 857 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
kevman 0:38ceb79fef03 858 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
kevman 0:38ceb79fef03 859 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
kevman 0:38ceb79fef03 860 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
kevman 0:38ceb79fef03 861 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
kevman 0:38ceb79fef03 862 uint32_t RESERVED0[1U];
kevman 0:38ceb79fef03 863 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
kevman 0:38ceb79fef03 864 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
kevman 0:38ceb79fef03 865 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
kevman 0:38ceb79fef03 866 uint32_t RESERVED1[1U];
kevman 0:38ceb79fef03 867 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
kevman 0:38ceb79fef03 868 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
kevman 0:38ceb79fef03 869 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
kevman 0:38ceb79fef03 870 uint32_t RESERVED2[1U];
kevman 0:38ceb79fef03 871 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
kevman 0:38ceb79fef03 872 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
kevman 0:38ceb79fef03 873 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
kevman 0:38ceb79fef03 874 } DWT_Type;
kevman 0:38ceb79fef03 875
kevman 0:38ceb79fef03 876 /* DWT Control Register Definitions */
kevman 0:38ceb79fef03 877 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
kevman 0:38ceb79fef03 878 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
kevman 0:38ceb79fef03 879
kevman 0:38ceb79fef03 880 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
kevman 0:38ceb79fef03 881 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
kevman 0:38ceb79fef03 882
kevman 0:38ceb79fef03 883 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
kevman 0:38ceb79fef03 884 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
kevman 0:38ceb79fef03 885
kevman 0:38ceb79fef03 886 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
kevman 0:38ceb79fef03 887 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
kevman 0:38ceb79fef03 888
kevman 0:38ceb79fef03 889 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
kevman 0:38ceb79fef03 890 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
kevman 0:38ceb79fef03 891
kevman 0:38ceb79fef03 892 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
kevman 0:38ceb79fef03 893 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
kevman 0:38ceb79fef03 894
kevman 0:38ceb79fef03 895 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
kevman 0:38ceb79fef03 896 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
kevman 0:38ceb79fef03 897
kevman 0:38ceb79fef03 898 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
kevman 0:38ceb79fef03 899 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
kevman 0:38ceb79fef03 900
kevman 0:38ceb79fef03 901 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
kevman 0:38ceb79fef03 902 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
kevman 0:38ceb79fef03 903
kevman 0:38ceb79fef03 904 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
kevman 0:38ceb79fef03 905 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
kevman 0:38ceb79fef03 906
kevman 0:38ceb79fef03 907 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
kevman 0:38ceb79fef03 908 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
kevman 0:38ceb79fef03 909
kevman 0:38ceb79fef03 910 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
kevman 0:38ceb79fef03 911 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
kevman 0:38ceb79fef03 912
kevman 0:38ceb79fef03 913 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
kevman 0:38ceb79fef03 914 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
kevman 0:38ceb79fef03 915
kevman 0:38ceb79fef03 916 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
kevman 0:38ceb79fef03 917 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
kevman 0:38ceb79fef03 918
kevman 0:38ceb79fef03 919 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
kevman 0:38ceb79fef03 920 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
kevman 0:38ceb79fef03 921
kevman 0:38ceb79fef03 922 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
kevman 0:38ceb79fef03 923 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
kevman 0:38ceb79fef03 924
kevman 0:38ceb79fef03 925 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
kevman 0:38ceb79fef03 926 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
kevman 0:38ceb79fef03 927
kevman 0:38ceb79fef03 928 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
kevman 0:38ceb79fef03 929 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
kevman 0:38ceb79fef03 930
kevman 0:38ceb79fef03 931 /* DWT CPI Count Register Definitions */
kevman 0:38ceb79fef03 932 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
kevman 0:38ceb79fef03 933 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
kevman 0:38ceb79fef03 934
kevman 0:38ceb79fef03 935 /* DWT Exception Overhead Count Register Definitions */
kevman 0:38ceb79fef03 936 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
kevman 0:38ceb79fef03 937 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
kevman 0:38ceb79fef03 938
kevman 0:38ceb79fef03 939 /* DWT Sleep Count Register Definitions */
kevman 0:38ceb79fef03 940 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
kevman 0:38ceb79fef03 941 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
kevman 0:38ceb79fef03 942
kevman 0:38ceb79fef03 943 /* DWT LSU Count Register Definitions */
kevman 0:38ceb79fef03 944 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
kevman 0:38ceb79fef03 945 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
kevman 0:38ceb79fef03 946
kevman 0:38ceb79fef03 947 /* DWT Folded-instruction Count Register Definitions */
kevman 0:38ceb79fef03 948 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
kevman 0:38ceb79fef03 949 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
kevman 0:38ceb79fef03 950
kevman 0:38ceb79fef03 951 /* DWT Comparator Mask Register Definitions */
kevman 0:38ceb79fef03 952 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
kevman 0:38ceb79fef03 953 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
kevman 0:38ceb79fef03 954
kevman 0:38ceb79fef03 955 /* DWT Comparator Function Register Definitions */
kevman 0:38ceb79fef03 956 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
kevman 0:38ceb79fef03 957 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
kevman 0:38ceb79fef03 958
kevman 0:38ceb79fef03 959 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
kevman 0:38ceb79fef03 960 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
kevman 0:38ceb79fef03 961
kevman 0:38ceb79fef03 962 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
kevman 0:38ceb79fef03 963 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
kevman 0:38ceb79fef03 964
kevman 0:38ceb79fef03 965 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
kevman 0:38ceb79fef03 966 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
kevman 0:38ceb79fef03 967
kevman 0:38ceb79fef03 968 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
kevman 0:38ceb79fef03 969 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
kevman 0:38ceb79fef03 970
kevman 0:38ceb79fef03 971 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
kevman 0:38ceb79fef03 972 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
kevman 0:38ceb79fef03 973
kevman 0:38ceb79fef03 974 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
kevman 0:38ceb79fef03 975 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
kevman 0:38ceb79fef03 976
kevman 0:38ceb79fef03 977 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
kevman 0:38ceb79fef03 978 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
kevman 0:38ceb79fef03 979
kevman 0:38ceb79fef03 980 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
kevman 0:38ceb79fef03 981 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
kevman 0:38ceb79fef03 982
kevman 0:38ceb79fef03 983 /*@}*/ /* end of group CMSIS_DWT */
kevman 0:38ceb79fef03 984
kevman 0:38ceb79fef03 985
kevman 0:38ceb79fef03 986 /**
kevman 0:38ceb79fef03 987 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 988 \defgroup CMSIS_TPI Trace Port Interface (TPI)
kevman 0:38ceb79fef03 989 \brief Type definitions for the Trace Port Interface (TPI)
kevman 0:38ceb79fef03 990 @{
kevman 0:38ceb79fef03 991 */
kevman 0:38ceb79fef03 992
kevman 0:38ceb79fef03 993 /**
kevman 0:38ceb79fef03 994 \brief Structure type to access the Trace Port Interface Register (TPI).
kevman 0:38ceb79fef03 995 */
kevman 0:38ceb79fef03 996 typedef struct
kevman 0:38ceb79fef03 997 {
kevman 0:38ceb79fef03 998 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
kevman 0:38ceb79fef03 999 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
kevman 0:38ceb79fef03 1000 uint32_t RESERVED0[2U];
kevman 0:38ceb79fef03 1001 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
kevman 0:38ceb79fef03 1002 uint32_t RESERVED1[55U];
kevman 0:38ceb79fef03 1003 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
kevman 0:38ceb79fef03 1004 uint32_t RESERVED2[131U];
kevman 0:38ceb79fef03 1005 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
kevman 0:38ceb79fef03 1006 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
kevman 0:38ceb79fef03 1007 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
kevman 0:38ceb79fef03 1008 uint32_t RESERVED3[759U];
kevman 0:38ceb79fef03 1009 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
kevman 0:38ceb79fef03 1010 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
kevman 0:38ceb79fef03 1011 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
kevman 0:38ceb79fef03 1012 uint32_t RESERVED4[1U];
kevman 0:38ceb79fef03 1013 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
kevman 0:38ceb79fef03 1014 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
kevman 0:38ceb79fef03 1015 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
kevman 0:38ceb79fef03 1016 uint32_t RESERVED5[39U];
kevman 0:38ceb79fef03 1017 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
kevman 0:38ceb79fef03 1018 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
kevman 0:38ceb79fef03 1019 uint32_t RESERVED7[8U];
kevman 0:38ceb79fef03 1020 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
kevman 0:38ceb79fef03 1021 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
kevman 0:38ceb79fef03 1022 } TPI_Type;
kevman 0:38ceb79fef03 1023
kevman 0:38ceb79fef03 1024 /* TPI Asynchronous Clock Prescaler Register Definitions */
kevman 0:38ceb79fef03 1025 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
kevman 0:38ceb79fef03 1026 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
kevman 0:38ceb79fef03 1027
kevman 0:38ceb79fef03 1028 /* TPI Selected Pin Protocol Register Definitions */
kevman 0:38ceb79fef03 1029 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
kevman 0:38ceb79fef03 1030 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
kevman 0:38ceb79fef03 1031
kevman 0:38ceb79fef03 1032 /* TPI Formatter and Flush Status Register Definitions */
kevman 0:38ceb79fef03 1033 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
kevman 0:38ceb79fef03 1034 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
kevman 0:38ceb79fef03 1035
kevman 0:38ceb79fef03 1036 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
kevman 0:38ceb79fef03 1037 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
kevman 0:38ceb79fef03 1038
kevman 0:38ceb79fef03 1039 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
kevman 0:38ceb79fef03 1040 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
kevman 0:38ceb79fef03 1041
kevman 0:38ceb79fef03 1042 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
kevman 0:38ceb79fef03 1043 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
kevman 0:38ceb79fef03 1044
kevman 0:38ceb79fef03 1045 /* TPI Formatter and Flush Control Register Definitions */
kevman 0:38ceb79fef03 1046 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
kevman 0:38ceb79fef03 1047 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
kevman 0:38ceb79fef03 1048
kevman 0:38ceb79fef03 1049 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
kevman 0:38ceb79fef03 1050 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
kevman 0:38ceb79fef03 1051
kevman 0:38ceb79fef03 1052 /* TPI TRIGGER Register Definitions */
kevman 0:38ceb79fef03 1053 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
kevman 0:38ceb79fef03 1054 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
kevman 0:38ceb79fef03 1055
kevman 0:38ceb79fef03 1056 /* TPI Integration ETM Data Register Definitions (FIFO0) */
kevman 0:38ceb79fef03 1057 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
kevman 0:38ceb79fef03 1058 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
kevman 0:38ceb79fef03 1059
kevman 0:38ceb79fef03 1060 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
kevman 0:38ceb79fef03 1061 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
kevman 0:38ceb79fef03 1062
kevman 0:38ceb79fef03 1063 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
kevman 0:38ceb79fef03 1064 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
kevman 0:38ceb79fef03 1065
kevman 0:38ceb79fef03 1066 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
kevman 0:38ceb79fef03 1067 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
kevman 0:38ceb79fef03 1068
kevman 0:38ceb79fef03 1069 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
kevman 0:38ceb79fef03 1070 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
kevman 0:38ceb79fef03 1071
kevman 0:38ceb79fef03 1072 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
kevman 0:38ceb79fef03 1073 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
kevman 0:38ceb79fef03 1074
kevman 0:38ceb79fef03 1075 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
kevman 0:38ceb79fef03 1076 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
kevman 0:38ceb79fef03 1077
kevman 0:38ceb79fef03 1078 /* TPI ITATBCTR2 Register Definitions */
kevman 0:38ceb79fef03 1079 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
kevman 0:38ceb79fef03 1080 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
kevman 0:38ceb79fef03 1081
kevman 0:38ceb79fef03 1082 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
kevman 0:38ceb79fef03 1083 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
kevman 0:38ceb79fef03 1084
kevman 0:38ceb79fef03 1085 /* TPI Integration ITM Data Register Definitions (FIFO1) */
kevman 0:38ceb79fef03 1086 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
kevman 0:38ceb79fef03 1087 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
kevman 0:38ceb79fef03 1088
kevman 0:38ceb79fef03 1089 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
kevman 0:38ceb79fef03 1090 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
kevman 0:38ceb79fef03 1091
kevman 0:38ceb79fef03 1092 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
kevman 0:38ceb79fef03 1093 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
kevman 0:38ceb79fef03 1094
kevman 0:38ceb79fef03 1095 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
kevman 0:38ceb79fef03 1096 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
kevman 0:38ceb79fef03 1097
kevman 0:38ceb79fef03 1098 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
kevman 0:38ceb79fef03 1099 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
kevman 0:38ceb79fef03 1100
kevman 0:38ceb79fef03 1101 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
kevman 0:38ceb79fef03 1102 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
kevman 0:38ceb79fef03 1103
kevman 0:38ceb79fef03 1104 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
kevman 0:38ceb79fef03 1105 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
kevman 0:38ceb79fef03 1106
kevman 0:38ceb79fef03 1107 /* TPI ITATBCTR0 Register Definitions */
kevman 0:38ceb79fef03 1108 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
kevman 0:38ceb79fef03 1109 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
kevman 0:38ceb79fef03 1110
kevman 0:38ceb79fef03 1111 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
kevman 0:38ceb79fef03 1112 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
kevman 0:38ceb79fef03 1113
kevman 0:38ceb79fef03 1114 /* TPI Integration Mode Control Register Definitions */
kevman 0:38ceb79fef03 1115 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
kevman 0:38ceb79fef03 1116 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
kevman 0:38ceb79fef03 1117
kevman 0:38ceb79fef03 1118 /* TPI DEVID Register Definitions */
kevman 0:38ceb79fef03 1119 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
kevman 0:38ceb79fef03 1120 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
kevman 0:38ceb79fef03 1121
kevman 0:38ceb79fef03 1122 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
kevman 0:38ceb79fef03 1123 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
kevman 0:38ceb79fef03 1124
kevman 0:38ceb79fef03 1125 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
kevman 0:38ceb79fef03 1126 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
kevman 0:38ceb79fef03 1127
kevman 0:38ceb79fef03 1128 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
kevman 0:38ceb79fef03 1129 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
kevman 0:38ceb79fef03 1130
kevman 0:38ceb79fef03 1131 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
kevman 0:38ceb79fef03 1132 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
kevman 0:38ceb79fef03 1133
kevman 0:38ceb79fef03 1134 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
kevman 0:38ceb79fef03 1135 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
kevman 0:38ceb79fef03 1136
kevman 0:38ceb79fef03 1137 /* TPI DEVTYPE Register Definitions */
kevman 0:38ceb79fef03 1138 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
kevman 0:38ceb79fef03 1139 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
kevman 0:38ceb79fef03 1140
kevman 0:38ceb79fef03 1141 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
kevman 0:38ceb79fef03 1142 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
kevman 0:38ceb79fef03 1143
kevman 0:38ceb79fef03 1144 /*@}*/ /* end of group CMSIS_TPI */
kevman 0:38ceb79fef03 1145
kevman 0:38ceb79fef03 1146
kevman 0:38ceb79fef03 1147 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman 0:38ceb79fef03 1148 /**
kevman 0:38ceb79fef03 1149 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 1150 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
kevman 0:38ceb79fef03 1151 \brief Type definitions for the Memory Protection Unit (MPU)
kevman 0:38ceb79fef03 1152 @{
kevman 0:38ceb79fef03 1153 */
kevman 0:38ceb79fef03 1154
kevman 0:38ceb79fef03 1155 /**
kevman 0:38ceb79fef03 1156 \brief Structure type to access the Memory Protection Unit (MPU).
kevman 0:38ceb79fef03 1157 */
kevman 0:38ceb79fef03 1158 typedef struct
kevman 0:38ceb79fef03 1159 {
kevman 0:38ceb79fef03 1160 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
kevman 0:38ceb79fef03 1161 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
kevman 0:38ceb79fef03 1162 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
kevman 0:38ceb79fef03 1163 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
kevman 0:38ceb79fef03 1164 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
kevman 0:38ceb79fef03 1165 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
kevman 0:38ceb79fef03 1166 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
kevman 0:38ceb79fef03 1167 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
kevman 0:38ceb79fef03 1168 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
kevman 0:38ceb79fef03 1169 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
kevman 0:38ceb79fef03 1170 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
kevman 0:38ceb79fef03 1171 } MPU_Type;
kevman 0:38ceb79fef03 1172
kevman 0:38ceb79fef03 1173 #define MPU_TYPE_RALIASES 4U
kevman 0:38ceb79fef03 1174
kevman 0:38ceb79fef03 1175 /* MPU Type Register Definitions */
kevman 0:38ceb79fef03 1176 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
kevman 0:38ceb79fef03 1177 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
kevman 0:38ceb79fef03 1178
kevman 0:38ceb79fef03 1179 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
kevman 0:38ceb79fef03 1180 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
kevman 0:38ceb79fef03 1181
kevman 0:38ceb79fef03 1182 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
kevman 0:38ceb79fef03 1183 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
kevman 0:38ceb79fef03 1184
kevman 0:38ceb79fef03 1185 /* MPU Control Register Definitions */
kevman 0:38ceb79fef03 1186 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
kevman 0:38ceb79fef03 1187 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
kevman 0:38ceb79fef03 1188
kevman 0:38ceb79fef03 1189 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
kevman 0:38ceb79fef03 1190 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
kevman 0:38ceb79fef03 1191
kevman 0:38ceb79fef03 1192 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
kevman 0:38ceb79fef03 1193 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
kevman 0:38ceb79fef03 1194
kevman 0:38ceb79fef03 1195 /* MPU Region Number Register Definitions */
kevman 0:38ceb79fef03 1196 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
kevman 0:38ceb79fef03 1197 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
kevman 0:38ceb79fef03 1198
kevman 0:38ceb79fef03 1199 /* MPU Region Base Address Register Definitions */
kevman 0:38ceb79fef03 1200 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
kevman 0:38ceb79fef03 1201 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
kevman 0:38ceb79fef03 1202
kevman 0:38ceb79fef03 1203 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
kevman 0:38ceb79fef03 1204 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
kevman 0:38ceb79fef03 1205
kevman 0:38ceb79fef03 1206 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
kevman 0:38ceb79fef03 1207 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
kevman 0:38ceb79fef03 1208
kevman 0:38ceb79fef03 1209 /* MPU Region Attribute and Size Register Definitions */
kevman 0:38ceb79fef03 1210 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
kevman 0:38ceb79fef03 1211 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
kevman 0:38ceb79fef03 1212
kevman 0:38ceb79fef03 1213 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
kevman 0:38ceb79fef03 1214 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
kevman 0:38ceb79fef03 1215
kevman 0:38ceb79fef03 1216 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
kevman 0:38ceb79fef03 1217 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
kevman 0:38ceb79fef03 1218
kevman 0:38ceb79fef03 1219 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
kevman 0:38ceb79fef03 1220 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
kevman 0:38ceb79fef03 1221
kevman 0:38ceb79fef03 1222 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
kevman 0:38ceb79fef03 1223 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
kevman 0:38ceb79fef03 1224
kevman 0:38ceb79fef03 1225 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
kevman 0:38ceb79fef03 1226 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
kevman 0:38ceb79fef03 1227
kevman 0:38ceb79fef03 1228 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
kevman 0:38ceb79fef03 1229 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
kevman 0:38ceb79fef03 1230
kevman 0:38ceb79fef03 1231 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
kevman 0:38ceb79fef03 1232 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
kevman 0:38ceb79fef03 1233
kevman 0:38ceb79fef03 1234 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
kevman 0:38ceb79fef03 1235 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
kevman 0:38ceb79fef03 1236
kevman 0:38ceb79fef03 1237 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
kevman 0:38ceb79fef03 1238 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
kevman 0:38ceb79fef03 1239
kevman 0:38ceb79fef03 1240 /*@} end of group CMSIS_MPU */
kevman 0:38ceb79fef03 1241 #endif
kevman 0:38ceb79fef03 1242
kevman 0:38ceb79fef03 1243
kevman 0:38ceb79fef03 1244 /**
kevman 0:38ceb79fef03 1245 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 1246 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
kevman 0:38ceb79fef03 1247 \brief Type definitions for the Core Debug Registers
kevman 0:38ceb79fef03 1248 @{
kevman 0:38ceb79fef03 1249 */
kevman 0:38ceb79fef03 1250
kevman 0:38ceb79fef03 1251 /**
kevman 0:38ceb79fef03 1252 \brief Structure type to access the Core Debug Register (CoreDebug).
kevman 0:38ceb79fef03 1253 */
kevman 0:38ceb79fef03 1254 typedef struct
kevman 0:38ceb79fef03 1255 {
kevman 0:38ceb79fef03 1256 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
kevman 0:38ceb79fef03 1257 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
kevman 0:38ceb79fef03 1258 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
kevman 0:38ceb79fef03 1259 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
kevman 0:38ceb79fef03 1260 } CoreDebug_Type;
kevman 0:38ceb79fef03 1261
kevman 0:38ceb79fef03 1262 /* Debug Halting Control and Status Register Definitions */
kevman 0:38ceb79fef03 1263 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
kevman 0:38ceb79fef03 1264 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
kevman 0:38ceb79fef03 1265
kevman 0:38ceb79fef03 1266 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
kevman 0:38ceb79fef03 1267 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
kevman 0:38ceb79fef03 1268
kevman 0:38ceb79fef03 1269 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
kevman 0:38ceb79fef03 1270 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
kevman 0:38ceb79fef03 1271
kevman 0:38ceb79fef03 1272 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
kevman 0:38ceb79fef03 1273 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
kevman 0:38ceb79fef03 1274
kevman 0:38ceb79fef03 1275 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
kevman 0:38ceb79fef03 1276 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
kevman 0:38ceb79fef03 1277
kevman 0:38ceb79fef03 1278 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
kevman 0:38ceb79fef03 1279 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
kevman 0:38ceb79fef03 1280
kevman 0:38ceb79fef03 1281 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
kevman 0:38ceb79fef03 1282 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
kevman 0:38ceb79fef03 1283
kevman 0:38ceb79fef03 1284 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
kevman 0:38ceb79fef03 1285 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
kevman 0:38ceb79fef03 1286
kevman 0:38ceb79fef03 1287 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
kevman 0:38ceb79fef03 1288 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
kevman 0:38ceb79fef03 1289
kevman 0:38ceb79fef03 1290 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
kevman 0:38ceb79fef03 1291 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
kevman 0:38ceb79fef03 1292
kevman 0:38ceb79fef03 1293 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
kevman 0:38ceb79fef03 1294 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
kevman 0:38ceb79fef03 1295
kevman 0:38ceb79fef03 1296 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
kevman 0:38ceb79fef03 1297 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
kevman 0:38ceb79fef03 1298
kevman 0:38ceb79fef03 1299 /* Debug Core Register Selector Register Definitions */
kevman 0:38ceb79fef03 1300 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
kevman 0:38ceb79fef03 1301 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
kevman 0:38ceb79fef03 1302
kevman 0:38ceb79fef03 1303 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
kevman 0:38ceb79fef03 1304 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
kevman 0:38ceb79fef03 1305
kevman 0:38ceb79fef03 1306 /* Debug Exception and Monitor Control Register Definitions */
kevman 0:38ceb79fef03 1307 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
kevman 0:38ceb79fef03 1308 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
kevman 0:38ceb79fef03 1309
kevman 0:38ceb79fef03 1310 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
kevman 0:38ceb79fef03 1311 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
kevman 0:38ceb79fef03 1312
kevman 0:38ceb79fef03 1313 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
kevman 0:38ceb79fef03 1314 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
kevman 0:38ceb79fef03 1315
kevman 0:38ceb79fef03 1316 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
kevman 0:38ceb79fef03 1317 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
kevman 0:38ceb79fef03 1318
kevman 0:38ceb79fef03 1319 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
kevman 0:38ceb79fef03 1320 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
kevman 0:38ceb79fef03 1321
kevman 0:38ceb79fef03 1322 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
kevman 0:38ceb79fef03 1323 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
kevman 0:38ceb79fef03 1324
kevman 0:38ceb79fef03 1325 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
kevman 0:38ceb79fef03 1326 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
kevman 0:38ceb79fef03 1327
kevman 0:38ceb79fef03 1328 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
kevman 0:38ceb79fef03 1329 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
kevman 0:38ceb79fef03 1330
kevman 0:38ceb79fef03 1331 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
kevman 0:38ceb79fef03 1332 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
kevman 0:38ceb79fef03 1333
kevman 0:38ceb79fef03 1334 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
kevman 0:38ceb79fef03 1335 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
kevman 0:38ceb79fef03 1336
kevman 0:38ceb79fef03 1337 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
kevman 0:38ceb79fef03 1338 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
kevman 0:38ceb79fef03 1339
kevman 0:38ceb79fef03 1340 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
kevman 0:38ceb79fef03 1341 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
kevman 0:38ceb79fef03 1342
kevman 0:38ceb79fef03 1343 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
kevman 0:38ceb79fef03 1344 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
kevman 0:38ceb79fef03 1345
kevman 0:38ceb79fef03 1346 /*@} end of group CMSIS_CoreDebug */
kevman 0:38ceb79fef03 1347
kevman 0:38ceb79fef03 1348
kevman 0:38ceb79fef03 1349 /**
kevman 0:38ceb79fef03 1350 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 1351 \defgroup CMSIS_core_bitfield Core register bit field macros
kevman 0:38ceb79fef03 1352 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
kevman 0:38ceb79fef03 1353 @{
kevman 0:38ceb79fef03 1354 */
kevman 0:38ceb79fef03 1355
kevman 0:38ceb79fef03 1356 /**
kevman 0:38ceb79fef03 1357 \brief Mask and shift a bit field value for use in a register bit range.
kevman 0:38ceb79fef03 1358 \param[in] field Name of the register bit field.
kevman 0:38ceb79fef03 1359 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
kevman 0:38ceb79fef03 1360 \return Masked and shifted value.
kevman 0:38ceb79fef03 1361 */
kevman 0:38ceb79fef03 1362 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
kevman 0:38ceb79fef03 1363
kevman 0:38ceb79fef03 1364 /**
kevman 0:38ceb79fef03 1365 \brief Mask and shift a register value to extract a bit filed value.
kevman 0:38ceb79fef03 1366 \param[in] field Name of the register bit field.
kevman 0:38ceb79fef03 1367 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
kevman 0:38ceb79fef03 1368 \return Masked and shifted bit field value.
kevman 0:38ceb79fef03 1369 */
kevman 0:38ceb79fef03 1370 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
kevman 0:38ceb79fef03 1371
kevman 0:38ceb79fef03 1372 /*@} end of group CMSIS_core_bitfield */
kevman 0:38ceb79fef03 1373
kevman 0:38ceb79fef03 1374
kevman 0:38ceb79fef03 1375 /**
kevman 0:38ceb79fef03 1376 \ingroup CMSIS_core_register
kevman 0:38ceb79fef03 1377 \defgroup CMSIS_core_base Core Definitions
kevman 0:38ceb79fef03 1378 \brief Definitions for base addresses, unions, and structures.
kevman 0:38ceb79fef03 1379 @{
kevman 0:38ceb79fef03 1380 */
kevman 0:38ceb79fef03 1381
kevman 0:38ceb79fef03 1382 /* Memory mapping of Core Hardware */
kevman 0:38ceb79fef03 1383 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
kevman 0:38ceb79fef03 1384 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
kevman 0:38ceb79fef03 1385 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
kevman 0:38ceb79fef03 1386 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
kevman 0:38ceb79fef03 1387 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
kevman 0:38ceb79fef03 1388 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
kevman 0:38ceb79fef03 1389 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
kevman 0:38ceb79fef03 1390 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
kevman 0:38ceb79fef03 1391
kevman 0:38ceb79fef03 1392 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
kevman 0:38ceb79fef03 1393 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
kevman 0:38ceb79fef03 1394 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
kevman 0:38ceb79fef03 1395 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
kevman 0:38ceb79fef03 1396 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
kevman 0:38ceb79fef03 1397 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
kevman 0:38ceb79fef03 1398 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
kevman 0:38ceb79fef03 1399 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
kevman 0:38ceb79fef03 1400
kevman 0:38ceb79fef03 1401 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman 0:38ceb79fef03 1402 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
kevman 0:38ceb79fef03 1403 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
kevman 0:38ceb79fef03 1404 #endif
kevman 0:38ceb79fef03 1405
kevman 0:38ceb79fef03 1406 /*@} */
kevman 0:38ceb79fef03 1407
kevman 0:38ceb79fef03 1408
kevman 0:38ceb79fef03 1409
kevman 0:38ceb79fef03 1410 /*******************************************************************************
kevman 0:38ceb79fef03 1411 * Hardware Abstraction Layer
kevman 0:38ceb79fef03 1412 Core Function Interface contains:
kevman 0:38ceb79fef03 1413 - Core NVIC Functions
kevman 0:38ceb79fef03 1414 - Core SysTick Functions
kevman 0:38ceb79fef03 1415 - Core Debug Functions
kevman 0:38ceb79fef03 1416 - Core Register Access Functions
kevman 0:38ceb79fef03 1417 ******************************************************************************/
kevman 0:38ceb79fef03 1418 /**
kevman 0:38ceb79fef03 1419 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
kevman 0:38ceb79fef03 1420 */
kevman 0:38ceb79fef03 1421
kevman 0:38ceb79fef03 1422
kevman 0:38ceb79fef03 1423
kevman 0:38ceb79fef03 1424 /* ########################## NVIC functions #################################### */
kevman 0:38ceb79fef03 1425 /**
kevman 0:38ceb79fef03 1426 \ingroup CMSIS_Core_FunctionInterface
kevman 0:38ceb79fef03 1427 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
kevman 0:38ceb79fef03 1428 \brief Functions that manage interrupts and exceptions via the NVIC.
kevman 0:38ceb79fef03 1429 @{
kevman 0:38ceb79fef03 1430 */
kevman 0:38ceb79fef03 1431
kevman 0:38ceb79fef03 1432 #ifdef CMSIS_NVIC_VIRTUAL
kevman 0:38ceb79fef03 1433 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
kevman 0:38ceb79fef03 1434 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
kevman 0:38ceb79fef03 1435 #endif
kevman 0:38ceb79fef03 1436 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
kevman 0:38ceb79fef03 1437 #else
kevman 0:38ceb79fef03 1438 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
kevman 0:38ceb79fef03 1439 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
kevman 0:38ceb79fef03 1440 #define NVIC_EnableIRQ __NVIC_EnableIRQ
kevman 0:38ceb79fef03 1441 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
kevman 0:38ceb79fef03 1442 #define NVIC_DisableIRQ __NVIC_DisableIRQ
kevman 0:38ceb79fef03 1443 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
kevman 0:38ceb79fef03 1444 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
kevman 0:38ceb79fef03 1445 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
kevman 0:38ceb79fef03 1446 #define NVIC_GetActive __NVIC_GetActive
kevman 0:38ceb79fef03 1447 #define NVIC_SetPriority __NVIC_SetPriority
kevman 0:38ceb79fef03 1448 #define NVIC_GetPriority __NVIC_GetPriority
kevman 0:38ceb79fef03 1449 #define NVIC_SystemReset __NVIC_SystemReset
kevman 0:38ceb79fef03 1450 #endif /* CMSIS_NVIC_VIRTUAL */
kevman 0:38ceb79fef03 1451
kevman 0:38ceb79fef03 1452 #ifdef CMSIS_VECTAB_VIRTUAL
kevman 0:38ceb79fef03 1453 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kevman 0:38ceb79fef03 1454 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
kevman 0:38ceb79fef03 1455 #endif
kevman 0:38ceb79fef03 1456 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
kevman 0:38ceb79fef03 1457 #else
kevman 0:38ceb79fef03 1458 #define NVIC_SetVector __NVIC_SetVector
kevman 0:38ceb79fef03 1459 #define NVIC_GetVector __NVIC_GetVector
kevman 0:38ceb79fef03 1460 #endif /* (CMSIS_VECTAB_VIRTUAL) */
kevman 0:38ceb79fef03 1461
kevman 0:38ceb79fef03 1462 #define NVIC_USER_IRQ_OFFSET 16
kevman 0:38ceb79fef03 1463
kevman 0:38ceb79fef03 1464
kevman 0:38ceb79fef03 1465 /* The following EXC_RETURN values are saved the LR on exception entry */
kevman 0:38ceb79fef03 1466 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
kevman 0:38ceb79fef03 1467 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
kevman 0:38ceb79fef03 1468 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
kevman 0:38ceb79fef03 1469
kevman 0:38ceb79fef03 1470
kevman 0:38ceb79fef03 1471 /**
kevman 0:38ceb79fef03 1472 \brief Set Priority Grouping
kevman 0:38ceb79fef03 1473 \details Sets the priority grouping field using the required unlock sequence.
kevman 0:38ceb79fef03 1474 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
kevman 0:38ceb79fef03 1475 Only values from 0..7 are used.
kevman 0:38ceb79fef03 1476 In case of a conflict between priority grouping and available
kevman 0:38ceb79fef03 1477 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kevman 0:38ceb79fef03 1478 \param [in] PriorityGroup Priority grouping field.
kevman 0:38ceb79fef03 1479 */
kevman 0:38ceb79fef03 1480 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
kevman 0:38ceb79fef03 1481 {
kevman 0:38ceb79fef03 1482 uint32_t reg_value;
kevman 0:38ceb79fef03 1483 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kevman 0:38ceb79fef03 1484
kevman 0:38ceb79fef03 1485 reg_value = SCB->AIRCR; /* read old register configuration */
kevman 0:38ceb79fef03 1486 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
kevman 0:38ceb79fef03 1487 reg_value = (reg_value |
kevman 0:38ceb79fef03 1488 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
kevman 0:38ceb79fef03 1489 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
kevman 0:38ceb79fef03 1490 SCB->AIRCR = reg_value;
kevman 0:38ceb79fef03 1491 }
kevman 0:38ceb79fef03 1492
kevman 0:38ceb79fef03 1493
kevman 0:38ceb79fef03 1494 /**
kevman 0:38ceb79fef03 1495 \brief Get Priority Grouping
kevman 0:38ceb79fef03 1496 \details Reads the priority grouping field from the NVIC Interrupt Controller.
kevman 0:38ceb79fef03 1497 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
kevman 0:38ceb79fef03 1498 */
kevman 0:38ceb79fef03 1499 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
kevman 0:38ceb79fef03 1500 {
kevman 0:38ceb79fef03 1501 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
kevman 0:38ceb79fef03 1502 }
kevman 0:38ceb79fef03 1503
kevman 0:38ceb79fef03 1504
kevman 0:38ceb79fef03 1505 /**
kevman 0:38ceb79fef03 1506 \brief Enable Interrupt
kevman 0:38ceb79fef03 1507 \details Enables a device specific interrupt in the NVIC interrupt controller.
kevman 0:38ceb79fef03 1508 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 1509 \note IRQn must not be negative.
kevman 0:38ceb79fef03 1510 */
kevman 0:38ceb79fef03 1511 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1512 {
kevman 0:38ceb79fef03 1513 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1514 {
kevman 0:38ceb79fef03 1515 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman 0:38ceb79fef03 1516 }
kevman 0:38ceb79fef03 1517 }
kevman 0:38ceb79fef03 1518
kevman 0:38ceb79fef03 1519
kevman 0:38ceb79fef03 1520 /**
kevman 0:38ceb79fef03 1521 \brief Get Interrupt Enable status
kevman 0:38ceb79fef03 1522 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
kevman 0:38ceb79fef03 1523 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 1524 \return 0 Interrupt is not enabled.
kevman 0:38ceb79fef03 1525 \return 1 Interrupt is enabled.
kevman 0:38ceb79fef03 1526 \note IRQn must not be negative.
kevman 0:38ceb79fef03 1527 */
kevman 0:38ceb79fef03 1528 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1529 {
kevman 0:38ceb79fef03 1530 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1531 {
kevman 0:38ceb79fef03 1532 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman 0:38ceb79fef03 1533 }
kevman 0:38ceb79fef03 1534 else
kevman 0:38ceb79fef03 1535 {
kevman 0:38ceb79fef03 1536 return(0U);
kevman 0:38ceb79fef03 1537 }
kevman 0:38ceb79fef03 1538 }
kevman 0:38ceb79fef03 1539
kevman 0:38ceb79fef03 1540
kevman 0:38ceb79fef03 1541 /**
kevman 0:38ceb79fef03 1542 \brief Disable Interrupt
kevman 0:38ceb79fef03 1543 \details Disables a device specific interrupt in the NVIC interrupt controller.
kevman 0:38ceb79fef03 1544 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 1545 \note IRQn must not be negative.
kevman 0:38ceb79fef03 1546 */
kevman 0:38ceb79fef03 1547 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1548 {
kevman 0:38ceb79fef03 1549 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1550 {
kevman 0:38ceb79fef03 1551 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman 0:38ceb79fef03 1552 __DSB();
kevman 0:38ceb79fef03 1553 __ISB();
kevman 0:38ceb79fef03 1554 }
kevman 0:38ceb79fef03 1555 }
kevman 0:38ceb79fef03 1556
kevman 0:38ceb79fef03 1557
kevman 0:38ceb79fef03 1558 /**
kevman 0:38ceb79fef03 1559 \brief Get Pending Interrupt
kevman 0:38ceb79fef03 1560 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
kevman 0:38ceb79fef03 1561 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 1562 \return 0 Interrupt status is not pending.
kevman 0:38ceb79fef03 1563 \return 1 Interrupt status is pending.
kevman 0:38ceb79fef03 1564 \note IRQn must not be negative.
kevman 0:38ceb79fef03 1565 */
kevman 0:38ceb79fef03 1566 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1567 {
kevman 0:38ceb79fef03 1568 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1569 {
kevman 0:38ceb79fef03 1570 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman 0:38ceb79fef03 1571 }
kevman 0:38ceb79fef03 1572 else
kevman 0:38ceb79fef03 1573 {
kevman 0:38ceb79fef03 1574 return(0U);
kevman 0:38ceb79fef03 1575 }
kevman 0:38ceb79fef03 1576 }
kevman 0:38ceb79fef03 1577
kevman 0:38ceb79fef03 1578
kevman 0:38ceb79fef03 1579 /**
kevman 0:38ceb79fef03 1580 \brief Set Pending Interrupt
kevman 0:38ceb79fef03 1581 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
kevman 0:38ceb79fef03 1582 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 1583 \note IRQn must not be negative.
kevman 0:38ceb79fef03 1584 */
kevman 0:38ceb79fef03 1585 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1586 {
kevman 0:38ceb79fef03 1587 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1588 {
kevman 0:38ceb79fef03 1589 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman 0:38ceb79fef03 1590 }
kevman 0:38ceb79fef03 1591 }
kevman 0:38ceb79fef03 1592
kevman 0:38ceb79fef03 1593
kevman 0:38ceb79fef03 1594 /**
kevman 0:38ceb79fef03 1595 \brief Clear Pending Interrupt
kevman 0:38ceb79fef03 1596 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
kevman 0:38ceb79fef03 1597 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 1598 \note IRQn must not be negative.
kevman 0:38ceb79fef03 1599 */
kevman 0:38ceb79fef03 1600 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1601 {
kevman 0:38ceb79fef03 1602 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1603 {
kevman 0:38ceb79fef03 1604 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
kevman 0:38ceb79fef03 1605 }
kevman 0:38ceb79fef03 1606 }
kevman 0:38ceb79fef03 1607
kevman 0:38ceb79fef03 1608
kevman 0:38ceb79fef03 1609 /**
kevman 0:38ceb79fef03 1610 \brief Get Active Interrupt
kevman 0:38ceb79fef03 1611 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
kevman 0:38ceb79fef03 1612 \param [in] IRQn Device specific interrupt number.
kevman 0:38ceb79fef03 1613 \return 0 Interrupt status is not active.
kevman 0:38ceb79fef03 1614 \return 1 Interrupt status is active.
kevman 0:38ceb79fef03 1615 \note IRQn must not be negative.
kevman 0:38ceb79fef03 1616 */
kevman 0:38ceb79fef03 1617 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1618 {
kevman 0:38ceb79fef03 1619 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1620 {
kevman 0:38ceb79fef03 1621 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
kevman 0:38ceb79fef03 1622 }
kevman 0:38ceb79fef03 1623 else
kevman 0:38ceb79fef03 1624 {
kevman 0:38ceb79fef03 1625 return(0U);
kevman 0:38ceb79fef03 1626 }
kevman 0:38ceb79fef03 1627 }
kevman 0:38ceb79fef03 1628
kevman 0:38ceb79fef03 1629
kevman 0:38ceb79fef03 1630 /**
kevman 0:38ceb79fef03 1631 \brief Set Interrupt Priority
kevman 0:38ceb79fef03 1632 \details Sets the priority of a device specific interrupt or a processor exception.
kevman 0:38ceb79fef03 1633 The interrupt number can be positive to specify a device specific interrupt,
kevman 0:38ceb79fef03 1634 or negative to specify a processor exception.
kevman 0:38ceb79fef03 1635 \param [in] IRQn Interrupt number.
kevman 0:38ceb79fef03 1636 \param [in] priority Priority to set.
kevman 0:38ceb79fef03 1637 \note The priority cannot be set for every processor exception.
kevman 0:38ceb79fef03 1638 */
kevman 0:38ceb79fef03 1639 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
kevman 0:38ceb79fef03 1640 {
kevman 0:38ceb79fef03 1641 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1642 {
kevman 0:38ceb79fef03 1643 NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kevman 0:38ceb79fef03 1644 }
kevman 0:38ceb79fef03 1645 else
kevman 0:38ceb79fef03 1646 {
kevman 0:38ceb79fef03 1647 SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
kevman 0:38ceb79fef03 1648 }
kevman 0:38ceb79fef03 1649 }
kevman 0:38ceb79fef03 1650
kevman 0:38ceb79fef03 1651
kevman 0:38ceb79fef03 1652 /**
kevman 0:38ceb79fef03 1653 \brief Get Interrupt Priority
kevman 0:38ceb79fef03 1654 \details Reads the priority of a device specific interrupt or a processor exception.
kevman 0:38ceb79fef03 1655 The interrupt number can be positive to specify a device specific interrupt,
kevman 0:38ceb79fef03 1656 or negative to specify a processor exception.
kevman 0:38ceb79fef03 1657 \param [in] IRQn Interrupt number.
kevman 0:38ceb79fef03 1658 \return Interrupt Priority.
kevman 0:38ceb79fef03 1659 Value is aligned automatically to the implemented priority bits of the microcontroller.
kevman 0:38ceb79fef03 1660 */
kevman 0:38ceb79fef03 1661 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1662 {
kevman 0:38ceb79fef03 1663
kevman 0:38ceb79fef03 1664 if ((int32_t)(IRQn) >= 0)
kevman 0:38ceb79fef03 1665 {
kevman 0:38ceb79fef03 1666 return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
kevman 0:38ceb79fef03 1667 }
kevman 0:38ceb79fef03 1668 else
kevman 0:38ceb79fef03 1669 {
kevman 0:38ceb79fef03 1670 return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
kevman 0:38ceb79fef03 1671 }
kevman 0:38ceb79fef03 1672 }
kevman 0:38ceb79fef03 1673
kevman 0:38ceb79fef03 1674
kevman 0:38ceb79fef03 1675 /**
kevman 0:38ceb79fef03 1676 \brief Encode Priority
kevman 0:38ceb79fef03 1677 \details Encodes the priority for an interrupt with the given priority group,
kevman 0:38ceb79fef03 1678 preemptive priority value, and subpriority value.
kevman 0:38ceb79fef03 1679 In case of a conflict between priority grouping and available
kevman 0:38ceb79fef03 1680 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
kevman 0:38ceb79fef03 1681 \param [in] PriorityGroup Used priority group.
kevman 0:38ceb79fef03 1682 \param [in] PreemptPriority Preemptive priority value (starting from 0).
kevman 0:38ceb79fef03 1683 \param [in] SubPriority Subpriority value (starting from 0).
kevman 0:38ceb79fef03 1684 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
kevman 0:38ceb79fef03 1685 */
kevman 0:38ceb79fef03 1686 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
kevman 0:38ceb79fef03 1687 {
kevman 0:38ceb79fef03 1688 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kevman 0:38ceb79fef03 1689 uint32_t PreemptPriorityBits;
kevman 0:38ceb79fef03 1690 uint32_t SubPriorityBits;
kevman 0:38ceb79fef03 1691
kevman 0:38ceb79fef03 1692 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kevman 0:38ceb79fef03 1693 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kevman 0:38ceb79fef03 1694
kevman 0:38ceb79fef03 1695 return (
kevman 0:38ceb79fef03 1696 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
kevman 0:38ceb79fef03 1697 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
kevman 0:38ceb79fef03 1698 );
kevman 0:38ceb79fef03 1699 }
kevman 0:38ceb79fef03 1700
kevman 0:38ceb79fef03 1701
kevman 0:38ceb79fef03 1702 /**
kevman 0:38ceb79fef03 1703 \brief Decode Priority
kevman 0:38ceb79fef03 1704 \details Decodes an interrupt priority value with a given priority group to
kevman 0:38ceb79fef03 1705 preemptive priority value and subpriority value.
kevman 0:38ceb79fef03 1706 In case of a conflict between priority grouping and available
kevman 0:38ceb79fef03 1707 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
kevman 0:38ceb79fef03 1708 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
kevman 0:38ceb79fef03 1709 \param [in] PriorityGroup Used priority group.
kevman 0:38ceb79fef03 1710 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
kevman 0:38ceb79fef03 1711 \param [out] pSubPriority Subpriority value (starting from 0).
kevman 0:38ceb79fef03 1712 */
kevman 0:38ceb79fef03 1713 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
kevman 0:38ceb79fef03 1714 {
kevman 0:38ceb79fef03 1715 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
kevman 0:38ceb79fef03 1716 uint32_t PreemptPriorityBits;
kevman 0:38ceb79fef03 1717 uint32_t SubPriorityBits;
kevman 0:38ceb79fef03 1718
kevman 0:38ceb79fef03 1719 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
kevman 0:38ceb79fef03 1720 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
kevman 0:38ceb79fef03 1721
kevman 0:38ceb79fef03 1722 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
kevman 0:38ceb79fef03 1723 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
kevman 0:38ceb79fef03 1724 }
kevman 0:38ceb79fef03 1725
kevman 0:38ceb79fef03 1726
kevman 0:38ceb79fef03 1727 /**
kevman 0:38ceb79fef03 1728 \brief Set Interrupt Vector
kevman 0:38ceb79fef03 1729 \details Sets an interrupt vector in SRAM based interrupt vector table.
kevman 0:38ceb79fef03 1730 The interrupt number can be positive to specify a device specific interrupt,
kevman 0:38ceb79fef03 1731 or negative to specify a processor exception.
kevman 0:38ceb79fef03 1732 VTOR must been relocated to SRAM before.
kevman 0:38ceb79fef03 1733 \param [in] IRQn Interrupt number
kevman 0:38ceb79fef03 1734 \param [in] vector Address of interrupt handler function
kevman 0:38ceb79fef03 1735 */
kevman 0:38ceb79fef03 1736 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
kevman 0:38ceb79fef03 1737 {
kevman 0:38ceb79fef03 1738 uint32_t *vectors = (uint32_t *)SCB->VTOR;
kevman 0:38ceb79fef03 1739 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
kevman 0:38ceb79fef03 1740 }
kevman 0:38ceb79fef03 1741
kevman 0:38ceb79fef03 1742
kevman 0:38ceb79fef03 1743 /**
kevman 0:38ceb79fef03 1744 \brief Get Interrupt Vector
kevman 0:38ceb79fef03 1745 \details Reads an interrupt vector from interrupt vector table.
kevman 0:38ceb79fef03 1746 The interrupt number can be positive to specify a device specific interrupt,
kevman 0:38ceb79fef03 1747 or negative to specify a processor exception.
kevman 0:38ceb79fef03 1748 \param [in] IRQn Interrupt number.
kevman 0:38ceb79fef03 1749 \return Address of interrupt handler function
kevman 0:38ceb79fef03 1750 */
kevman 0:38ceb79fef03 1751 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
kevman 0:38ceb79fef03 1752 {
kevman 0:38ceb79fef03 1753 uint32_t *vectors = (uint32_t *)SCB->VTOR;
kevman 0:38ceb79fef03 1754 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
kevman 0:38ceb79fef03 1755 }
kevman 0:38ceb79fef03 1756
kevman 0:38ceb79fef03 1757
kevman 0:38ceb79fef03 1758 /**
kevman 0:38ceb79fef03 1759 \brief System Reset
kevman 0:38ceb79fef03 1760 \details Initiates a system reset request to reset the MCU.
kevman 0:38ceb79fef03 1761 */
kevman 0:38ceb79fef03 1762 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
kevman 0:38ceb79fef03 1763 {
kevman 0:38ceb79fef03 1764 __DSB(); /* Ensure all outstanding memory accesses included
kevman 0:38ceb79fef03 1765 buffered write are completed before reset */
kevman 0:38ceb79fef03 1766 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
kevman 0:38ceb79fef03 1767 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
kevman 0:38ceb79fef03 1768 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
kevman 0:38ceb79fef03 1769 __DSB(); /* Ensure completion of memory access */
kevman 0:38ceb79fef03 1770
kevman 0:38ceb79fef03 1771 for(;;) /* wait until reset */
kevman 0:38ceb79fef03 1772 {
kevman 0:38ceb79fef03 1773 __NOP();
kevman 0:38ceb79fef03 1774 }
kevman 0:38ceb79fef03 1775 }
kevman 0:38ceb79fef03 1776
kevman 0:38ceb79fef03 1777 /*@} end of CMSIS_Core_NVICFunctions */
kevman 0:38ceb79fef03 1778
kevman 0:38ceb79fef03 1779 /* ########################## MPU functions #################################### */
kevman 0:38ceb79fef03 1780
kevman 0:38ceb79fef03 1781 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
kevman 0:38ceb79fef03 1782
kevman 0:38ceb79fef03 1783 #include "mpu_armv7.h"
kevman 0:38ceb79fef03 1784
kevman 0:38ceb79fef03 1785 #endif
kevman 0:38ceb79fef03 1786
kevman 0:38ceb79fef03 1787 /* ########################## FPU functions #################################### */
kevman 0:38ceb79fef03 1788 /**
kevman 0:38ceb79fef03 1789 \ingroup CMSIS_Core_FunctionInterface
kevman 0:38ceb79fef03 1790 \defgroup CMSIS_Core_FpuFunctions FPU Functions
kevman 0:38ceb79fef03 1791 \brief Function that provides FPU type.
kevman 0:38ceb79fef03 1792 @{
kevman 0:38ceb79fef03 1793 */
kevman 0:38ceb79fef03 1794
kevman 0:38ceb79fef03 1795 /**
kevman 0:38ceb79fef03 1796 \brief get FPU type
kevman 0:38ceb79fef03 1797 \details returns the FPU type
kevman 0:38ceb79fef03 1798 \returns
kevman 0:38ceb79fef03 1799 - \b 0: No FPU
kevman 0:38ceb79fef03 1800 - \b 1: Single precision FPU
kevman 0:38ceb79fef03 1801 - \b 2: Double + Single precision FPU
kevman 0:38ceb79fef03 1802 */
kevman 0:38ceb79fef03 1803 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
kevman 0:38ceb79fef03 1804 {
kevman 0:38ceb79fef03 1805 return 0U; /* No FPU */
kevman 0:38ceb79fef03 1806 }
kevman 0:38ceb79fef03 1807
kevman 0:38ceb79fef03 1808
kevman 0:38ceb79fef03 1809 /*@} end of CMSIS_Core_FpuFunctions */
kevman 0:38ceb79fef03 1810
kevman 0:38ceb79fef03 1811
kevman 0:38ceb79fef03 1812
kevman 0:38ceb79fef03 1813 /* ################################## SysTick function ############################################ */
kevman 0:38ceb79fef03 1814 /**
kevman 0:38ceb79fef03 1815 \ingroup CMSIS_Core_FunctionInterface
kevman 0:38ceb79fef03 1816 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
kevman 0:38ceb79fef03 1817 \brief Functions that configure the System.
kevman 0:38ceb79fef03 1818 @{
kevman 0:38ceb79fef03 1819 */
kevman 0:38ceb79fef03 1820
kevman 0:38ceb79fef03 1821 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
kevman 0:38ceb79fef03 1822
kevman 0:38ceb79fef03 1823 /**
kevman 0:38ceb79fef03 1824 \brief System Tick Configuration
kevman 0:38ceb79fef03 1825 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
kevman 0:38ceb79fef03 1826 Counter is in free running mode to generate periodic interrupts.
kevman 0:38ceb79fef03 1827 \param [in] ticks Number of ticks between two interrupts.
kevman 0:38ceb79fef03 1828 \return 0 Function succeeded.
kevman 0:38ceb79fef03 1829 \return 1 Function failed.
kevman 0:38ceb79fef03 1830 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
kevman 0:38ceb79fef03 1831 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
kevman 0:38ceb79fef03 1832 must contain a vendor-specific implementation of this function.
kevman 0:38ceb79fef03 1833 */
kevman 0:38ceb79fef03 1834 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
kevman 0:38ceb79fef03 1835 {
kevman 0:38ceb79fef03 1836 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
kevman 0:38ceb79fef03 1837 {
kevman 0:38ceb79fef03 1838 return (1UL); /* Reload value impossible */
kevman 0:38ceb79fef03 1839 }
kevman 0:38ceb79fef03 1840
kevman 0:38ceb79fef03 1841 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
kevman 0:38ceb79fef03 1842 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
kevman 0:38ceb79fef03 1843 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
kevman 0:38ceb79fef03 1844 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
kevman 0:38ceb79fef03 1845 SysTick_CTRL_TICKINT_Msk |
kevman 0:38ceb79fef03 1846 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
kevman 0:38ceb79fef03 1847 return (0UL); /* Function successful */
kevman 0:38ceb79fef03 1848 }
kevman 0:38ceb79fef03 1849
kevman 0:38ceb79fef03 1850 #endif
kevman 0:38ceb79fef03 1851
kevman 0:38ceb79fef03 1852 /*@} end of CMSIS_Core_SysTickFunctions */
kevman 0:38ceb79fef03 1853
kevman 0:38ceb79fef03 1854
kevman 0:38ceb79fef03 1855
kevman 0:38ceb79fef03 1856 /* ##################################### Debug In/Output function ########################################### */
kevman 0:38ceb79fef03 1857 /**
kevman 0:38ceb79fef03 1858 \ingroup CMSIS_Core_FunctionInterface
kevman 0:38ceb79fef03 1859 \defgroup CMSIS_core_DebugFunctions ITM Functions
kevman 0:38ceb79fef03 1860 \brief Functions that access the ITM debug interface.
kevman 0:38ceb79fef03 1861 @{
kevman 0:38ceb79fef03 1862 */
kevman 0:38ceb79fef03 1863
kevman 0:38ceb79fef03 1864 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
kevman 0:38ceb79fef03 1865 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
kevman 0:38ceb79fef03 1866
kevman 0:38ceb79fef03 1867
kevman 0:38ceb79fef03 1868 /**
kevman 0:38ceb79fef03 1869 \brief ITM Send Character
kevman 0:38ceb79fef03 1870 \details Transmits a character via the ITM channel 0, and
kevman 0:38ceb79fef03 1871 \li Just returns when no debugger is connected that has booked the output.
kevman 0:38ceb79fef03 1872 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
kevman 0:38ceb79fef03 1873 \param [in] ch Character to transmit.
kevman 0:38ceb79fef03 1874 \returns Character to transmit.
kevman 0:38ceb79fef03 1875 */
kevman 0:38ceb79fef03 1876 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
kevman 0:38ceb79fef03 1877 {
kevman 0:38ceb79fef03 1878 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
kevman 0:38ceb79fef03 1879 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
kevman 0:38ceb79fef03 1880 {
kevman 0:38ceb79fef03 1881 while (ITM->PORT[0U].u32 == 0UL)
kevman 0:38ceb79fef03 1882 {
kevman 0:38ceb79fef03 1883 __NOP();
kevman 0:38ceb79fef03 1884 }
kevman 0:38ceb79fef03 1885 ITM->PORT[0U].u8 = (uint8_t)ch;
kevman 0:38ceb79fef03 1886 }
kevman 0:38ceb79fef03 1887 return (ch);
kevman 0:38ceb79fef03 1888 }
kevman 0:38ceb79fef03 1889
kevman 0:38ceb79fef03 1890
kevman 0:38ceb79fef03 1891 /**
kevman 0:38ceb79fef03 1892 \brief ITM Receive Character
kevman 0:38ceb79fef03 1893 \details Inputs a character via the external variable \ref ITM_RxBuffer.
kevman 0:38ceb79fef03 1894 \return Received character.
kevman 0:38ceb79fef03 1895 \return -1 No character pending.
kevman 0:38ceb79fef03 1896 */
kevman 0:38ceb79fef03 1897 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
kevman 0:38ceb79fef03 1898 {
kevman 0:38ceb79fef03 1899 int32_t ch = -1; /* no character available */
kevman 0:38ceb79fef03 1900
kevman 0:38ceb79fef03 1901 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
kevman 0:38ceb79fef03 1902 {
kevman 0:38ceb79fef03 1903 ch = ITM_RxBuffer;
kevman 0:38ceb79fef03 1904 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
kevman 0:38ceb79fef03 1905 }
kevman 0:38ceb79fef03 1906
kevman 0:38ceb79fef03 1907 return (ch);
kevman 0:38ceb79fef03 1908 }
kevman 0:38ceb79fef03 1909
kevman 0:38ceb79fef03 1910
kevman 0:38ceb79fef03 1911 /**
kevman 0:38ceb79fef03 1912 \brief ITM Check Character
kevman 0:38ceb79fef03 1913 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
kevman 0:38ceb79fef03 1914 \return 0 No character available.
kevman 0:38ceb79fef03 1915 \return 1 Character available.
kevman 0:38ceb79fef03 1916 */
kevman 0:38ceb79fef03 1917 __STATIC_INLINE int32_t ITM_CheckChar (void)
kevman 0:38ceb79fef03 1918 {
kevman 0:38ceb79fef03 1919
kevman 0:38ceb79fef03 1920 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
kevman 0:38ceb79fef03 1921 {
kevman 0:38ceb79fef03 1922 return (0); /* no character available */
kevman 0:38ceb79fef03 1923 }
kevman 0:38ceb79fef03 1924 else
kevman 0:38ceb79fef03 1925 {
kevman 0:38ceb79fef03 1926 return (1); /* character available */
kevman 0:38ceb79fef03 1927 }
kevman 0:38ceb79fef03 1928 }
kevman 0:38ceb79fef03 1929
kevman 0:38ceb79fef03 1930 /*@} end of CMSIS_core_DebugFunctions */
kevman 0:38ceb79fef03 1931
kevman 0:38ceb79fef03 1932
kevman 0:38ceb79fef03 1933
kevman 0:38ceb79fef03 1934
kevman 0:38ceb79fef03 1935 #ifdef __cplusplus
kevman 0:38ceb79fef03 1936 }
kevman 0:38ceb79fef03 1937 #endif
kevman 0:38ceb79fef03 1938
kevman 0:38ceb79fef03 1939 #endif /* __CORE_CM3_H_DEPENDANT */
kevman 0:38ceb79fef03 1940
kevman 0:38ceb79fef03 1941 #endif /* __CMSIS_GENERIC */