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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_lc7981_320x64.c@0:d8f4c441e032, 2016-06-10 (annotated)

Committer:
lixianyu
Date:
Fri Jun 10 15:20:20 2016 +0000
Revision:
0:d8f4c441e032
u8glib???????????i2c???

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_lc7981_320x64.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Note: Requires 16 bit mode (Must be enabled in u8g.h)
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Tested with Varitronix MGLS32064-03.pdf
lixianyu 0:d8f4c441e032 8
lixianyu 0:d8f4c441e032 9 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 10
lixianyu 0:d8f4c441e032 11 Copyright (c) 2012, olikraus@gmail.com
lixianyu 0:d8f4c441e032 12 All rights reserved.
lixianyu 0:d8f4c441e032 13
lixianyu 0:d8f4c441e032 14 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 15 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 16
lixianyu 0:d8f4c441e032 17 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 18 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 21 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 22 materials provided with the distribution.
lixianyu 0:d8f4c441e032 23
lixianyu 0:d8f4c441e032 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 26 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 27 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 28 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 29 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 30 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 32 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 33 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 34 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 35 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 36 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 37
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 */
lixianyu 0:d8f4c441e032 40
lixianyu 0:d8f4c441e032 41 #include "u8g.h"
lixianyu 0:d8f4c441e032 42
lixianyu 0:d8f4c441e032 43 #ifdef U8G_16BIT
lixianyu 0:d8f4c441e032 44 #define WIDTH 320
lixianyu 0:d8f4c441e032 45 #else
lixianyu 0:d8f4c441e032 46 #define WIDTH 240
lixianyu 0:d8f4c441e032 47 #endif
lixianyu 0:d8f4c441e032 48
lixianyu 0:d8f4c441e032 49 #define HEIGHT 64
lixianyu 0:d8f4c441e032 50 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 51
lixianyu 0:d8f4c441e032 52
lixianyu 0:d8f4c441e032 53 /*
lixianyu 0:d8f4c441e032 54 http://www.gaw.ru/pdf/lcd/lcm/Varitronix/graf/MGLS32064-03.pdf
lixianyu 0:d8f4c441e032 55 */
lixianyu 0:d8f4c441e032 56
lixianyu 0:d8f4c441e032 57 static const uint8_t u8g_dev_lc7981_320x64_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 58 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 59 U8G_ESC_ADR(1), /* instruction mode */
lixianyu 0:d8f4c441e032 60 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
lixianyu 0:d8f4c441e032 61 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 62 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 63
lixianyu 0:d8f4c441e032 64
lixianyu 0:d8f4c441e032 65 U8G_ESC_ADR(1), /* instruction mode */
lixianyu 0:d8f4c441e032 66 0x000, /* mode register */
lixianyu 0:d8f4c441e032 67 U8G_ESC_ADR(0), /* data mode */
lixianyu 0:d8f4c441e032 68 0x032, /* display on (bit 5), master mode on (bit 4), graphics mode on (bit 1)*/
lixianyu 0:d8f4c441e032 69
lixianyu 0:d8f4c441e032 70 U8G_ESC_ADR(1), /* instruction mode */
lixianyu 0:d8f4c441e032 71 0x001, /* character/bits per pixel pitch */
lixianyu 0:d8f4c441e032 72 U8G_ESC_ADR(0), /* data mode */
lixianyu 0:d8f4c441e032 73 0x007, /* 8 bits per pixel */
lixianyu 0:d8f4c441e032 74
lixianyu 0:d8f4c441e032 75 U8G_ESC_ADR(1), /* instruction mode */
lixianyu 0:d8f4c441e032 76 0x002, /* number of chars/byte width of the screen */
lixianyu 0:d8f4c441e032 77 U8G_ESC_ADR(0), /* data mode */
lixianyu 0:d8f4c441e032 78 WIDTH/8-1, /* 8 bits per pixel */
lixianyu 0:d8f4c441e032 79
lixianyu 0:d8f4c441e032 80 U8G_ESC_ADR(1), /* instruction mode */
lixianyu 0:d8f4c441e032 81 0x003, /* time division */
lixianyu 0:d8f4c441e032 82 U8G_ESC_ADR(0), /* data mode */
lixianyu 0:d8f4c441e032 83 0x07f, /* */
lixianyu 0:d8f4c441e032 84
lixianyu 0:d8f4c441e032 85 U8G_ESC_ADR(1), /* instruction mode */
lixianyu 0:d8f4c441e032 86 0x008, /* display start low */
lixianyu 0:d8f4c441e032 87 U8G_ESC_ADR(0), /* data mode */
lixianyu 0:d8f4c441e032 88 0x000, /* */
lixianyu 0:d8f4c441e032 89
lixianyu 0:d8f4c441e032 90 U8G_ESC_ADR(1), /* instruction mode */
lixianyu 0:d8f4c441e032 91 0x009, /* display start high */
lixianyu 0:d8f4c441e032 92 U8G_ESC_ADR(0), /* data mode */
lixianyu 0:d8f4c441e032 93 0x000, /* */
lixianyu 0:d8f4c441e032 94
lixianyu 0:d8f4c441e032 95 U8G_ESC_DLY(10), /* delay 10 ms */
lixianyu 0:d8f4c441e032 96
lixianyu 0:d8f4c441e032 97 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 98 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 99 };
lixianyu 0:d8f4c441e032 100
lixianyu 0:d8f4c441e032 101 uint8_t u8g_dev_lc7981_320x64_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 102 {
lixianyu 0:d8f4c441e032 103 switch(msg)
lixianyu 0:d8f4c441e032 104 {
lixianyu 0:d8f4c441e032 105 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 106 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_NONE);
lixianyu 0:d8f4c441e032 107 u8g_WriteEscSeqP(u8g, dev, u8g_dev_lc7981_320x64_init_seq);
lixianyu 0:d8f4c441e032 108 break;
lixianyu 0:d8f4c441e032 109 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 110 break;
lixianyu 0:d8f4c441e032 111 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 112 {
lixianyu 0:d8f4c441e032 113 uint8_t y, i;
lixianyu 0:d8f4c441e032 114 uint16_t disp_ram_adr;
lixianyu 0:d8f4c441e032 115 uint8_t *ptr;
lixianyu 0:d8f4c441e032 116 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 117
lixianyu 0:d8f4c441e032 118 u8g_SetAddress(u8g, dev, 1); /* cmd mode */
lixianyu 0:d8f4c441e032 119 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 120 y = pb->p.page_y0;
lixianyu 0:d8f4c441e032 121 ptr = pb->buf;
lixianyu 0:d8f4c441e032 122 disp_ram_adr = WIDTH/8;
lixianyu 0:d8f4c441e032 123 disp_ram_adr *= y;
lixianyu 0:d8f4c441e032 124 for( i = 0; i < 8; i ++ )
lixianyu 0:d8f4c441e032 125 {
lixianyu 0:d8f4c441e032 126 u8g_SetAddress(u8g, dev, 1); /* cmd mode */
lixianyu 0:d8f4c441e032 127 u8g_WriteByte(u8g, dev, 0x00a ); /* display ram (cursor) address low byte */
lixianyu 0:d8f4c441e032 128 u8g_SetAddress(u8g, dev, 0); /* data mode */
lixianyu 0:d8f4c441e032 129 u8g_WriteByte(u8g, dev, disp_ram_adr & 0x0ff );
lixianyu 0:d8f4c441e032 130
lixianyu 0:d8f4c441e032 131 u8g_SetAddress(u8g, dev, 1); /* cmd mode */
lixianyu 0:d8f4c441e032 132 u8g_WriteByte(u8g, dev, 0x00b ); /* display ram (cursor) address hight byte */
lixianyu 0:d8f4c441e032 133 u8g_SetAddress(u8g, dev, 0); /* data mode */
lixianyu 0:d8f4c441e032 134 u8g_WriteByte(u8g, dev, disp_ram_adr >> 8 );
lixianyu 0:d8f4c441e032 135
lixianyu 0:d8f4c441e032 136 u8g_SetAddress(u8g, dev, 1); /* cmd mode */
lixianyu 0:d8f4c441e032 137 u8g_WriteByte(u8g, dev, 0x00c ); /* write data */
lixianyu 0:d8f4c441e032 138 u8g_SetAddress(u8g, dev, 0); /* data mode */
lixianyu 0:d8f4c441e032 139 u8g_WriteSequence(u8g, dev, WIDTH/8, ptr);
lixianyu 0:d8f4c441e032 140 ptr += WIDTH/8;
lixianyu 0:d8f4c441e032 141 disp_ram_adr += WIDTH/8;
lixianyu 0:d8f4c441e032 142 }
lixianyu 0:d8f4c441e032 143 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 144 }
lixianyu 0:d8f4c441e032 145 break;
lixianyu 0:d8f4c441e032 146 }
lixianyu 0:d8f4c441e032 147 return u8g_dev_pb8h1f_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 148 }
lixianyu 0:d8f4c441e032 149
lixianyu 0:d8f4c441e032 150 U8G_PB_DEV(u8g_dev_lc7981_320x64_8bit, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_lc7981_320x64_fn, U8G_COM_FAST_PARALLEL);
lixianyu 0:d8f4c441e032 151
lixianyu 0:d8f4c441e032 152