hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1351_128x128.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ssd1351_128x128.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Copyright (c) 2013, jamjardavies@gmail.com
lixianyu 0:d8f4c441e032 8 Copyright (c) 2013, olikraus@gmail.com
lixianyu 0:d8f4c441e032 9 All rights reserved.
lixianyu 0:d8f4c441e032 10
lixianyu 0:d8f4c441e032 11 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 12 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 13
lixianyu 0:d8f4c441e032 14 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 15 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 16
lixianyu 0:d8f4c441e032 17 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 18 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 19 materials provided with the distribution.
lixianyu 0:d8f4c441e032 20
lixianyu 0:d8f4c441e032 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 22 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 23 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 24 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 25 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 26 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 27 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 30 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 31 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 33 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 34
lixianyu 0:d8f4c441e032 35 History:
lixianyu 0:d8f4c441e032 36 Initial version 20 May 2013 jamjardavies@gmail.com
lixianyu 0:d8f4c441e032 37 indexed device 22 May 2013 olikraus@gmail.com
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 */
lixianyu 0:d8f4c441e032 40
lixianyu 0:d8f4c441e032 41 #include "u8g.h"
lixianyu 0:d8f4c441e032 42
lixianyu 0:d8f4c441e032 43 #define WIDTH 128
lixianyu 0:d8f4c441e032 44 #define HEIGHT 128
lixianyu 0:d8f4c441e032 45 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 46
lixianyu 0:d8f4c441e032 47 static const uint8_t u8g_dev_ssd1351_128x128_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 48 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 49 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 50 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 51 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 52 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 53 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 54
lixianyu 0:d8f4c441e032 55 0xfd, /* Command Lock */
lixianyu 0:d8f4c441e032 56 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 57 0x12,
lixianyu 0:d8f4c441e032 58
lixianyu 0:d8f4c441e032 59 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 60 0xfd,
lixianyu 0:d8f4c441e032 61 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 62 0xb1, /* Command Lock */
lixianyu 0:d8f4c441e032 63
lixianyu 0:d8f4c441e032 64 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 65 0xae, /* Set Display Off */
lixianyu 0:d8f4c441e032 66
lixianyu 0:d8f4c441e032 67 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 68 0xb3,
lixianyu 0:d8f4c441e032 69 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 70 0xf1, /* Front Clock Div */
lixianyu 0:d8f4c441e032 71
lixianyu 0:d8f4c441e032 72 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 73 0xca,
lixianyu 0:d8f4c441e032 74 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 75 0x7f, /* Set Multiplex Ratio */
lixianyu 0:d8f4c441e032 76
lixianyu 0:d8f4c441e032 77 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 78 0xa0,
lixianyu 0:d8f4c441e032 79 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 80 0xb4, /* Set Colour Depth */
lixianyu 0:d8f4c441e032 81
lixianyu 0:d8f4c441e032 82 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 83 0x15,
lixianyu 0:d8f4c441e032 84 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 85 0x00, 0x7f, /* Set Column Address */
lixianyu 0:d8f4c441e032 86
lixianyu 0:d8f4c441e032 87 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 88 0x75,
lixianyu 0:d8f4c441e032 89 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 90 0x00, 0x7f, /* Set Row Address */
lixianyu 0:d8f4c441e032 91
lixianyu 0:d8f4c441e032 92 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 93 0xa1,
lixianyu 0:d8f4c441e032 94 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 95 0x00, /* Set Display Start Line */
lixianyu 0:d8f4c441e032 96
lixianyu 0:d8f4c441e032 97 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 98 0xa2,
lixianyu 0:d8f4c441e032 99 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 100 0x00, /* Set Display Offset */
lixianyu 0:d8f4c441e032 101
lixianyu 0:d8f4c441e032 102 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 103 0xb5,
lixianyu 0:d8f4c441e032 104 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 105 0x00, /* Set GPIO */
lixianyu 0:d8f4c441e032 106
lixianyu 0:d8f4c441e032 107 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 108 0xab,
lixianyu 0:d8f4c441e032 109 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 110 0x01, /* Set Function Selection */
lixianyu 0:d8f4c441e032 111
lixianyu 0:d8f4c441e032 112 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 113 0xb1,
lixianyu 0:d8f4c441e032 114 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 115 0x32, /* Set Phase Length */
lixianyu 0:d8f4c441e032 116
lixianyu 0:d8f4c441e032 117 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 118 0xb4,
lixianyu 0:d8f4c441e032 119 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 120 0xa0, 0xb5, 0x55, /* Set Segment Low Voltage */
lixianyu 0:d8f4c441e032 121
lixianyu 0:d8f4c441e032 122 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 123 0xbb,
lixianyu 0:d8f4c441e032 124 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 125 0x17, /* Set Precharge Voltage */
lixianyu 0:d8f4c441e032 126
lixianyu 0:d8f4c441e032 127 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 128 0xbe,
lixianyu 0:d8f4c441e032 129 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 130 0x05, /* Set VComH Voltage */
lixianyu 0:d8f4c441e032 131
lixianyu 0:d8f4c441e032 132 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 133 0xc1,
lixianyu 0:d8f4c441e032 134 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 135 0xc8, 0x80, 0xc8, /* Set Contrast */
lixianyu 0:d8f4c441e032 136
lixianyu 0:d8f4c441e032 137 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 138 0xc7,
lixianyu 0:d8f4c441e032 139 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 140 0x0f, /* Set Master Contrast */
lixianyu 0:d8f4c441e032 141
lixianyu 0:d8f4c441e032 142 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 143 0xb6,
lixianyu 0:d8f4c441e032 144 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 145 0x01, /* Set Second Precharge Period */
lixianyu 0:d8f4c441e032 146
lixianyu 0:d8f4c441e032 147 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 148 0xa6, /* Set Display Mode Reset */
lixianyu 0:d8f4c441e032 149
lixianyu 0:d8f4c441e032 150
lixianyu 0:d8f4c441e032 151 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 152 0xb8, /* Set CMD Grayscale Lookup */
lixianyu 0:d8f4c441e032 153 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 154 0x05,
lixianyu 0:d8f4c441e032 155 0x06,
lixianyu 0:d8f4c441e032 156 0x07,
lixianyu 0:d8f4c441e032 157 0x08,
lixianyu 0:d8f4c441e032 158 0x09,
lixianyu 0:d8f4c441e032 159 0x0a,
lixianyu 0:d8f4c441e032 160 0x0b,
lixianyu 0:d8f4c441e032 161 0x0c,
lixianyu 0:d8f4c441e032 162 0x0D,
lixianyu 0:d8f4c441e032 163 0x0E,
lixianyu 0:d8f4c441e032 164 0x0F,
lixianyu 0:d8f4c441e032 165 0x10,
lixianyu 0:d8f4c441e032 166 0x11,
lixianyu 0:d8f4c441e032 167 0x12,
lixianyu 0:d8f4c441e032 168 0x13,
lixianyu 0:d8f4c441e032 169 0x14,
lixianyu 0:d8f4c441e032 170 0x15,
lixianyu 0:d8f4c441e032 171 0x16,
lixianyu 0:d8f4c441e032 172 0x18,
lixianyu 0:d8f4c441e032 173 0x1a,
lixianyu 0:d8f4c441e032 174 0x1b,
lixianyu 0:d8f4c441e032 175 0x1C,
lixianyu 0:d8f4c441e032 176 0x1D,
lixianyu 0:d8f4c441e032 177 0x1F,
lixianyu 0:d8f4c441e032 178 0x21,
lixianyu 0:d8f4c441e032 179 0x23,
lixianyu 0:d8f4c441e032 180 0x25,
lixianyu 0:d8f4c441e032 181 0x27,
lixianyu 0:d8f4c441e032 182 0x2A,
lixianyu 0:d8f4c441e032 183 0x2D,
lixianyu 0:d8f4c441e032 184 0x30,
lixianyu 0:d8f4c441e032 185 0x33,
lixianyu 0:d8f4c441e032 186 0x36,
lixianyu 0:d8f4c441e032 187 0x39,
lixianyu 0:d8f4c441e032 188 0x3C,
lixianyu 0:d8f4c441e032 189 0x3F,
lixianyu 0:d8f4c441e032 190 0x42,
lixianyu 0:d8f4c441e032 191 0x45,
lixianyu 0:d8f4c441e032 192 0x48,
lixianyu 0:d8f4c441e032 193 0x4C,
lixianyu 0:d8f4c441e032 194 0x50,
lixianyu 0:d8f4c441e032 195 0x54,
lixianyu 0:d8f4c441e032 196 0x58,
lixianyu 0:d8f4c441e032 197 0x5C,
lixianyu 0:d8f4c441e032 198 0x60,
lixianyu 0:d8f4c441e032 199 0x64,
lixianyu 0:d8f4c441e032 200 0x68,
lixianyu 0:d8f4c441e032 201 0x6C,
lixianyu 0:d8f4c441e032 202 0x70,
lixianyu 0:d8f4c441e032 203 0x74,
lixianyu 0:d8f4c441e032 204 0x78,
lixianyu 0:d8f4c441e032 205 0x7D,
lixianyu 0:d8f4c441e032 206 0x82,
lixianyu 0:d8f4c441e032 207 0x87,
lixianyu 0:d8f4c441e032 208 0x8C,
lixianyu 0:d8f4c441e032 209 0x91,
lixianyu 0:d8f4c441e032 210 0x96,
lixianyu 0:d8f4c441e032 211 0x9B,
lixianyu 0:d8f4c441e032 212 0xA0,
lixianyu 0:d8f4c441e032 213 0xA5,
lixianyu 0:d8f4c441e032 214 0xAA,
lixianyu 0:d8f4c441e032 215 0xAF,
lixianyu 0:d8f4c441e032 216 0xB4,
lixianyu 0:d8f4c441e032 217
lixianyu 0:d8f4c441e032 218 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 219 0xaf, /* Set Display On */
lixianyu 0:d8f4c441e032 220 0x5c,
lixianyu 0:d8f4c441e032 221 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 222 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 223 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 224 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 225 };
lixianyu 0:d8f4c441e032 226
lixianyu 0:d8f4c441e032 227
lixianyu 0:d8f4c441e032 228 /* set gpio to high */
lixianyu 0:d8f4c441e032 229 static const uint8_t u8g_dev_ssd1351_128x128gh_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 230 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 231 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 232 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 233 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 234 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 235 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 236
lixianyu 0:d8f4c441e032 237 0xfd, /* Command Lock */
lixianyu 0:d8f4c441e032 238 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 239 0x12,
lixianyu 0:d8f4c441e032 240
lixianyu 0:d8f4c441e032 241 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 242 0xfd,
lixianyu 0:d8f4c441e032 243 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 244 0xb1, /* Command Lock */
lixianyu 0:d8f4c441e032 245
lixianyu 0:d8f4c441e032 246 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 247 0xae, /* Set Display Off */
lixianyu 0:d8f4c441e032 248
lixianyu 0:d8f4c441e032 249 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 250 0xb3,
lixianyu 0:d8f4c441e032 251 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 252 0xf1, /* Front Clock Div */
lixianyu 0:d8f4c441e032 253
lixianyu 0:d8f4c441e032 254 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 255 0xca,
lixianyu 0:d8f4c441e032 256 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 257 0x7f, /* Set Multiplex Ratio */
lixianyu 0:d8f4c441e032 258
lixianyu 0:d8f4c441e032 259 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 260 0xa0,
lixianyu 0:d8f4c441e032 261 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 262 0xb4, /* Set Colour Depth */
lixianyu 0:d8f4c441e032 263
lixianyu 0:d8f4c441e032 264 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 265 0x15,
lixianyu 0:d8f4c441e032 266 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 267 0x00, 0x7f, /* Set Column Address */
lixianyu 0:d8f4c441e032 268
lixianyu 0:d8f4c441e032 269 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 270 0x75,
lixianyu 0:d8f4c441e032 271 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 272 0x00, 0x7f, /* Set Row Address */
lixianyu 0:d8f4c441e032 273
lixianyu 0:d8f4c441e032 274 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 275 0xa1,
lixianyu 0:d8f4c441e032 276 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 277 0x00, /* Set Display Start Line */
lixianyu 0:d8f4c441e032 278
lixianyu 0:d8f4c441e032 279 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 280 0xa2,
lixianyu 0:d8f4c441e032 281 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 282 0x00, /* Set Display Offset */
lixianyu 0:d8f4c441e032 283
lixianyu 0:d8f4c441e032 284 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 285 0xb5,
lixianyu 0:d8f4c441e032 286 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 287 0x03, /* Set GPIO to High Level */
lixianyu 0:d8f4c441e032 288
lixianyu 0:d8f4c441e032 289 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 290 0xab,
lixianyu 0:d8f4c441e032 291 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 292 0x01, /* Set Function Selection */
lixianyu 0:d8f4c441e032 293
lixianyu 0:d8f4c441e032 294 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 295 0xb1,
lixianyu 0:d8f4c441e032 296 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 297 0x32, /* Set Phase Length */
lixianyu 0:d8f4c441e032 298
lixianyu 0:d8f4c441e032 299 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 300 0xb4,
lixianyu 0:d8f4c441e032 301 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 302 0xa0, 0xb5, 0x55, /* Set Segment Low Voltage */
lixianyu 0:d8f4c441e032 303
lixianyu 0:d8f4c441e032 304 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 305 0xbb,
lixianyu 0:d8f4c441e032 306 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 307 0x17, /* Set Precharge Voltage */
lixianyu 0:d8f4c441e032 308
lixianyu 0:d8f4c441e032 309 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 310 0xbe,
lixianyu 0:d8f4c441e032 311 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 312 0x05, /* Set VComH Voltage */
lixianyu 0:d8f4c441e032 313
lixianyu 0:d8f4c441e032 314 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 315 0xc1,
lixianyu 0:d8f4c441e032 316 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 317 0xc8, 0x80, 0xc8, /* Set Contrast */
lixianyu 0:d8f4c441e032 318
lixianyu 0:d8f4c441e032 319 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 320 0xc7,
lixianyu 0:d8f4c441e032 321 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 322 0x0f, /* Set Master Contrast */
lixianyu 0:d8f4c441e032 323
lixianyu 0:d8f4c441e032 324 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 325 0xb6,
lixianyu 0:d8f4c441e032 326 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 327 0x01, /* Set Second Precharge Period */
lixianyu 0:d8f4c441e032 328
lixianyu 0:d8f4c441e032 329 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 330 0xa6, /* Set Display Mode Reset */
lixianyu 0:d8f4c441e032 331
lixianyu 0:d8f4c441e032 332
lixianyu 0:d8f4c441e032 333 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 334 0xb8, /* Set CMD Grayscale Lookup */
lixianyu 0:d8f4c441e032 335 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 336 0x05,
lixianyu 0:d8f4c441e032 337 0x06,
lixianyu 0:d8f4c441e032 338 0x07,
lixianyu 0:d8f4c441e032 339 0x08,
lixianyu 0:d8f4c441e032 340 0x09,
lixianyu 0:d8f4c441e032 341 0x0a,
lixianyu 0:d8f4c441e032 342 0x0b,
lixianyu 0:d8f4c441e032 343 0x0c,
lixianyu 0:d8f4c441e032 344 0x0D,
lixianyu 0:d8f4c441e032 345 0x0E,
lixianyu 0:d8f4c441e032 346 0x0F,
lixianyu 0:d8f4c441e032 347 0x10,
lixianyu 0:d8f4c441e032 348 0x11,
lixianyu 0:d8f4c441e032 349 0x12,
lixianyu 0:d8f4c441e032 350 0x13,
lixianyu 0:d8f4c441e032 351 0x14,
lixianyu 0:d8f4c441e032 352 0x15,
lixianyu 0:d8f4c441e032 353 0x16,
lixianyu 0:d8f4c441e032 354 0x18,
lixianyu 0:d8f4c441e032 355 0x1a,
lixianyu 0:d8f4c441e032 356 0x1b,
lixianyu 0:d8f4c441e032 357 0x1C,
lixianyu 0:d8f4c441e032 358 0x1D,
lixianyu 0:d8f4c441e032 359 0x1F,
lixianyu 0:d8f4c441e032 360 0x21,
lixianyu 0:d8f4c441e032 361 0x23,
lixianyu 0:d8f4c441e032 362 0x25,
lixianyu 0:d8f4c441e032 363 0x27,
lixianyu 0:d8f4c441e032 364 0x2A,
lixianyu 0:d8f4c441e032 365 0x2D,
lixianyu 0:d8f4c441e032 366 0x30,
lixianyu 0:d8f4c441e032 367 0x33,
lixianyu 0:d8f4c441e032 368 0x36,
lixianyu 0:d8f4c441e032 369 0x39,
lixianyu 0:d8f4c441e032 370 0x3C,
lixianyu 0:d8f4c441e032 371 0x3F,
lixianyu 0:d8f4c441e032 372 0x42,
lixianyu 0:d8f4c441e032 373 0x45,
lixianyu 0:d8f4c441e032 374 0x48,
lixianyu 0:d8f4c441e032 375 0x4C,
lixianyu 0:d8f4c441e032 376 0x50,
lixianyu 0:d8f4c441e032 377 0x54,
lixianyu 0:d8f4c441e032 378 0x58,
lixianyu 0:d8f4c441e032 379 0x5C,
lixianyu 0:d8f4c441e032 380 0x60,
lixianyu 0:d8f4c441e032 381 0x64,
lixianyu 0:d8f4c441e032 382 0x68,
lixianyu 0:d8f4c441e032 383 0x6C,
lixianyu 0:d8f4c441e032 384 0x70,
lixianyu 0:d8f4c441e032 385 0x74,
lixianyu 0:d8f4c441e032 386 0x78,
lixianyu 0:d8f4c441e032 387 0x7D,
lixianyu 0:d8f4c441e032 388 0x82,
lixianyu 0:d8f4c441e032 389 0x87,
lixianyu 0:d8f4c441e032 390 0x8C,
lixianyu 0:d8f4c441e032 391 0x91,
lixianyu 0:d8f4c441e032 392 0x96,
lixianyu 0:d8f4c441e032 393 0x9B,
lixianyu 0:d8f4c441e032 394 0xA0,
lixianyu 0:d8f4c441e032 395 0xA5,
lixianyu 0:d8f4c441e032 396 0xAA,
lixianyu 0:d8f4c441e032 397 0xAF,
lixianyu 0:d8f4c441e032 398 0xB4,
lixianyu 0:d8f4c441e032 399
lixianyu 0:d8f4c441e032 400 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 401 0xaf, /* Set Display On */
lixianyu 0:d8f4c441e032 402 0x5c,
lixianyu 0:d8f4c441e032 403 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 404 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 405 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 406 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 407 };
lixianyu 0:d8f4c441e032 408
lixianyu 0:d8f4c441e032 409 #define u8g_dev_ssd1351_128x128_init_seq u8g_dev_ssd1351_128x128_init_seq
lixianyu 0:d8f4c441e032 410
lixianyu 0:d8f4c441e032 411 static const uint8_t u8g_dev_ssd1351_128x128_column_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 412 U8G_ESC_CS(1),
lixianyu 0:d8f4c441e032 413 U8G_ESC_ADR(0), 0x15,
lixianyu 0:d8f4c441e032 414 U8G_ESC_ADR(1), 0x00, 0x7f,
lixianyu 0:d8f4c441e032 415 U8G_ESC_ADR(0), 0x75,
lixianyu 0:d8f4c441e032 416 U8G_ESC_ADR(1), 0x00, 0x7f,
lixianyu 0:d8f4c441e032 417 U8G_ESC_ADR(0), 0x5c,
lixianyu 0:d8f4c441e032 418 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 419 U8G_ESC_CS(0),
lixianyu 0:d8f4c441e032 420 U8G_ESC_END
lixianyu 0:d8f4c441e032 421 };
lixianyu 0:d8f4c441e032 422
lixianyu 0:d8f4c441e032 423 #define RGB332_STREAM_BYTES 8
lixianyu 0:d8f4c441e032 424 static uint8_t u8g_ssd1351_stream_bytes[RGB332_STREAM_BYTES*3];
lixianyu 0:d8f4c441e032 425
lixianyu 0:d8f4c441e032 426 void u8g_ssd1351_to_stream(uint8_t *ptr)
lixianyu 0:d8f4c441e032 427 {
lixianyu 0:d8f4c441e032 428 uint8_t cnt = RGB332_STREAM_BYTES;
lixianyu 0:d8f4c441e032 429 uint8_t val;
lixianyu 0:d8f4c441e032 430 uint8_t *dest = u8g_ssd1351_stream_bytes;
lixianyu 0:d8f4c441e032 431 for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
lixianyu 0:d8f4c441e032 432 {
lixianyu 0:d8f4c441e032 433 val = *ptr++;
lixianyu 0:d8f4c441e032 434 *dest++ = ((val & 0xe0) >> 2);
lixianyu 0:d8f4c441e032 435 *dest++ = ((val & 0x1c) << 1);
lixianyu 0:d8f4c441e032 436 *dest++ = ((val & 0x03) << 4);
lixianyu 0:d8f4c441e032 437 }
lixianyu 0:d8f4c441e032 438 }
lixianyu 0:d8f4c441e032 439
lixianyu 0:d8f4c441e032 440
lixianyu 0:d8f4c441e032 441 #ifdef OBSOLETE
lixianyu 0:d8f4c441e032 442 // Convert the internal RGB 332 to R
lixianyu 0:d8f4c441e032 443 static uint8_t u8g_ssd1351_get_r(uint8_t colour)
lixianyu 0:d8f4c441e032 444 {
lixianyu 0:d8f4c441e032 445 //return ((colour & 0xe0) >> 5) * 9;
lixianyu 0:d8f4c441e032 446 //return ((colour & 0xe0) >> 5) * 8;
lixianyu 0:d8f4c441e032 447 return ((colour & 0xe0) >> 2) ;
lixianyu 0:d8f4c441e032 448 }
lixianyu 0:d8f4c441e032 449
lixianyu 0:d8f4c441e032 450 // Convert the internal RGB 332 to G
lixianyu 0:d8f4c441e032 451 static uint8_t u8g_ssd1351_get_g(uint8_t colour)
lixianyu 0:d8f4c441e032 452 {
lixianyu 0:d8f4c441e032 453 //return ((colour & 0x1c) >> 2) * 9;
lixianyu 0:d8f4c441e032 454 //return ((colour & 0x1c) >> 2) * 8;
lixianyu 0:d8f4c441e032 455 return ((colour & 0x1c) << 1);
lixianyu 0:d8f4c441e032 456 }
lixianyu 0:d8f4c441e032 457
lixianyu 0:d8f4c441e032 458 // Convert the internal RGB 332 to B
lixianyu 0:d8f4c441e032 459 static uint8_t u8g_ssd1351_get_b(uint8_t colour)
lixianyu 0:d8f4c441e032 460 {
lixianyu 0:d8f4c441e032 461 //return (colour & 0x03) * 21;
lixianyu 0:d8f4c441e032 462 return (colour & 0x03) * 16;
lixianyu 0:d8f4c441e032 463 }
lixianyu 0:d8f4c441e032 464 #endif
lixianyu 0:d8f4c441e032 465
lixianyu 0:d8f4c441e032 466
lixianyu 0:d8f4c441e032 467 uint8_t u8g_dev_ssd1351_128x128_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 468 {
lixianyu 0:d8f4c441e032 469 // u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 470
lixianyu 0:d8f4c441e032 471 switch(msg)
lixianyu 0:d8f4c441e032 472 {
lixianyu 0:d8f4c441e032 473 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 474 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 475 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
lixianyu 0:d8f4c441e032 476 break;
lixianyu 0:d8f4c441e032 477
lixianyu 0:d8f4c441e032 478 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 479 break;
lixianyu 0:d8f4c441e032 480
lixianyu 0:d8f4c441e032 481 case U8G_DEV_MSG_PAGE_FIRST:
lixianyu 0:d8f4c441e032 482 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
lixianyu 0:d8f4c441e032 483 break;
lixianyu 0:d8f4c441e032 484
lixianyu 0:d8f4c441e032 485 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 486 {
lixianyu 0:d8f4c441e032 487 u8g_uint_t x;
lixianyu 0:d8f4c441e032 488 uint8_t page_height;
lixianyu 0:d8f4c441e032 489 uint8_t i;
lixianyu 0:d8f4c441e032 490 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 491 uint8_t *ptr = pb->buf;
lixianyu 0:d8f4c441e032 492
lixianyu 0:d8f4c441e032 493 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 494
lixianyu 0:d8f4c441e032 495 page_height = pb->p.page_y1;
lixianyu 0:d8f4c441e032 496 page_height -= pb->p.page_y0;
lixianyu 0:d8f4c441e032 497 page_height++;
lixianyu 0:d8f4c441e032 498 for( i = 0; i < page_height; i++ )
lixianyu 0:d8f4c441e032 499 {
lixianyu 0:d8f4c441e032 500
lixianyu 0:d8f4c441e032 501 for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
lixianyu 0:d8f4c441e032 502 {
lixianyu 0:d8f4c441e032 503 u8g_ssd1351_to_stream(ptr);
lixianyu 0:d8f4c441e032 504 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
lixianyu 0:d8f4c441e032 505 ptr += RGB332_STREAM_BYTES;
lixianyu 0:d8f4c441e032 506 }
lixianyu 0:d8f4c441e032 507 }
lixianyu 0:d8f4c441e032 508 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 509 }
lixianyu 0:d8f4c441e032 510
lixianyu 0:d8f4c441e032 511 break;
lixianyu 0:d8f4c441e032 512 case U8G_DEV_MSG_GET_MODE:
lixianyu 0:d8f4c441e032 513 return U8G_MODE_R3G3B2;
lixianyu 0:d8f4c441e032 514 }
lixianyu 0:d8f4c441e032 515
lixianyu 0:d8f4c441e032 516 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 517 }
lixianyu 0:d8f4c441e032 518
lixianyu 0:d8f4c441e032 519 uint8_t u8g_dev_ssd1351_128x128gh_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 520 {
lixianyu 0:d8f4c441e032 521 // u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 522
lixianyu 0:d8f4c441e032 523 switch(msg)
lixianyu 0:d8f4c441e032 524 {
lixianyu 0:d8f4c441e032 525 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 526 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 527 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128gh_init_seq);
lixianyu 0:d8f4c441e032 528 break;
lixianyu 0:d8f4c441e032 529
lixianyu 0:d8f4c441e032 530 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 531 break;
lixianyu 0:d8f4c441e032 532
lixianyu 0:d8f4c441e032 533 case U8G_DEV_MSG_PAGE_FIRST:
lixianyu 0:d8f4c441e032 534 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
lixianyu 0:d8f4c441e032 535 break;
lixianyu 0:d8f4c441e032 536
lixianyu 0:d8f4c441e032 537 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 538 {
lixianyu 0:d8f4c441e032 539 u8g_uint_t x;
lixianyu 0:d8f4c441e032 540 uint8_t page_height;
lixianyu 0:d8f4c441e032 541 uint8_t i;
lixianyu 0:d8f4c441e032 542 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 543 uint8_t *ptr = pb->buf;
lixianyu 0:d8f4c441e032 544
lixianyu 0:d8f4c441e032 545 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 546
lixianyu 0:d8f4c441e032 547 page_height = pb->p.page_y1;
lixianyu 0:d8f4c441e032 548 page_height -= pb->p.page_y0;
lixianyu 0:d8f4c441e032 549 page_height++;
lixianyu 0:d8f4c441e032 550 for( i = 0; i < page_height; i++ )
lixianyu 0:d8f4c441e032 551 {
lixianyu 0:d8f4c441e032 552
lixianyu 0:d8f4c441e032 553 for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
lixianyu 0:d8f4c441e032 554 {
lixianyu 0:d8f4c441e032 555 u8g_ssd1351_to_stream(ptr);
lixianyu 0:d8f4c441e032 556 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
lixianyu 0:d8f4c441e032 557 ptr += RGB332_STREAM_BYTES;
lixianyu 0:d8f4c441e032 558 }
lixianyu 0:d8f4c441e032 559 }
lixianyu 0:d8f4c441e032 560 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 561 }
lixianyu 0:d8f4c441e032 562
lixianyu 0:d8f4c441e032 563 break;
lixianyu 0:d8f4c441e032 564 case U8G_DEV_MSG_GET_MODE:
lixianyu 0:d8f4c441e032 565 return U8G_MODE_R3G3B2;
lixianyu 0:d8f4c441e032 566 }
lixianyu 0:d8f4c441e032 567
lixianyu 0:d8f4c441e032 568 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 569 }
lixianyu 0:d8f4c441e032 570
lixianyu 0:d8f4c441e032 571 static uint8_t u8g_dev_ssd1351_128x128_r[256];
lixianyu 0:d8f4c441e032 572 static uint8_t u8g_dev_ssd1351_128x128_g[256];
lixianyu 0:d8f4c441e032 573 static uint8_t u8g_dev_ssd1351_128x128_b[256];
lixianyu 0:d8f4c441e032 574
lixianyu 0:d8f4c441e032 575 uint8_t u8g_dev_ssd1351_128x128_idx_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 576 {
lixianyu 0:d8f4c441e032 577 // u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 578
lixianyu 0:d8f4c441e032 579 switch(msg)
lixianyu 0:d8f4c441e032 580 {
lixianyu 0:d8f4c441e032 581 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 582 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 583 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
lixianyu 0:d8f4c441e032 584 break;
lixianyu 0:d8f4c441e032 585
lixianyu 0:d8f4c441e032 586 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 587 break;
lixianyu 0:d8f4c441e032 588
lixianyu 0:d8f4c441e032 589 case U8G_DEV_MSG_SET_COLOR_ENTRY:
lixianyu 0:d8f4c441e032 590 u8g_dev_ssd1351_128x128_r[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->r;
lixianyu 0:d8f4c441e032 591 u8g_dev_ssd1351_128x128_g[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->g;
lixianyu 0:d8f4c441e032 592 u8g_dev_ssd1351_128x128_b[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->b;
lixianyu 0:d8f4c441e032 593 break;
lixianyu 0:d8f4c441e032 594
lixianyu 0:d8f4c441e032 595 case U8G_DEV_MSG_PAGE_FIRST:
lixianyu 0:d8f4c441e032 596 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
lixianyu 0:d8f4c441e032 597 break;
lixianyu 0:d8f4c441e032 598
lixianyu 0:d8f4c441e032 599 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 600 {
lixianyu 0:d8f4c441e032 601 int x;
lixianyu 0:d8f4c441e032 602 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 603 uint8_t *ptr = pb->buf;
lixianyu 0:d8f4c441e032 604
lixianyu 0:d8f4c441e032 605 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 606
lixianyu 0:d8f4c441e032 607 for (x = 0; x < pb->width; x++)
lixianyu 0:d8f4c441e032 608 {
lixianyu 0:d8f4c441e032 609 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_r[(*ptr)>>2]);
lixianyu 0:d8f4c441e032 610 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_g[(*ptr)>>2]);
lixianyu 0:d8f4c441e032 611 u8g_WriteByte(u8g, dev, u8g_dev_ssd1351_128x128_b[(*ptr)>>2]);
lixianyu 0:d8f4c441e032 612
lixianyu 0:d8f4c441e032 613 ptr++;
lixianyu 0:d8f4c441e032 614 }
lixianyu 0:d8f4c441e032 615
lixianyu 0:d8f4c441e032 616 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 617 }
lixianyu 0:d8f4c441e032 618
lixianyu 0:d8f4c441e032 619 break;
lixianyu 0:d8f4c441e032 620 case U8G_DEV_MSG_GET_MODE:
lixianyu 0:d8f4c441e032 621 return U8G_MODE_INDEX;
lixianyu 0:d8f4c441e032 622 }
lixianyu 0:d8f4c441e032 623
lixianyu 0:d8f4c441e032 624 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 625 }
lixianyu 0:d8f4c441e032 626
lixianyu 0:d8f4c441e032 627 void u8g_ssd1351_hicolor_to_stream(uint8_t *ptr)
lixianyu 0:d8f4c441e032 628 {
lixianyu 0:d8f4c441e032 629 register uint8_t cnt = RGB332_STREAM_BYTES;
lixianyu 0:d8f4c441e032 630 register uint8_t low, high, r, g, b;
lixianyu 0:d8f4c441e032 631 uint8_t *dest = u8g_ssd1351_stream_bytes;
lixianyu 0:d8f4c441e032 632 for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
lixianyu 0:d8f4c441e032 633 {
lixianyu 0:d8f4c441e032 634 low = *ptr++;
lixianyu 0:d8f4c441e032 635 high = *ptr++;
lixianyu 0:d8f4c441e032 636
lixianyu 0:d8f4c441e032 637 r = high & ~7;
lixianyu 0:d8f4c441e032 638 r >>= 2;
lixianyu 0:d8f4c441e032 639 b = low & 31;
lixianyu 0:d8f4c441e032 640 b <<= 1;
lixianyu 0:d8f4c441e032 641 g = high & 7;
lixianyu 0:d8f4c441e032 642 g <<= 3;
lixianyu 0:d8f4c441e032 643 g |= (low>>5)&7;
lixianyu 0:d8f4c441e032 644
lixianyu 0:d8f4c441e032 645 *dest++ = r;
lixianyu 0:d8f4c441e032 646 *dest++ = g;
lixianyu 0:d8f4c441e032 647 *dest++ = b;
lixianyu 0:d8f4c441e032 648 }
lixianyu 0:d8f4c441e032 649 }
lixianyu 0:d8f4c441e032 650
lixianyu 0:d8f4c441e032 651
lixianyu 0:d8f4c441e032 652 uint8_t u8g_dev_ssd1351_128x128_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 653 {
lixianyu 0:d8f4c441e032 654 switch(msg)
lixianyu 0:d8f4c441e032 655 {
lixianyu 0:d8f4c441e032 656 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 657 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 658 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_init_seq);
lixianyu 0:d8f4c441e032 659 break;
lixianyu 0:d8f4c441e032 660 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 661 break;
lixianyu 0:d8f4c441e032 662 case U8G_DEV_MSG_PAGE_FIRST:
lixianyu 0:d8f4c441e032 663 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
lixianyu 0:d8f4c441e032 664 break;
lixianyu 0:d8f4c441e032 665 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 666 {
lixianyu 0:d8f4c441e032 667 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 668 uint8_t i, j;
lixianyu 0:d8f4c441e032 669 uint8_t page_height;
lixianyu 0:d8f4c441e032 670 uint8_t *ptr = pb->buf;
lixianyu 0:d8f4c441e032 671
lixianyu 0:d8f4c441e032 672 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 673
lixianyu 0:d8f4c441e032 674 page_height = pb->p.page_y1;
lixianyu 0:d8f4c441e032 675 page_height -= pb->p.page_y0;
lixianyu 0:d8f4c441e032 676 page_height++;
lixianyu 0:d8f4c441e032 677 for( j = 0; j < page_height; j++ )
lixianyu 0:d8f4c441e032 678 {
lixianyu 0:d8f4c441e032 679 for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
lixianyu 0:d8f4c441e032 680 {
lixianyu 0:d8f4c441e032 681 u8g_ssd1351_hicolor_to_stream(ptr);
lixianyu 0:d8f4c441e032 682 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
lixianyu 0:d8f4c441e032 683 ptr += RGB332_STREAM_BYTES*2;
lixianyu 0:d8f4c441e032 684 }
lixianyu 0:d8f4c441e032 685
lixianyu 0:d8f4c441e032 686 }
lixianyu 0:d8f4c441e032 687
lixianyu 0:d8f4c441e032 688 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 689
lixianyu 0:d8f4c441e032 690 }
lixianyu 0:d8f4c441e032 691 break; /* continue to base fn */
lixianyu 0:d8f4c441e032 692 case U8G_DEV_MSG_GET_MODE:
lixianyu 0:d8f4c441e032 693 return U8G_MODE_HICOLOR;
lixianyu 0:d8f4c441e032 694 }
lixianyu 0:d8f4c441e032 695 return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 696 }
lixianyu 0:d8f4c441e032 697
lixianyu 0:d8f4c441e032 698 uint8_t u8g_dev_ssd1351_128x128gh_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 699 {
lixianyu 0:d8f4c441e032 700 switch(msg)
lixianyu 0:d8f4c441e032 701 {
lixianyu 0:d8f4c441e032 702 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 703 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 704 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128gh_init_seq);
lixianyu 0:d8f4c441e032 705 break;
lixianyu 0:d8f4c441e032 706 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 707 break;
lixianyu 0:d8f4c441e032 708 case U8G_DEV_MSG_PAGE_FIRST:
lixianyu 0:d8f4c441e032 709 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1351_128x128_column_seq);
lixianyu 0:d8f4c441e032 710 break;
lixianyu 0:d8f4c441e032 711 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 712 {
lixianyu 0:d8f4c441e032 713 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 714 uint8_t i, j;
lixianyu 0:d8f4c441e032 715 uint8_t page_height;
lixianyu 0:d8f4c441e032 716 uint8_t *ptr = pb->buf;
lixianyu 0:d8f4c441e032 717
lixianyu 0:d8f4c441e032 718 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 719
lixianyu 0:d8f4c441e032 720 page_height = pb->p.page_y1;
lixianyu 0:d8f4c441e032 721 page_height -= pb->p.page_y0;
lixianyu 0:d8f4c441e032 722 page_height++;
lixianyu 0:d8f4c441e032 723 for( j = 0; j < page_height; j++ )
lixianyu 0:d8f4c441e032 724 {
lixianyu 0:d8f4c441e032 725 for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
lixianyu 0:d8f4c441e032 726 {
lixianyu 0:d8f4c441e032 727 u8g_ssd1351_hicolor_to_stream(ptr);
lixianyu 0:d8f4c441e032 728 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1351_stream_bytes);
lixianyu 0:d8f4c441e032 729 ptr += RGB332_STREAM_BYTES*2;
lixianyu 0:d8f4c441e032 730 }
lixianyu 0:d8f4c441e032 731
lixianyu 0:d8f4c441e032 732 }
lixianyu 0:d8f4c441e032 733
lixianyu 0:d8f4c441e032 734 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 735
lixianyu 0:d8f4c441e032 736 }
lixianyu 0:d8f4c441e032 737 break; /* continue to base fn */
lixianyu 0:d8f4c441e032 738 case U8G_DEV_MSG_GET_MODE:
lixianyu 0:d8f4c441e032 739 return U8G_MODE_HICOLOR;
lixianyu 0:d8f4c441e032 740 }
lixianyu 0:d8f4c441e032 741 return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 742 }
lixianyu 0:d8f4c441e032 743
lixianyu 0:d8f4c441e032 744
lixianyu 0:d8f4c441e032 745 uint8_t u8g_dev_ssd1351_128x128_byte_buf[WIDTH*PAGE_HEIGHT] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 746
lixianyu 0:d8f4c441e032 747 u8g_pb_t u8g_dev_ssd1351_128x128_byte_pb = { {PAGE_HEIGHT, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_byte_buf};
lixianyu 0:d8f4c441e032 748 u8g_dev_t u8g_dev_ssd1351_128x128_332_sw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 749 u8g_dev_t u8g_dev_ssd1351_128x128_332_hw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 750 u8g_dev_t u8g_dev_ssd1351_128x128gh_332_sw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 751 u8g_dev_t u8g_dev_ssd1351_128x128gh_332_hw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 752
lixianyu 0:d8f4c441e032 753 //u8g_dev_t u8g_dev_ssd1351_128x128_idx_sw_spi = { u8g_dev_ssd1351_128x128_idx_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 754 //u8g_dev_t u8g_dev_ssd1351_128x128_idx_hw_spi = { u8g_dev_ssd1351_128x128_idx_fn, &u8g_dev_ssd1351_128x128_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 755
lixianyu 0:d8f4c441e032 756
lixianyu 0:d8f4c441e032 757 /* only half of the height, because two bytes are needed for one pixel */
lixianyu 0:d8f4c441e032 758 u8g_pb_t u8g_dev_ssd1351_128x128_hicolor_byte_pb = { {PAGE_HEIGHT/2, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_byte_buf};
lixianyu 0:d8f4c441e032 759 u8g_dev_t u8g_dev_ssd1351_128x128_hicolor_sw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 760 u8g_dev_t u8g_dev_ssd1351_128x128_hicolor_hw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 761 u8g_dev_t u8g_dev_ssd1351_128x128gh_hicolor_sw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 762 u8g_dev_t u8g_dev_ssd1351_128x128gh_hicolor_hw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_hicolor_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 763
lixianyu 0:d8f4c441e032 764
lixianyu 0:d8f4c441e032 765 uint8_t u8g_dev_ssd1351_128x128_4x_byte_buf[WIDTH*PAGE_HEIGHT*4] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 766
lixianyu 0:d8f4c441e032 767 u8g_pb_t u8g_dev_ssd1351_128x128_4x_332_byte_pb = { {PAGE_HEIGHT*4, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_4x_byte_buf};
lixianyu 0:d8f4c441e032 768 u8g_dev_t u8g_dev_ssd1351_128x128_4x_332_sw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 769 u8g_dev_t u8g_dev_ssd1351_128x128_4x_332_hw_spi = { u8g_dev_ssd1351_128x128_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 770 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_332_sw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 771 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_332_hw_spi = { u8g_dev_ssd1351_128x128gh_332_fn, &u8g_dev_ssd1351_128x128_4x_332_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 772
lixianyu 0:d8f4c441e032 773 u8g_pb_t u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb = { {PAGE_HEIGHT/2*4, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1351_128x128_4x_byte_buf};
lixianyu 0:d8f4c441e032 774 u8g_dev_t u8g_dev_ssd1351_128x128_4x_hicolor_sw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 775 u8g_dev_t u8g_dev_ssd1351_128x128_4x_hicolor_hw_spi = { u8g_dev_ssd1351_128x128_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 776 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_hicolor_sw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 777 u8g_dev_t u8g_dev_ssd1351_128x128gh_4x_hicolor_hw_spi = { u8g_dev_ssd1351_128x128gh_hicolor_fn, &u8g_dev_ssd1351_128x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 778
lixianyu 0:d8f4c441e032 779
lixianyu 0:d8f4c441e032 780 /*
lixianyu 0:d8f4c441e032 781 U8G_PB_DEV(u8g_dev_ssd1351_128x128_332_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_332_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 782 U8G_PB_DEV(u8g_dev_ssd1351_128x128_332_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_332_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 783
lixianyu 0:d8f4c441e032 784 U8G_PB_DEV(u8g_dev_ssd1351_128x128_idx_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_idx_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 785 U8G_PB_DEV(u8g_dev_ssd1351_128x128_idx_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1351_128x128_idx_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 786 */
lixianyu 0:d8f4c441e032 787
lixianyu 0:d8f4c441e032 788