hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1309_128x64.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ssd1309_128x64.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Copyright (c) 2012, olikraus@gmail.com
lixianyu 0:d8f4c441e032 8 All rights reserved.
lixianyu 0:d8f4c441e032 9
lixianyu 0:d8f4c441e032 10 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 11 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 14 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 17 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 18 materials provided with the distribution.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 33
lixianyu 0:d8f4c441e032 34
lixianyu 0:d8f4c441e032 35 */
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 #include "u8g.h"
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 #define WIDTH 128
lixianyu 0:d8f4c441e032 40 #define HEIGHT 64
lixianyu 0:d8f4c441e032 41 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 42
lixianyu 0:d8f4c441e032 43
lixianyu 0:d8f4c441e032 44 /* ssd1309 ini sequence*/
lixianyu 0:d8f4c441e032 45 static const uint8_t u8g_dev_ssd1309_128x64_init_seq[] PROGMEM={
lixianyu 0:d8f4c441e032 46 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 47 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 48 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 49 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 50
lixianyu 0:d8f4c441e032 51 0xfd,0x12, /*Command Lock */
lixianyu 0:d8f4c441e032 52 0xae, /*Set Display Off */
lixianyu 0:d8f4c441e032 53 0xd5,0xa0, /*set Display Clock Divide Ratio/Oscillator Frequency */
lixianyu 0:d8f4c441e032 54 0xa8,0x3f, /*Set Multiplex Ratio */
lixianyu 0:d8f4c441e032 55 0x3d,0x00, /*Set Display Offset*/
lixianyu 0:d8f4c441e032 56 0x40, /*Set Display Start Line*/
lixianyu 0:d8f4c441e032 57 0xa1, /*Set Segment Re-Map*/
lixianyu 0:d8f4c441e032 58 0xc8, /*Set COM Output Scan Direction*/
lixianyu 0:d8f4c441e032 59 0xda,0x12, /*Set COM Pins Hardware Configuration*/
lixianyu 0:d8f4c441e032 60 0x81,0xdf, /*Set Current Control */
lixianyu 0:d8f4c441e032 61 0xd9,0x82, /*Set Pre-Charge Period */
lixianyu 0:d8f4c441e032 62 0xdb,0x34, /*Set VCOMH Deselect Level */
lixianyu 0:d8f4c441e032 63 0xa4, /*Set Entire Display On/Off */
lixianyu 0:d8f4c441e032 64 0xa6, /*Set Normal/Inverse Display*/
lixianyu 0:d8f4c441e032 65 U8G_ESC_VCC(1), /*Power up VCC & Stabilized */
lixianyu 0:d8f4c441e032 66 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 67 0xaf, /*Set Display On */
lixianyu 0:d8f4c441e032 68 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 69 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 70 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 71 };
lixianyu 0:d8f4c441e032 72
lixianyu 0:d8f4c441e032 73 /* select one init sequence here */
lixianyu 0:d8f4c441e032 74 #define u8g_dev_ssd1309_128x64_init_seq u8g_dev_ssd1309_128x64_init_seq
lixianyu 0:d8f4c441e032 75
lixianyu 0:d8f4c441e032 76
lixianyu 0:d8f4c441e032 77 static const uint8_t u8g_dev_ssd1309_128x64_data_start[] PROGMEM = {
lixianyu 0:d8f4c441e032 78 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 79 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 80 0x010, /* set upper 4 bit of the col adr to 0 */
lixianyu 0:d8f4c441e032 81 0x000, /* set lower 4 bit of the col adr to 4 */
lixianyu 0:d8f4c441e032 82 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 83 };
lixianyu 0:d8f4c441e032 84
lixianyu 0:d8f4c441e032 85 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 86 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 87 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 88 0x0ae, /* display off */
lixianyu 0:d8f4c441e032 89 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 90 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 91 };
lixianyu 0:d8f4c441e032 92
lixianyu 0:d8f4c441e032 93 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 94 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 95 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 96 0x0af, /* display on */
lixianyu 0:d8f4c441e032 97 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 98 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 99 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 100 };
lixianyu 0:d8f4c441e032 101
lixianyu 0:d8f4c441e032 102 uint8_t u8g_dev_ssd1309_128x64_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 103 {
lixianyu 0:d8f4c441e032 104 switch(msg)
lixianyu 0:d8f4c441e032 105 {
lixianyu 0:d8f4c441e032 106 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 107 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 108 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1309_128x64_init_seq);
lixianyu 0:d8f4c441e032 109 break;
lixianyu 0:d8f4c441e032 110 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 111 break;
lixianyu 0:d8f4c441e032 112 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 113 {
lixianyu 0:d8f4c441e032 114 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 115 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1309_128x64_data_start);
lixianyu 0:d8f4c441e032 116 u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (SSD1306) */
lixianyu 0:d8f4c441e032 117 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 118 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
lixianyu 0:d8f4c441e032 119 return 0;
lixianyu 0:d8f4c441e032 120 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 121 }
lixianyu 0:d8f4c441e032 122 break;
lixianyu 0:d8f4c441e032 123 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 124 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 125 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 126 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 127 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) ); /* 11 Jul 2015: fixed contrast calculation */
lixianyu 0:d8f4c441e032 128 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 129 return 1;
lixianyu 0:d8f4c441e032 130 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 131 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 132 return 1;
lixianyu 0:d8f4c441e032 133 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 134 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 135 return 1;
lixianyu 0:d8f4c441e032 136 }
lixianyu 0:d8f4c441e032 137 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 138 }
lixianyu 0:d8f4c441e032 139
lixianyu 0:d8f4c441e032 140 U8G_PB_DEV(u8g_dev_ssd1309_128x64_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1309_128x64_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 141 U8G_PB_DEV(u8g_dev_ssd1309_128x64_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1309_128x64_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 142 U8G_PB_DEV(u8g_dev_ssd1309_128x64_i2c, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1309_128x64_fn, U8G_COM_SSD_I2C);
lixianyu 0:d8f4c441e032 143