hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1306_64x48.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ssd1306_64x48.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Copyright (c) 2011, olikraus@gmail.com
lixianyu 0:d8f4c441e032 8 All rights reserved.
lixianyu 0:d8f4c441e032 9
lixianyu 0:d8f4c441e032 10 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 11 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 14 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 17 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 18 materials provided with the distribution.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 33
lixianyu 0:d8f4c441e032 34
lixianyu 0:d8f4c441e032 35
lixianyu 0:d8f4c441e032 36 */
lixianyu 0:d8f4c441e032 37
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 #include "u8g.h"
lixianyu 0:d8f4c441e032 40
lixianyu 0:d8f4c441e032 41 #define WIDTH 64
lixianyu 0:d8f4c441e032 42 #define HEIGHT 48
lixianyu 0:d8f4c441e032 43 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 44
lixianyu 0:d8f4c441e032 45
lixianyu 0:d8f4c441e032 46
lixianyu 0:d8f4c441e032 47 /* init sequence buydisplay.com 0.66" 64x48 OLED */
lixianyu 0:d8f4c441e032 48 /* http://www.buydisplay.com/download/manual/ER-OLED0.66-1_Series_Datasheet.pdf */
lixianyu 0:d8f4c441e032 49 static const uint8_t u8g_dev_ssd1306_64x48_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 50 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 51 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 52 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 53 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 54
lixianyu 0:d8f4c441e032 55 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 56 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
lixianyu 0:d8f4c441e032 57 0x0a8, 0x02f, /* Multiplex Ration, Jul 12, 2015: From 0.66" OLED datasheet */
lixianyu 0:d8f4c441e032 58
lixianyu 0:d8f4c441e032 59 0x0d3, 0x000, /* */
lixianyu 0:d8f4c441e032 60
lixianyu 0:d8f4c441e032 61 0x040, /* start line */
lixianyu 0:d8f4c441e032 62
lixianyu 0:d8f4c441e032 63 0x08d, 0x014, /* charge pump setting (p62): 0x014 enable, 0x010 disable */
lixianyu 0:d8f4c441e032 64
lixianyu 0:d8f4c441e032 65 //0x020, 0x002, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Feb 23, 2013: 64x48 OLED: 0x002, 64x48 OLED 0x012 */
lixianyu 0:d8f4c441e032 66 0x0a1, /* segment remap a0/a1*/
lixianyu 0:d8f4c441e032 67 0x0c8, /* c0: scan dir normal, c8: reverse */
lixianyu 0:d8f4c441e032 68 0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Jul 12, 2015: From 0.66" OLED datasheet */
lixianyu 0:d8f4c441e032 69 0x081, 0x0cf, /* set contrast control */
lixianyu 0:d8f4c441e032 70 0x0d9, 0x022, /* pre-charge period 0x022/f1, from 0.66" OLED datasheet */
lixianyu 0:d8f4c441e032 71 0x0db, 0x000, /* vcomh deselect level, from 0.66" OLED datasheet */
lixianyu 0:d8f4c441e032 72
lixianyu 0:d8f4c441e032 73 0x02e, /* 2012-05-27: Deactivate scroll */
lixianyu 0:d8f4c441e032 74 0x0a4, /* output ram to display */
lixianyu 0:d8f4c441e032 75 0x0a6, /* none inverted normal display mode */
lixianyu 0:d8f4c441e032 76 0x0af, /* display on */
lixianyu 0:d8f4c441e032 77
lixianyu 0:d8f4c441e032 78 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 79 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 80 };
lixianyu 0:d8f4c441e032 81
lixianyu 0:d8f4c441e032 82
lixianyu 0:d8f4c441e032 83
lixianyu 0:d8f4c441e032 84
lixianyu 0:d8f4c441e032 85 static const uint8_t u8g_dev_ssd1306_64x48_data_start[] PROGMEM = {
lixianyu 0:d8f4c441e032 86 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 87 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 88 0x010+2, /* set upper 4 bit of the col adr. to 0, 0.66" OLED starts with offset 32 */
lixianyu 0:d8f4c441e032 89 0x000, /* set lower 4 bit of the col adr. to 4 */
lixianyu 0:d8f4c441e032 90 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 91 };
lixianyu 0:d8f4c441e032 92
lixianyu 0:d8f4c441e032 93 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 94 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 95 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 96 0x0ae, /* display off */
lixianyu 0:d8f4c441e032 97 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 98 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 99 };
lixianyu 0:d8f4c441e032 100
lixianyu 0:d8f4c441e032 101 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 102 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 103 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 104 0x0af, /* display on */
lixianyu 0:d8f4c441e032 105 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 106 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 107 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 108 };
lixianyu 0:d8f4c441e032 109
lixianyu 0:d8f4c441e032 110 uint8_t u8g_dev_ssd1306_64x48_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 111 {
lixianyu 0:d8f4c441e032 112 switch(msg)
lixianyu 0:d8f4c441e032 113 {
lixianyu 0:d8f4c441e032 114 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 115 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 116 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_64x48_init_seq);
lixianyu 0:d8f4c441e032 117 break;
lixianyu 0:d8f4c441e032 118 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 119 break;
lixianyu 0:d8f4c441e032 120 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 121 {
lixianyu 0:d8f4c441e032 122 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 123 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_64x48_data_start);
lixianyu 0:d8f4c441e032 124 u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (SSD1306) */
lixianyu 0:d8f4c441e032 125 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 126 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
lixianyu 0:d8f4c441e032 127 return 0;
lixianyu 0:d8f4c441e032 128 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 129 }
lixianyu 0:d8f4c441e032 130 break;
lixianyu 0:d8f4c441e032 131 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 132 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 133 return 1;
lixianyu 0:d8f4c441e032 134 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 135 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 136 return 1;
lixianyu 0:d8f4c441e032 137 }
lixianyu 0:d8f4c441e032 138
lixianyu 0:d8f4c441e032 139 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 140 }
lixianyu 0:d8f4c441e032 141
lixianyu 0:d8f4c441e032 142 uint8_t u8g_dev_ssd1306_64x48_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 143 {
lixianyu 0:d8f4c441e032 144 switch(msg)
lixianyu 0:d8f4c441e032 145 {
lixianyu 0:d8f4c441e032 146 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 147 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 148 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_64x48_init_seq);
lixianyu 0:d8f4c441e032 149 break;
lixianyu 0:d8f4c441e032 150 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 151 break;
lixianyu 0:d8f4c441e032 152 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 153 {
lixianyu 0:d8f4c441e032 154 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 155
lixianyu 0:d8f4c441e032 156 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_64x48_data_start);
lixianyu 0:d8f4c441e032 157 u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2)); /* select current page (SSD1306) */
lixianyu 0:d8f4c441e032 158 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 159 u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
lixianyu 0:d8f4c441e032 160 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 161
lixianyu 0:d8f4c441e032 162 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_64x48_data_start);
lixianyu 0:d8f4c441e032 163 u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2+1)); /* select current page (SSD1306) */
lixianyu 0:d8f4c441e032 164 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 165 u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
lixianyu 0:d8f4c441e032 166 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 167 }
lixianyu 0:d8f4c441e032 168 break;
lixianyu 0:d8f4c441e032 169 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 170 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 171 return 1;
lixianyu 0:d8f4c441e032 172 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 173 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 174 return 1;
lixianyu 0:d8f4c441e032 175 }
lixianyu 0:d8f4c441e032 176 return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 177 }
lixianyu 0:d8f4c441e032 178
lixianyu 0:d8f4c441e032 179 U8G_PB_DEV(u8g_dev_ssd1306_64x48_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_64x48_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 180 U8G_PB_DEV(u8g_dev_ssd1306_64x48_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_64x48_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 181 U8G_PB_DEV(u8g_dev_ssd1306_64x48_i2c, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_64x48_fn, U8G_COM_SSD_I2C);
lixianyu 0:d8f4c441e032 182
lixianyu 0:d8f4c441e032 183 uint8_t u8g_dev_ssd1306_64x48_2x_buf[WIDTH*2] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 184 u8g_pb_t u8g_dev_ssd1306_64x48_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1306_64x48_2x_buf};
lixianyu 0:d8f4c441e032 185 u8g_dev_t u8g_dev_ssd1306_64x48_2x_sw_spi = { u8g_dev_ssd1306_64x48_2x_fn, &u8g_dev_ssd1306_64x48_2x_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 186 u8g_dev_t u8g_dev_ssd1306_64x48_2x_hw_spi = { u8g_dev_ssd1306_64x48_2x_fn, &u8g_dev_ssd1306_64x48_2x_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 187 u8g_dev_t u8g_dev_ssd1306_64x48_2x_i2c = { u8g_dev_ssd1306_64x48_2x_fn, &u8g_dev_ssd1306_64x48_2x_pb, U8G_COM_SSD_I2C };
lixianyu 0:d8f4c441e032 188