hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1306_128x32.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ssd1306_128x32.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Copyright (c) 2011, olikraus@gmail.com
lixianyu 0:d8f4c441e032 8 All rights reserved.
lixianyu 0:d8f4c441e032 9
lixianyu 0:d8f4c441e032 10 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 11 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 14 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 17 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 18 materials provided with the distribution.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 33
lixianyu 0:d8f4c441e032 34
lixianyu 0:d8f4c441e032 35 23 Feb 2013: Fixed, Issue 147
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 */
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39
lixianyu 0:d8f4c441e032 40 #include "u8g.h"
lixianyu 0:d8f4c441e032 41
lixianyu 0:d8f4c441e032 42 #define WIDTH 128
lixianyu 0:d8f4c441e032 43 #define HEIGHT 32
lixianyu 0:d8f4c441e032 44 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 45
lixianyu 0:d8f4c441e032 46
lixianyu 0:d8f4c441e032 47 /* init sequence adafruit 128x32 OLED (NOT TESTED) */
lixianyu 0:d8f4c441e032 48 static const uint8_t u8g_dev_ssd1306_128x32_adafruit1_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 49 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 50 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 51 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 52 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 53
lixianyu 0:d8f4c441e032 54 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 55 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
lixianyu 0:d8f4c441e032 56 0x0a8, 0x03f, /* */
lixianyu 0:d8f4c441e032 57
lixianyu 0:d8f4c441e032 58 0x0d3, 0x000, /* */
lixianyu 0:d8f4c441e032 59
lixianyu 0:d8f4c441e032 60 0x040, /* start line */
lixianyu 0:d8f4c441e032 61
lixianyu 0:d8f4c441e032 62 0x08d, 0x010, /* [1] charge pump setting (p62): 0x014 enable, 0x010 disable */
lixianyu 0:d8f4c441e032 63
lixianyu 0:d8f4c441e032 64 0x020, 0x000, /* */
lixianyu 0:d8f4c441e032 65 0x0a1, /* segment remap a0/a1*/
lixianyu 0:d8f4c441e032 66 0x0c8, /* c0: scan dir normal, c8: reverse */
lixianyu 0:d8f4c441e032 67 0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
lixianyu 0:d8f4c441e032 68 0x081, 0x09f, /* [1] set contrast control */
lixianyu 0:d8f4c441e032 69 0x0d9, 0x022, /* [1] pre-charge period 0x022/f1*/
lixianyu 0:d8f4c441e032 70 0x0db, 0x040, /* vcomh deselect level */
lixianyu 0:d8f4c441e032 71
lixianyu 0:d8f4c441e032 72 0x02e, /* 2012-05-27: Deactivate scroll */
lixianyu 0:d8f4c441e032 73 0x0a4, /* output ram to display */
lixianyu 0:d8f4c441e032 74 0x0a6, /* none inverted normal display mode */
lixianyu 0:d8f4c441e032 75 0x0af, /* display on */
lixianyu 0:d8f4c441e032 76
lixianyu 0:d8f4c441e032 77 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 78 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 79 };
lixianyu 0:d8f4c441e032 80
lixianyu 0:d8f4c441e032 81
lixianyu 0:d8f4c441e032 82 /* init sequence adafruit 128x32 OLED (NOT TESTED) */
lixianyu 0:d8f4c441e032 83 static const uint8_t u8g_dev_ssd1306_128x32_adafruit2_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 84 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 85 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 86 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 87 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 88
lixianyu 0:d8f4c441e032 89 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 90 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
lixianyu 0:d8f4c441e032 91 0x0a8, 0x03f, /* */
lixianyu 0:d8f4c441e032 92
lixianyu 0:d8f4c441e032 93 0x0d3, 0x000, /* */
lixianyu 0:d8f4c441e032 94
lixianyu 0:d8f4c441e032 95 0x040, /* start line */
lixianyu 0:d8f4c441e032 96
lixianyu 0:d8f4c441e032 97 0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
lixianyu 0:d8f4c441e032 98
lixianyu 0:d8f4c441e032 99 0x020, 0x000, /* */
lixianyu 0:d8f4c441e032 100 0x0a1, /* segment remap a0/a1*/
lixianyu 0:d8f4c441e032 101 0x0c8, /* c0: scan dir normal, c8: reverse */
lixianyu 0:d8f4c441e032 102 0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
lixianyu 0:d8f4c441e032 103 0x081, 0x0cf, /* [2] set contrast control */
lixianyu 0:d8f4c441e032 104 0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
lixianyu 0:d8f4c441e032 105 0x0db, 0x040, /* vcomh deselect level */
lixianyu 0:d8f4c441e032 106
lixianyu 0:d8f4c441e032 107 0x02e, /* 2012-05-27: Deactivate scroll */
lixianyu 0:d8f4c441e032 108 0x0a4, /* output ram to display */
lixianyu 0:d8f4c441e032 109 0x0a6, /* none inverted normal display mode */
lixianyu 0:d8f4c441e032 110 0x0af, /* display on */
lixianyu 0:d8f4c441e032 111
lixianyu 0:d8f4c441e032 112 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 113 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 114 };
lixianyu 0:d8f4c441e032 115
lixianyu 0:d8f4c441e032 116
lixianyu 0:d8f4c441e032 117 /* init sequence adafruit 128x32 OLED (TESTED - WORKING 23.02.13), like adafruit3, but with page addressing mode */
lixianyu 0:d8f4c441e032 118 static const uint8_t u8g_dev_ssd1306_128x32_adafruit3_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 119 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 120 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 121 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 122 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 123
lixianyu 0:d8f4c441e032 124 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 125 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
lixianyu 0:d8f4c441e032 126 0x0a8, 0x01f, /* Feb 23, 2013: 128x32 OLED: 0x01f, 128x32 OLED 0x03f */
lixianyu 0:d8f4c441e032 127
lixianyu 0:d8f4c441e032 128 0x0d3, 0x000, /* */
lixianyu 0:d8f4c441e032 129
lixianyu 0:d8f4c441e032 130 0x040, /* start line */
lixianyu 0:d8f4c441e032 131
lixianyu 0:d8f4c441e032 132 0x08d, 0x014, /* [2] charge pump setting (p62): 0x014 enable, 0x010 disable */
lixianyu 0:d8f4c441e032 133
lixianyu 0:d8f4c441e032 134 0x020, 0x002, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5), Feb 23, 2013: 128x32 OLED: 0x002, 128x32 OLED 0x012 */
lixianyu 0:d8f4c441e032 135 0x0a1, /* segment remap a0/a1*/
lixianyu 0:d8f4c441e032 136 0x0c8, /* c0: scan dir normal, c8: reverse */
lixianyu 0:d8f4c441e032 137 0x0da, 0x002, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
lixianyu 0:d8f4c441e032 138 0x081, 0x0cf, /* [2] set contrast control */
lixianyu 0:d8f4c441e032 139 0x0d9, 0x0f1, /* [2] pre-charge period 0x022/f1*/
lixianyu 0:d8f4c441e032 140 0x0db, 0x040, /* vcomh deselect level */
lixianyu 0:d8f4c441e032 141
lixianyu 0:d8f4c441e032 142 0x02e, /* 2012-05-27: Deactivate scroll */
lixianyu 0:d8f4c441e032 143 0x0a4, /* output ram to display */
lixianyu 0:d8f4c441e032 144 0x0a6, /* none inverted normal display mode */
lixianyu 0:d8f4c441e032 145 0x0af, /* display on */
lixianyu 0:d8f4c441e032 146
lixianyu 0:d8f4c441e032 147 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 148 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 149 };
lixianyu 0:d8f4c441e032 150
lixianyu 0:d8f4c441e032 151
lixianyu 0:d8f4c441e032 152 /* init sequence Univision datasheet (NOT TESTED) */
lixianyu 0:d8f4c441e032 153 static const uint8_t u8g_dev_ssd1306_128x32_univision_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 154 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 155 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 156 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 157 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 158
lixianyu 0:d8f4c441e032 159 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 160 0x0d5, 0x080, /* clock divide ratio (0x00=1) and oscillator frequency (0x8) */
lixianyu 0:d8f4c441e032 161 0x0a8, 0x03f, /* multiplex ratio */
lixianyu 0:d8f4c441e032 162 0x0d3, 0x000, /* display offset */
lixianyu 0:d8f4c441e032 163 0x040, /* start line */
lixianyu 0:d8f4c441e032 164 0x08d, 0x010, /* charge pump setting (p62): 0x014 enable, 0x010 disable */
lixianyu 0:d8f4c441e032 165 0x0a1, /* segment remap a0/a1*/
lixianyu 0:d8f4c441e032 166 0x0c8, /* c0: scan dir normal, c8: reverse */
lixianyu 0:d8f4c441e032 167 0x0da, 0x012, /* com pin HW config, sequential com pin config (bit 4), disable left/right remap (bit 5) */
lixianyu 0:d8f4c441e032 168 0x081, 0x09f, /* set contrast control */
lixianyu 0:d8f4c441e032 169 0x0d9, 0x022, /* pre-charge period */
lixianyu 0:d8f4c441e032 170 0x0db, 0x040, /* vcomh deselect level */
lixianyu 0:d8f4c441e032 171 0x022, 0x000, /* page addressing mode WRONG: 3 byte cmd! */
lixianyu 0:d8f4c441e032 172 0x0a4, /* output ram to display */
lixianyu 0:d8f4c441e032 173 0x0a6, /* none inverted normal display mode */
lixianyu 0:d8f4c441e032 174 0x0af, /* display on */
lixianyu 0:d8f4c441e032 175 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 176 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 177 };
lixianyu 0:d8f4c441e032 178
lixianyu 0:d8f4c441e032 179
lixianyu 0:d8f4c441e032 180 /* select one init sequence here */
lixianyu 0:d8f4c441e032 181 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_univision_init_seq
lixianyu 0:d8f4c441e032 182 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit1_init_seq
lixianyu 0:d8f4c441e032 183 //define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit2_init_seq
lixianyu 0:d8f4c441e032 184 #define u8g_dev_ssd1306_128x32_init_seq u8g_dev_ssd1306_128x32_adafruit3_init_seq
lixianyu 0:d8f4c441e032 185
lixianyu 0:d8f4c441e032 186
lixianyu 0:d8f4c441e032 187 static const uint8_t u8g_dev_ssd1306_128x32_data_start[] PROGMEM = {
lixianyu 0:d8f4c441e032 188 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 189 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 190 0x010, /* set upper 4 bit of the col adr. to 0 */
lixianyu 0:d8f4c441e032 191 0x000, /* set lower 4 bit of the col adr. to 4 */
lixianyu 0:d8f4c441e032 192 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 193 };
lixianyu 0:d8f4c441e032 194
lixianyu 0:d8f4c441e032 195 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 196 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 197 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 198 0x0ae, /* display off */
lixianyu 0:d8f4c441e032 199 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 200 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 201 };
lixianyu 0:d8f4c441e032 202
lixianyu 0:d8f4c441e032 203 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 204 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 205 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 206 0x0af, /* display on */
lixianyu 0:d8f4c441e032 207 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 208 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 209 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 210 };
lixianyu 0:d8f4c441e032 211
lixianyu 0:d8f4c441e032 212 uint8_t u8g_dev_ssd1306_128x32_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 213 {
lixianyu 0:d8f4c441e032 214 switch(msg)
lixianyu 0:d8f4c441e032 215 {
lixianyu 0:d8f4c441e032 216 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 217 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 218 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_init_seq);
lixianyu 0:d8f4c441e032 219 break;
lixianyu 0:d8f4c441e032 220 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 221 break;
lixianyu 0:d8f4c441e032 222 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 223 {
lixianyu 0:d8f4c441e032 224 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 225 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
lixianyu 0:d8f4c441e032 226 u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (SSD1306) */
lixianyu 0:d8f4c441e032 227 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 228 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
lixianyu 0:d8f4c441e032 229 return 0;
lixianyu 0:d8f4c441e032 230 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 231 }
lixianyu 0:d8f4c441e032 232 break;
lixianyu 0:d8f4c441e032 233 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 234 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 235 return 1;
lixianyu 0:d8f4c441e032 236 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 237 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 238 return 1;
lixianyu 0:d8f4c441e032 239 }
lixianyu 0:d8f4c441e032 240
lixianyu 0:d8f4c441e032 241 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 242 }
lixianyu 0:d8f4c441e032 243
lixianyu 0:d8f4c441e032 244 uint8_t u8g_dev_ssd1306_128x32_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 245 {
lixianyu 0:d8f4c441e032 246 switch(msg)
lixianyu 0:d8f4c441e032 247 {
lixianyu 0:d8f4c441e032 248 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 249 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 250 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_init_seq);
lixianyu 0:d8f4c441e032 251 break;
lixianyu 0:d8f4c441e032 252 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 253 break;
lixianyu 0:d8f4c441e032 254 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 255 {
lixianyu 0:d8f4c441e032 256 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 257
lixianyu 0:d8f4c441e032 258 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
lixianyu 0:d8f4c441e032 259 u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2)); /* select current page (SSD1306) */
lixianyu 0:d8f4c441e032 260 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 261 u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
lixianyu 0:d8f4c441e032 262 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 263
lixianyu 0:d8f4c441e032 264 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1306_128x32_data_start);
lixianyu 0:d8f4c441e032 265 u8g_WriteByte(u8g, dev, 0x0b0 | (pb->p.page*2+1)); /* select current page (SSD1306) */
lixianyu 0:d8f4c441e032 266 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 267 u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
lixianyu 0:d8f4c441e032 268 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 269 }
lixianyu 0:d8f4c441e032 270 break;
lixianyu 0:d8f4c441e032 271 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 272 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 273 return 1;
lixianyu 0:d8f4c441e032 274 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 275 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 276 return 1;
lixianyu 0:d8f4c441e032 277 }
lixianyu 0:d8f4c441e032 278 return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 279 }
lixianyu 0:d8f4c441e032 280
lixianyu 0:d8f4c441e032 281 U8G_PB_DEV(u8g_dev_ssd1306_128x32_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 282 U8G_PB_DEV(u8g_dev_ssd1306_128x32_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 283 U8G_PB_DEV(u8g_dev_ssd1306_128x32_i2c, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ssd1306_128x32_fn, U8G_COM_SSD_I2C);
lixianyu 0:d8f4c441e032 284
lixianyu 0:d8f4c441e032 285 uint8_t u8g_dev_ssd1306_128x32_2x_buf[WIDTH*2] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 286 u8g_pb_t u8g_dev_ssd1306_128x32_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1306_128x32_2x_buf};
lixianyu 0:d8f4c441e032 287 u8g_dev_t u8g_dev_ssd1306_128x32_2x_sw_spi = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 288 u8g_dev_t u8g_dev_ssd1306_128x32_2x_hw_spi = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 289 u8g_dev_t u8g_dev_ssd1306_128x32_2x_i2c = { u8g_dev_ssd1306_128x32_2x_fn, &u8g_dev_ssd1306_128x32_2x_pb, U8G_COM_SSD_I2C };
lixianyu 0:d8f4c441e032 290