hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ld7032_60x32.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ld7032_60x32.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 60x32 OLED display
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 8
lixianyu 0:d8f4c441e032 9 Copyright (c) 2011, olikraus@gmail.com
lixianyu 0:d8f4c441e032 10 All rights reserved.
lixianyu 0:d8f4c441e032 11
lixianyu 0:d8f4c441e032 12 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 13 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 14
lixianyu 0:d8f4c441e032 15 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 16 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 17
lixianyu 0:d8f4c441e032 18 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 19 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 20 materials provided with the distribution.
lixianyu 0:d8f4c441e032 21
lixianyu 0:d8f4c441e032 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 23 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 24 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 25 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 27 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 28 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 31 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 32 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 34 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 35
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 */
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 #include "u8g.h"
lixianyu 0:d8f4c441e032 40
lixianyu 0:d8f4c441e032 41 /* define width as 64, so that it is a multiple of 8 */
lixianyu 0:d8f4c441e032 42 #define WIDTH 64
lixianyu 0:d8f4c441e032 43 #define HEIGHT 32
lixianyu 0:d8f4c441e032 44 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 45
lixianyu 0:d8f4c441e032 46 static const uint8_t u8g_dev_ld7032_60x32_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 47 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 48 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 49 U8G_ESC_DLY(1), /* delay 1 ms */
lixianyu 0:d8f4c441e032 50 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 51 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 52
lixianyu 0:d8f4c441e032 53
lixianyu 0:d8f4c441e032 54 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 55 0x002, /* Dot Matrix Display ON/OFF */
lixianyu 0:d8f4c441e032 56 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 57 0x001, /* ON */
lixianyu 0:d8f4c441e032 58
lixianyu 0:d8f4c441e032 59 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 60 0x014, /* Dot Matrix Display Stand-by ON/OFF */
lixianyu 0:d8f4c441e032 61 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 62 0x000, /* ON */
lixianyu 0:d8f4c441e032 63
lixianyu 0:d8f4c441e032 64 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 65 0x01a, /* Dot Matrix Frame Rate */
lixianyu 0:d8f4c441e032 66 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 67 0x004, /* special value for this OLED from manual */
lixianyu 0:d8f4c441e032 68
lixianyu 0:d8f4c441e032 69 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 70 0x01d, /* Graphics Memory Writing Direction */
lixianyu 0:d8f4c441e032 71 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 72 0x000, /* reset default (right down, horizontal) */
lixianyu 0:d8f4c441e032 73
lixianyu 0:d8f4c441e032 74 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 75 0x009, /* Display Direction */
lixianyu 0:d8f4c441e032 76 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 77 0x000, /* reset default (x,y: min --> max) */
lixianyu 0:d8f4c441e032 78
lixianyu 0:d8f4c441e032 79 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 80 0x030, /* Display Size X */
lixianyu 0:d8f4c441e032 81 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 82 0x000, /* Column Start Output */
lixianyu 0:d8f4c441e032 83 0x03b, /* Column End Output */
lixianyu 0:d8f4c441e032 84
lixianyu 0:d8f4c441e032 85 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 86 0x032, /* Display Size Y */
lixianyu 0:d8f4c441e032 87 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 88 0x000, /* Row Start Output */
lixianyu 0:d8f4c441e032 89 0x01f, /* Row End Output */
lixianyu 0:d8f4c441e032 90
lixianyu 0:d8f4c441e032 91 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 92 0x010, /* Peak Pulse Width Set */
lixianyu 0:d8f4c441e032 93 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 94 0x000, /* 0 SCLK */
lixianyu 0:d8f4c441e032 95
lixianyu 0:d8f4c441e032 96 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 97 0x016, /* Peak Pulse Delay Set */
lixianyu 0:d8f4c441e032 98 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 99 0x000, /* 0 SCLK */
lixianyu 0:d8f4c441e032 100
lixianyu 0:d8f4c441e032 101 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 102 0x012, /* Dot Matrix Current Level Set */
lixianyu 0:d8f4c441e032 103 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 104 0x050, /* 0x050 * 1 uA = 80 uA */
lixianyu 0:d8f4c441e032 105
lixianyu 0:d8f4c441e032 106 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 107 0x018, /* Pre-Charge Pulse Width */
lixianyu 0:d8f4c441e032 108 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 109 0x003, /* 3 SCLK */
lixianyu 0:d8f4c441e032 110
lixianyu 0:d8f4c441e032 111 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 112 0x044, /* Pre-Charge Mode */
lixianyu 0:d8f4c441e032 113 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 114 0x002, /* Every Time */
lixianyu 0:d8f4c441e032 115
lixianyu 0:d8f4c441e032 116 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 117 0x048, /* Row overlap timing */
lixianyu 0:d8f4c441e032 118 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 119 0x003, /* Pre-Charge + Peak Delay + Peak boot Timing */
lixianyu 0:d8f4c441e032 120
lixianyu 0:d8f4c441e032 121 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 122 0x03f, /* VCC_R_SEL */
lixianyu 0:d8f4c441e032 123 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 124 0x011, /* ??? */
lixianyu 0:d8f4c441e032 125
lixianyu 0:d8f4c441e032 126 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 127 0x03d, /* VSS selection */
lixianyu 0:d8f4c441e032 128 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 129 0x000, /* 2.8V */
lixianyu 0:d8f4c441e032 130
lixianyu 0:d8f4c441e032 131 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 132 0x002, /* Dot Matrix Display ON/OFF */
lixianyu 0:d8f4c441e032 133 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 134 0x001, /* ON */
lixianyu 0:d8f4c441e032 135
lixianyu 0:d8f4c441e032 136 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 137 0x008, /* write data */
lixianyu 0:d8f4c441e032 138
lixianyu 0:d8f4c441e032 139 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 140 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 141 };
lixianyu 0:d8f4c441e032 142
lixianyu 0:d8f4c441e032 143 /* use box commands to set start adr */
lixianyu 0:d8f4c441e032 144 static const uint8_t u8g_dev_ld7032_60x32_data_start[] PROGMEM = {
lixianyu 0:d8f4c441e032 145 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 146 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 147
lixianyu 0:d8f4c441e032 148
lixianyu 0:d8f4c441e032 149 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 150 0x034, /* box x start */
lixianyu 0:d8f4c441e032 151 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 152 0x000, /* 0 */
lixianyu 0:d8f4c441e032 153
lixianyu 0:d8f4c441e032 154 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 155 0x035, /* box x end */
lixianyu 0:d8f4c441e032 156 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 157 0x007, /* */
lixianyu 0:d8f4c441e032 158
lixianyu 0:d8f4c441e032 159 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 160 0x037, /* box y end */
lixianyu 0:d8f4c441e032 161 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 162 0x01f, /* */
lixianyu 0:d8f4c441e032 163
lixianyu 0:d8f4c441e032 164 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 165 0x036, /* box y start */
lixianyu 0:d8f4c441e032 166 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 167
lixianyu 0:d8f4c441e032 168 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 169 };
lixianyu 0:d8f4c441e032 170
lixianyu 0:d8f4c441e032 171 static const uint8_t u8g_dev_ld7032_60x32_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 172 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 173 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 174 /* ... */
lixianyu 0:d8f4c441e032 175 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 176 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 177 };
lixianyu 0:d8f4c441e032 178
lixianyu 0:d8f4c441e032 179 static const uint8_t u8g_dev_ld7032_60x32_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 180 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 181 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 182 /* ... */
lixianyu 0:d8f4c441e032 183 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 184 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 185 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 186 };
lixianyu 0:d8f4c441e032 187
lixianyu 0:d8f4c441e032 188 uint8_t u8g_dev_ld7032_60x32_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 189 {
lixianyu 0:d8f4c441e032 190 switch(msg)
lixianyu 0:d8f4c441e032 191 {
lixianyu 0:d8f4c441e032 192 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 193 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
lixianyu 0:d8f4c441e032 194 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ld7032_60x32_init_seq);
lixianyu 0:d8f4c441e032 195 break;
lixianyu 0:d8f4c441e032 196 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 197 break;
lixianyu 0:d8f4c441e032 198 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 199 {
lixianyu 0:d8f4c441e032 200 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 201 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ld7032_60x32_data_start);
lixianyu 0:d8f4c441e032 202 u8g_WriteByte(u8g, dev, pb->p.page_y0); /* y start */
lixianyu 0:d8f4c441e032 203 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 204 u8g_WriteByte(u8g, dev, 0x008);
lixianyu 0:d8f4c441e032 205 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 206 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
lixianyu 0:d8f4c441e032 207 return 0;
lixianyu 0:d8f4c441e032 208 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 209 }
lixianyu 0:d8f4c441e032 210 break;
lixianyu 0:d8f4c441e032 211 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 212 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 213 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 214 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 215 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
lixianyu 0:d8f4c441e032 216 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 217 return 1;
lixianyu 0:d8f4c441e032 218 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 219 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ld7032_60x32_sleep_on);
lixianyu 0:d8f4c441e032 220 return 1;
lixianyu 0:d8f4c441e032 221 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 222 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ld7032_60x32_sleep_off);
lixianyu 0:d8f4c441e032 223 return 1;
lixianyu 0:d8f4c441e032 224 }
lixianyu 0:d8f4c441e032 225 return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 226 }
lixianyu 0:d8f4c441e032 227
lixianyu 0:d8f4c441e032 228 U8G_PB_DEV(u8g_dev_ld7032_60x32_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ld7032_60x32_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 229 U8G_PB_DEV(u8g_dev_ld7032_60x32_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ld7032_60x32_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 230 U8G_PB_DEV(u8g_dev_ld7032_60x32_parallel, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ld7032_60x32_fn, U8G_COM_PARALLEL);
lixianyu 0:d8f4c441e032 231 U8G_PB_DEV(u8g_dev_ld7032_60x32_hw_usart_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ld7032_60x32_fn, U8G_COM_HW_USART_SPI);
lixianyu 0:d8f4c441e032 232
lixianyu 0:d8f4c441e032 233