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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_uc1701_mini12864.c@0:d8f4c441e032, 2016-06-10 (annotated)

Committer:
lixianyu
Date:
Fri Jun 10 15:20:20 2016 +0000
Revision:
0:d8f4c441e032
u8glib???????????i2c???

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_uc1701_mini12864.c (dealextreme)
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Copyright (c) 2011, olikraus@gmail.com
lixianyu 0:d8f4c441e032 8 All rights reserved.
lixianyu 0:d8f4c441e032 9
lixianyu 0:d8f4c441e032 10 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 11 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 14 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 17 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 18 materials provided with the distribution.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 33
lixianyu 0:d8f4c441e032 34
lixianyu 0:d8f4c441e032 35 */
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 #include "u8g.h"
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 #define WIDTH 128
lixianyu 0:d8f4c441e032 40 #define HEIGHT 64
lixianyu 0:d8f4c441e032 41 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 42
lixianyu 0:d8f4c441e032 43 static const uint8_t u8g_dev_uc1701_mini12864_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 44 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 45 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 46 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 47 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 48
lixianyu 0:d8f4c441e032 49 0x0e2, /* soft reset */
lixianyu 0:d8f4c441e032 50 0x040, /* set display start line to 0 */
lixianyu 0:d8f4c441e032 51 0x0a0, /* ADC set to reverse */
lixianyu 0:d8f4c441e032 52 0x0c8, /* common output mode */
lixianyu 0:d8f4c441e032 53 0x0a6, /* display normal, bit val 0: LCD pixel off. */
lixianyu 0:d8f4c441e032 54 0x0a2, /* LCD bias 1/9 */
lixianyu 0:d8f4c441e032 55 0x02f, /* all power control circuits on */
lixianyu 0:d8f4c441e032 56 0x0f8, /* set booster ratio to */
lixianyu 0:d8f4c441e032 57 0x000, /* 4x */
lixianyu 0:d8f4c441e032 58 0x023, /* set V0 voltage resistor ratio to large */
lixianyu 0:d8f4c441e032 59 0x081, /* set contrast */
lixianyu 0:d8f4c441e032 60 0x027, /* contrast value */
lixianyu 0:d8f4c441e032 61 0x0ac, /* indicator */
lixianyu 0:d8f4c441e032 62 0x000, /* disable */
lixianyu 0:d8f4c441e032 63 0x0af, /* display on */
lixianyu 0:d8f4c441e032 64
lixianyu 0:d8f4c441e032 65 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 66 0x0a5, /* display all points, ST7565 */
lixianyu 0:d8f4c441e032 67 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 68 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 69 0x0a4, /* normal display */
lixianyu 0:d8f4c441e032 70 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 71 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 72 };
lixianyu 0:d8f4c441e032 73
lixianyu 0:d8f4c441e032 74 static const uint8_t u8g_dev_uc1701_mini12864_data_start[] PROGMEM = {
lixianyu 0:d8f4c441e032 75 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 76 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 77 0x010, /* set upper 4 bit of the col adr to 0 */
lixianyu 0:d8f4c441e032 78 0x000, /* set lower 4 bit of the col adr to 4 */
lixianyu 0:d8f4c441e032 79 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 80 };
lixianyu 0:d8f4c441e032 81
lixianyu 0:d8f4c441e032 82 uint8_t u8g_dev_uc1701_mini12864_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 83 {
lixianyu 0:d8f4c441e032 84 switch(msg)
lixianyu 0:d8f4c441e032 85 {
lixianyu 0:d8f4c441e032 86 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 87 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 88 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1701_mini12864_init_seq);
lixianyu 0:d8f4c441e032 89 break;
lixianyu 0:d8f4c441e032 90 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 91 break;
lixianyu 0:d8f4c441e032 92 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 93 {
lixianyu 0:d8f4c441e032 94 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 95 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1701_mini12864_data_start);
lixianyu 0:d8f4c441e032 96 u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page */
lixianyu 0:d8f4c441e032 97 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 98 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
lixianyu 0:d8f4c441e032 99 return 0;
lixianyu 0:d8f4c441e032 100 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 101 }
lixianyu 0:d8f4c441e032 102 break;
lixianyu 0:d8f4c441e032 103 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 104 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 105 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 106 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 107 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
lixianyu 0:d8f4c441e032 108 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 109 return 1;
lixianyu 0:d8f4c441e032 110 }
lixianyu 0:d8f4c441e032 111 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 112 }
lixianyu 0:d8f4c441e032 113
lixianyu 0:d8f4c441e032 114 uint8_t u8g_dev_uc1701_mini12864_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 115 {
lixianyu 0:d8f4c441e032 116 switch(msg)
lixianyu 0:d8f4c441e032 117 {
lixianyu 0:d8f4c441e032 118 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 119 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 120 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1701_mini12864_init_seq);
lixianyu 0:d8f4c441e032 121 break;
lixianyu 0:d8f4c441e032 122 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 123 break;
lixianyu 0:d8f4c441e032 124 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 125 {
lixianyu 0:d8f4c441e032 126 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 127
lixianyu 0:d8f4c441e032 128 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1701_mini12864_data_start);
lixianyu 0:d8f4c441e032 129 u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page */
lixianyu 0:d8f4c441e032 130 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 131 u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
lixianyu 0:d8f4c441e032 132 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 133
lixianyu 0:d8f4c441e032 134 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1701_mini12864_data_start);
lixianyu 0:d8f4c441e032 135 u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page */
lixianyu 0:d8f4c441e032 136 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 137 u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
lixianyu 0:d8f4c441e032 138 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 139 }
lixianyu 0:d8f4c441e032 140 break;
lixianyu 0:d8f4c441e032 141 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 142 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 143 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 144 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 145 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
lixianyu 0:d8f4c441e032 146 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 147 return 1;
lixianyu 0:d8f4c441e032 148 }
lixianyu 0:d8f4c441e032 149 return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 150 }
lixianyu 0:d8f4c441e032 151
lixianyu 0:d8f4c441e032 152 U8G_PB_DEV(u8g_dev_uc1701_mini12864_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_uc1701_mini12864_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 153 U8G_PB_DEV(u8g_dev_uc1701_mini12864_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_uc1701_mini12864_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 154
lixianyu 0:d8f4c441e032 155 uint8_t u8g_dev_uc1701_mini12864_2x_buf[WIDTH*2] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 156 u8g_pb_t u8g_dev_uc1701_mini12864_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_uc1701_mini12864_2x_buf};
lixianyu 0:d8f4c441e032 157 u8g_dev_t u8g_dev_uc1701_mini12864_2x_sw_spi = { u8g_dev_uc1701_mini12864_2x_fn, &u8g_dev_uc1701_mini12864_2x_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 158 u8g_dev_t u8g_dev_uc1701_mini12864_2x_hw_spi = { u8g_dev_uc1701_mini12864_2x_fn, &u8g_dev_uc1701_mini12864_2x_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 159