hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1325_nhd27oled_gr.c@0:d8f4c441e032, 2016-06-10 (annotated)

Committer:
lixianyu
Date:
Fri Jun 10 15:20:20 2016 +0000
Revision:
0:d8f4c441e032
u8glib???????????i2c???

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ssd1325_nhd27oled_gr.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 2-Bit (gray level) Driver for SSD1325 Controller (OLED Display)
lixianyu 0:d8f4c441e032 6 Tested with NHD-2.7-12864UCY3
lixianyu 0:d8f4c441e032 7
lixianyu 0:d8f4c441e032 8 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 9
lixianyu 0:d8f4c441e032 10 Copyright (c) 2011, olikraus@gmail.com
lixianyu 0:d8f4c441e032 11 All rights reserved.
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 14 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 17 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 18
lixianyu 0:d8f4c441e032 19 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 20 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 21 materials provided with the distribution.
lixianyu 0:d8f4c441e032 22
lixianyu 0:d8f4c441e032 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 24 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 25 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 26 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 28 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 29 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 31 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 32 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 33 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 35 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 SSD130x Monochrom OLED Controller
lixianyu 0:d8f4c441e032 38 SSD131x Character OLED Controller
lixianyu 0:d8f4c441e032 39 SSD132x Graylevel OLED Controller
lixianyu 0:d8f4c441e032 40 SSD1331 Color OLED Controller
lixianyu 0:d8f4c441e032 41
lixianyu 0:d8f4c441e032 42 */
lixianyu 0:d8f4c441e032 43
lixianyu 0:d8f4c441e032 44 #ifdef OBSOLETE_CODE
lixianyu 0:d8f4c441e032 45
lixianyu 0:d8f4c441e032 46 #include "u8g.h"
lixianyu 0:d8f4c441e032 47
lixianyu 0:d8f4c441e032 48 #define WIDTH 128
lixianyu 0:d8f4c441e032 49 #define HEIGHT 64
lixianyu 0:d8f4c441e032 50
lixianyu 0:d8f4c441e032 51 /* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
lixianyu 0:d8f4c441e032 52 static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 53 U8G_ESC_DLY(10), /* delay 10 ms */
lixianyu 0:d8f4c441e032 54 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 55 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 56 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 57 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 58 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 59 0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
lixianyu 0:d8f4c441e032 60 0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
lixianyu 0:d8f4c441e032 61 0x0a2, 0x04c, /* display offset, shift mapping ram counter */
lixianyu 0:d8f4c441e032 62 0x0a1, 0x000, /* display start line */
lixianyu 0:d8f4c441e032 63 0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
lixianyu 0:d8f4c441e032 64 0x0a0, 0x056, /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
lixianyu 0:d8f4c441e032 65 0x086, /* full current range (0x084, 0x085, 0x086) */
lixianyu 0:d8f4c441e032 66 0x0b8, /* set gray scale table */
lixianyu 0:d8f4c441e032 67 //0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
lixianyu 0:d8f4c441e032 68 0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
lixianyu 0:d8f4c441e032 69 0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
lixianyu 0:d8f4c441e032 70 0x0b2, 0x051, /* frame frequency (row period) */
lixianyu 0:d8f4c441e032 71 0x0b1, 0x055, /* phase length */
lixianyu 0:d8f4c441e032 72 0x0bc, 0x010, /* pre-charge voltage level */
lixianyu 0:d8f4c441e032 73 0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 74 0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 75 0x0be, 0x01c, /* VCOMH voltage */
lixianyu 0:d8f4c441e032 76 0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 77 0x0a5, /* all pixel on */
lixianyu 0:d8f4c441e032 78 0x0af, /* display on */
lixianyu 0:d8f4c441e032 79 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 80 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 81 0x0a4, /* normal display mode */
lixianyu 0:d8f4c441e032 82 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 83 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 84 };
lixianyu 0:d8f4c441e032 85
lixianyu 0:d8f4c441e032 86 static const uint8_t u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 87 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 88 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 89 0x015, /* column address... */
lixianyu 0:d8f4c441e032 90 0x000, /* start at column 0 */
lixianyu 0:d8f4c441e032 91 0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
lixianyu 0:d8f4c441e032 92 0x075, /* row address... */
lixianyu 0:d8f4c441e032 93 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 94 };
lixianyu 0:d8f4c441e032 95
lixianyu 0:d8f4c441e032 96
lixianyu 0:d8f4c441e032 97 static void u8g_dev_ssd1325_2bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
lixianyu 0:d8f4c441e032 98 {
lixianyu 0:d8f4c441e032 99 uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
lixianyu 0:d8f4c441e032 100
lixianyu 0:d8f4c441e032 101 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
lixianyu 0:d8f4c441e032 102
lixianyu 0:d8f4c441e032 103 page <<= 2;
lixianyu 0:d8f4c441e032 104 u8g_WriteByte(u8g, dev, page); /* start at the selected page */
lixianyu 0:d8f4c441e032 105 page += 3;
lixianyu 0:d8f4c441e032 106 u8g_WriteByte(u8g, dev, page); /* end within the selected page */
lixianyu 0:d8f4c441e032 107
lixianyu 0:d8f4c441e032 108 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 109 }
lixianyu 0:d8f4c441e032 110
lixianyu 0:d8f4c441e032 111 static void u8g_dev_ssd1325_2bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
lixianyu 0:d8f4c441e032 112 {
lixianyu 0:d8f4c441e032 113 uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
lixianyu 0:d8f4c441e032 114
lixianyu 0:d8f4c441e032 115 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_prepare_page_seq);
lixianyu 0:d8f4c441e032 116
lixianyu 0:d8f4c441e032 117 page <<= 1;
lixianyu 0:d8f4c441e032 118 page += is_odd;
lixianyu 0:d8f4c441e032 119
lixianyu 0:d8f4c441e032 120
lixianyu 0:d8f4c441e032 121 page <<= 2;
lixianyu 0:d8f4c441e032 122 u8g_WriteByte(u8g, dev, page); /* start at the selected page */
lixianyu 0:d8f4c441e032 123 page += 3;
lixianyu 0:d8f4c441e032 124 u8g_WriteByte(u8g, dev, page); /* end within the selected page */
lixianyu 0:d8f4c441e032 125
lixianyu 0:d8f4c441e032 126 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 127 }
lixianyu 0:d8f4c441e032 128
lixianyu 0:d8f4c441e032 129 /* assumes row autoincrement and activated nibble remap */
lixianyu 0:d8f4c441e032 130 static void u8g_dev_ssd1325_2bit_write_4_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
lixianyu 0:d8f4c441e032 131 {
lixianyu 0:d8f4c441e032 132 uint8_t d, tmp, cnt;
lixianyu 0:d8f4c441e032 133 cnt = 4;
lixianyu 0:d8f4c441e032 134 do
lixianyu 0:d8f4c441e032 135 {
lixianyu 0:d8f4c441e032 136 d = left;
lixianyu 0:d8f4c441e032 137 d &= 3;
lixianyu 0:d8f4c441e032 138 d <<= 4;
lixianyu 0:d8f4c441e032 139 tmp = right;
lixianyu 0:d8f4c441e032 140 tmp &= 3;
lixianyu 0:d8f4c441e032 141 d |= tmp;
lixianyu 0:d8f4c441e032 142 d <<= 2;
lixianyu 0:d8f4c441e032 143 u8g_WriteByte(u8g, dev, d);
lixianyu 0:d8f4c441e032 144 left >>= 2;
lixianyu 0:d8f4c441e032 145 right >>= 2;
lixianyu 0:d8f4c441e032 146 cnt--;
lixianyu 0:d8f4c441e032 147 }while ( cnt > 0 );
lixianyu 0:d8f4c441e032 148 }
lixianyu 0:d8f4c441e032 149
lixianyu 0:d8f4c441e032 150 static void u8g_dev_ssd1325_2bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev)
lixianyu 0:d8f4c441e032 151 {
lixianyu 0:d8f4c441e032 152 uint8_t cnt, left, right;
lixianyu 0:d8f4c441e032 153 uint8_t *ptr;
lixianyu 0:d8f4c441e032 154 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 155
lixianyu 0:d8f4c441e032 156 cnt = pb->width;
lixianyu 0:d8f4c441e032 157 cnt >>= 1;
lixianyu 0:d8f4c441e032 158 ptr = pb->buf;
lixianyu 0:d8f4c441e032 159 do
lixianyu 0:d8f4c441e032 160 {
lixianyu 0:d8f4c441e032 161 left = *ptr++;
lixianyu 0:d8f4c441e032 162 right = *ptr++;
lixianyu 0:d8f4c441e032 163 u8g_dev_ssd1325_2bit_write_4_pixel(u8g, dev, left, right);
lixianyu 0:d8f4c441e032 164 cnt--;
lixianyu 0:d8f4c441e032 165 } while( cnt > 0 );
lixianyu 0:d8f4c441e032 166 }
lixianyu 0:d8f4c441e032 167
lixianyu 0:d8f4c441e032 168 static void u8g_dev_ssd1325_2bit_2x_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
lixianyu 0:d8f4c441e032 169 {
lixianyu 0:d8f4c441e032 170 uint8_t cnt, left, right;
lixianyu 0:d8f4c441e032 171 uint8_t *ptr;
lixianyu 0:d8f4c441e032 172 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 173
lixianyu 0:d8f4c441e032 174 ptr = pb->buf;
lixianyu 0:d8f4c441e032 175 cnt = pb->width;
lixianyu 0:d8f4c441e032 176 if ( is_odd )
lixianyu 0:d8f4c441e032 177 ptr += cnt;
lixianyu 0:d8f4c441e032 178 cnt >>= 1;
lixianyu 0:d8f4c441e032 179 do
lixianyu 0:d8f4c441e032 180 {
lixianyu 0:d8f4c441e032 181 left = *ptr++;
lixianyu 0:d8f4c441e032 182 right = *ptr++;
lixianyu 0:d8f4c441e032 183 u8g_dev_ssd1325_2bit_write_4_pixel(u8g, dev, left, right);
lixianyu 0:d8f4c441e032 184 cnt--;
lixianyu 0:d8f4c441e032 185 } while( cnt > 0 );
lixianyu 0:d8f4c441e032 186 }
lixianyu 0:d8f4c441e032 187
lixianyu 0:d8f4c441e032 188 static uint8_t u8g_dev_ssd1325_nhd27oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 189 {
lixianyu 0:d8f4c441e032 190 switch(msg)
lixianyu 0:d8f4c441e032 191 {
lixianyu 0:d8f4c441e032 192 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 193 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 194 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
lixianyu 0:d8f4c441e032 195 break;
lixianyu 0:d8f4c441e032 196 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 197 break;
lixianyu 0:d8f4c441e032 198 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 199 {
lixianyu 0:d8f4c441e032 200 u8g_dev_ssd1325_2bit_prepare_page(u8g, dev);
lixianyu 0:d8f4c441e032 201 u8g_dev_ssd1325_2bit_write_buffer(u8g, dev);
lixianyu 0:d8f4c441e032 202 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 203 }
lixianyu 0:d8f4c441e032 204 break;
lixianyu 0:d8f4c441e032 205 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 206 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 207 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 208 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 209 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
lixianyu 0:d8f4c441e032 210 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 211 return 1;
lixianyu 0:d8f4c441e032 212 }
lixianyu 0:d8f4c441e032 213 return u8g_dev_pb8v2_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 214 }
lixianyu 0:d8f4c441e032 215
lixianyu 0:d8f4c441e032 216 static uint8_t u8g_dev_ssd1325_nhd27oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 217 {
lixianyu 0:d8f4c441e032 218 switch(msg)
lixianyu 0:d8f4c441e032 219 {
lixianyu 0:d8f4c441e032 220 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 221 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 222 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_2bit_nhd_27_12864ucy3_init_seq);
lixianyu 0:d8f4c441e032 223 break;
lixianyu 0:d8f4c441e032 224 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 225 break;
lixianyu 0:d8f4c441e032 226 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 227 {
lixianyu 0:d8f4c441e032 228 u8g_dev_ssd1325_2bit_2x_prepare_page(u8g, dev, 0);
lixianyu 0:d8f4c441e032 229 u8g_dev_ssd1325_2bit_2x_write_buffer(u8g, dev, 0);
lixianyu 0:d8f4c441e032 230 u8g_dev_ssd1325_2bit_2x_prepare_page(u8g, dev, 1);
lixianyu 0:d8f4c441e032 231 u8g_dev_ssd1325_2bit_2x_write_buffer(u8g, dev, 1);
lixianyu 0:d8f4c441e032 232 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 233 }
lixianyu 0:d8f4c441e032 234 break;
lixianyu 0:d8f4c441e032 235 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 236 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 237 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 238 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 239 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
lixianyu 0:d8f4c441e032 240 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 241 return 1;
lixianyu 0:d8f4c441e032 242 }
lixianyu 0:d8f4c441e032 243 return u8g_dev_pb16v2_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 244 }
lixianyu 0:d8f4c441e032 245
lixianyu 0:d8f4c441e032 246 //U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 247 //U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1325_nhd27oled_gr_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 248
lixianyu 0:d8f4c441e032 249 //uint8_t u8g_dev_ssd1325_nhd27oled_2x_buf[WIDTH*2] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 250 //u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_buf};
lixianyu 0:d8f4c441e032 251 //u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 252 //u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_gr_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_gr_fn, &u8g_dev_ssd1325_nhd27oled_2x_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 253
lixianyu 0:d8f4c441e032 254
lixianyu 0:d8f4c441e032 255 #endif /* OBSOLETE_CODE */
lixianyu 0:d8f4c441e032 256