hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_uc1608_240x128.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 u8g_dev_uc1608_240x128.c
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 8
lixianyu 0:d8f4c441e032 9 Copyright (c) 2013, olikraus@gmail.com (original 240x64 library)
lixianyu 0:d8f4c441e032 10 Modified by thieringpeti@gmail.com for Raystar rx240128 family displays
lixianyu 0:d8f4c441e032 11 All rights reserved.
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 14 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 17 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 18
lixianyu 0:d8f4c441e032 19 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 20 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 21 materials provided with the distribution.
lixianyu 0:d8f4c441e032 22
lixianyu 0:d8f4c441e032 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 24 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 25 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 26 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 28 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 29 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 31 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 32 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 33 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 35 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37
lixianyu 0:d8f4c441e032 38 */
lixianyu 0:d8f4c441e032 39
lixianyu 0:d8f4c441e032 40 /*
lixianyu 0:d8f4c441e032 41 Display: http://www.tme.eu/en/details/rx240128a-ghw/lcd-graphic-displays/raystar-optronics/
lixianyu 0:d8f4c441e032 42 Connection: HW / SW SPI.
lixianyu 0:d8f4c441e032 43 To get this display working, You need some extra capacitors:
lixianyu 0:d8f4c441e032 44
lixianyu 0:d8f4c441e032 45 connect 4.7uF caps between:
lixianyu 0:d8f4c441e032 46 PIN1 & PIN2 VB1 +-
lixianyu 0:d8f4c441e032 47 PIN3 & PIN4 VB0 -+
lixianyu 0:d8f4c441e032 48 connect 0.1uF caps between:
lixianyu 0:d8f4c441e032 49 VLCD and VSS
lixianyu 0:d8f4c441e032 50 VBIAS and VSS
lixianyu 0:d8f4c441e032 51 You can find some schematics with a 10M resistor parallellized with the VLCD capacitor.
lixianyu 0:d8f4c441e032 52
lixianyu 0:d8f4c441e032 53 Select 4-bit SPI mode.
lixianyu 0:d8f4c441e032 54
lixianyu 0:d8f4c441e032 55 Connect D7 (PIN9) To VDD (+3.3V)
lixianyu 0:d8f4c441e032 56 Connect D1, D2, D4, D5, D6 to GND (PINS 10,11,12,14,15)
lixianyu 0:d8f4c441e032 57 Connect WR0, WR1, BM0, BM1 to GND (PINS 17,18,22,23)
lixianyu 0:d8f4c441e032 58
lixianyu 0:d8f4c441e032 59 D0: (PIN16) AVR's SCK pin (HW SPI)
lixianyu 0:d8f4c441e032 60 D3: (PIN13) AVR's MOSI pin (HW SPI)
lixianyu 0:d8f4c441e032 61 CD: (PIN19) used as A0 in the library
lixianyu 0:d8f4c441e032 62 CS: (PIN21) Connect to the defined CS pin, and You can re-use the HW SPI in different routines.
lixianyu 0:d8f4c441e032 63 RST: (PIN20) optional reset, can be defined in the function, resets on initialization.
lixianyu 0:d8f4c441e032 64
lixianyu 0:d8f4c441e032 65 Adjust contrast if necessary. Default: 0x072.
lixianyu 0:d8f4c441e032 66
lixianyu 0:d8f4c441e032 67 */
lixianyu 0:d8f4c441e032 68
lixianyu 0:d8f4c441e032 69 #include "u8g.h"
lixianyu 0:d8f4c441e032 70
lixianyu 0:d8f4c441e032 71 #define WIDTH 240
lixianyu 0:d8f4c441e032 72 #define HEIGHT 128
lixianyu 0:d8f4c441e032 73 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 74
lixianyu 0:d8f4c441e032 75 /* see also ERC24064-1 for init sequence example */
lixianyu 0:d8f4c441e032 76 static const uint8_t u8g_dev_uc1608_240x128_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 77 U8G_ESC_CS(1), /* disable chip (UC1608 has positive logic for CS) */
lixianyu 0:d8f4c441e032 78 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 79 U8G_ESC_RST(1), /* do reset low pulse with (15*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 80
lixianyu 0:d8f4c441e032 81
lixianyu 0:d8f4c441e032 82 U8G_ESC_CS(0), /* enable chip */
lixianyu 0:d8f4c441e032 83 0x0e2, /* soft reset */
lixianyu 0:d8f4c441e032 84
lixianyu 0:d8f4c441e032 85 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 86 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 87 0x026, /* MUX rate and temperature compensation */
lixianyu 0:d8f4c441e032 88
lixianyu 0:d8f4c441e032 89 0x0c8, /* Map control, Bit 3: MY=1, Bit 2: MX=0, Bit 0: MSF =0 */
lixianyu 0:d8f4c441e032 90
lixianyu 0:d8f4c441e032 91 0x0eb, /* LCD bias Bits 0/1: 00=10.7 01=10.3, 10=12.0, 11=12.7*/
lixianyu 0:d8f4c441e032 92 /* default 0x0ea for 240x128 */
lixianyu 0:d8f4c441e032 93 0x081, /* set contrast (bits 0..5) and gain (bits 6/7) */
lixianyu 0:d8f4c441e032 94 0x072, /* default for 240x128 displays: 0x072*/
lixianyu 0:d8f4c441e032 95
lixianyu 0:d8f4c441e032 96 0x02f, /* power on, Bit 2 PC2=1 (internal charge pump), Bits 0/1: cap of panel */
lixianyu 0:d8f4c441e032 97 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 98
lixianyu 0:d8f4c441e032 99 0x040, /* set display start line to 0 */
lixianyu 0:d8f4c441e032 100 0x090, /* no fixed lines */
lixianyu 0:d8f4c441e032 101 0x089, /* RAM access control */
lixianyu 0:d8f4c441e032 102
lixianyu 0:d8f4c441e032 103 0x0af, /* disable sleep mode */
lixianyu 0:d8f4c441e032 104 0x0a4, /* normal display */
lixianyu 0:d8f4c441e032 105 0x0a5, /* display all points, ST7565, UC1610 */
lixianyu 0:d8f4c441e032 106 // 0x0a7, /* inverse display */
lixianyu 0:d8f4c441e032 107 0x0a6, /* normal display */
lixianyu 0:d8f4c441e032 108
lixianyu 0:d8f4c441e032 109 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 110 0x0a4, /* normal display */
lixianyu 0:d8f4c441e032 111 U8G_ESC_CS(1), /* disable chip */
lixianyu 0:d8f4c441e032 112 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 113 };
lixianyu 0:d8f4c441e032 114
lixianyu 0:d8f4c441e032 115 static const uint8_t u8g_dev_uc1608_240x128_data_start[] PROGMEM = {
lixianyu 0:d8f4c441e032 116 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 117 U8G_ESC_CS(0), /* enable chip */
lixianyu 0:d8f4c441e032 118 0x010, /* set upper 4 bit of the col adr to 0 (UC1608) */
lixianyu 0:d8f4c441e032 119 0x000, /* set lower 4 bit of the col adr to 0 */
lixianyu 0:d8f4c441e032 120 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 121 };
lixianyu 0:d8f4c441e032 122
lixianyu 0:d8f4c441e032 123 uint8_t u8g_dev_uc1608_240x128_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 124 {
lixianyu 0:d8f4c441e032 125 switch(msg)
lixianyu 0:d8f4c441e032 126 {
lixianyu 0:d8f4c441e032 127 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 128 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 129 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1608_240x128_init_seq);
lixianyu 0:d8f4c441e032 130 break;
lixianyu 0:d8f4c441e032 131 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 132 break;
lixianyu 0:d8f4c441e032 133 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 134 {
lixianyu 0:d8f4c441e032 135 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 136 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1608_240x128_data_start);
lixianyu 0:d8f4c441e032 137 u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (UC1608) */
lixianyu 0:d8f4c441e032 138 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 139 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
lixianyu 0:d8f4c441e032 140 return 0;
lixianyu 0:d8f4c441e032 141 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 142 }
lixianyu 0:d8f4c441e032 143 break;
lixianyu 0:d8f4c441e032 144 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 145 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 146 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 147 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 148 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2); /* set contrast from, keep gain at 0 */
lixianyu 0:d8f4c441e032 149 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 150 return 1;
lixianyu 0:d8f4c441e032 151 }
lixianyu 0:d8f4c441e032 152 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 153 }
lixianyu 0:d8f4c441e032 154
lixianyu 0:d8f4c441e032 155 uint8_t u8g_dev_uc1608_240x128_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 156 {
lixianyu 0:d8f4c441e032 157 switch(msg)
lixianyu 0:d8f4c441e032 158 {
lixianyu 0:d8f4c441e032 159 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 160 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 161 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1608_240x128_init_seq);
lixianyu 0:d8f4c441e032 162 break;
lixianyu 0:d8f4c441e032 163 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 164 break;
lixianyu 0:d8f4c441e032 165 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 166 {
lixianyu 0:d8f4c441e032 167 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 168
lixianyu 0:d8f4c441e032 169 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1608_240x128_data_start);
lixianyu 0:d8f4c441e032 170 u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
lixianyu 0:d8f4c441e032 171 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 172 u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
lixianyu 0:d8f4c441e032 173 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 174
lixianyu 0:d8f4c441e032 175 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1608_240x128_data_start);
lixianyu 0:d8f4c441e032 176 u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
lixianyu 0:d8f4c441e032 177 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 178 u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
lixianyu 0:d8f4c441e032 179 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 180 }
lixianyu 0:d8f4c441e032 181 break;
lixianyu 0:d8f4c441e032 182 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 183 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 184 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 185 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 186 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
lixianyu 0:d8f4c441e032 187 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 188 return 1;
lixianyu 0:d8f4c441e032 189 }
lixianyu 0:d8f4c441e032 190 return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 191 }
lixianyu 0:d8f4c441e032 192
lixianyu 0:d8f4c441e032 193 U8G_PB_DEV(u8g_dev_uc1608_240x128_sw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_uc1608_240x128_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 194 U8G_PB_DEV(u8g_dev_uc1608_240x128_hw_spi , WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_uc1608_240x128_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 195
lixianyu 0:d8f4c441e032 196 uint8_t u8g_dev_uc1608_240x128_2x_buf[WIDTH*2] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 197 u8g_pb_t u8g_dev_uc1608_240x128_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_uc1608_240x128_2x_buf};
lixianyu 0:d8f4c441e032 198 u8g_dev_t u8g_dev_uc1608_240x128_2x_sw_spi = { u8g_dev_uc1608_240x128_2x_fn, &u8g_dev_uc1608_240x128_2x_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 199 u8g_dev_t u8g_dev_uc1608_240x128_2x_hw_spi = { u8g_dev_uc1608_240x128_2x_fn, &u8g_dev_uc1608_240x128_2x_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 200
lixianyu 0:d8f4c441e032 201