hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_uc1601_c128032.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_uc1601_c128032.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 LCD-AG-C128032R-DIW W/KK E6 PBF from http://www.artronic.pl/o_produkcie.php?id=1343
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 8
lixianyu 0:d8f4c441e032 9 Copyright (c) 2013, olikraus@gmail.com
lixianyu 0:d8f4c441e032 10 All rights reserved.
lixianyu 0:d8f4c441e032 11
lixianyu 0:d8f4c441e032 12 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 13 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 14
lixianyu 0:d8f4c441e032 15 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 16 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 17
lixianyu 0:d8f4c441e032 18 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 19 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 20 materials provided with the distribution.
lixianyu 0:d8f4c441e032 21
lixianyu 0:d8f4c441e032 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 23 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 24 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 25 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 27 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 28 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 31 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 32 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 34 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 35
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 */
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 #include "u8g.h"
lixianyu 0:d8f4c441e032 40
lixianyu 0:d8f4c441e032 41 #define WIDTH 128
lixianyu 0:d8f4c441e032 42 #define HEIGHT 32
lixianyu 0:d8f4c441e032 43 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 44
lixianyu 0:d8f4c441e032 45 /* init sequence */
lixianyu 0:d8f4c441e032 46 static const uint8_t u8g_dev_uc1601_c128032_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 47 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 48 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 49 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 50 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
lixianyu 0:d8f4c441e032 51
lixianyu 0:d8f4c441e032 52 0x0a3, /* 0x0a3: LCD bias 1/7 , 0x0a2: LCD bias 1/9 */
lixianyu 0:d8f4c441e032 53 0x0a0, /* 0x0a0: ADC set to normal, 0x0a1 ADC set to inverted */
lixianyu 0:d8f4c441e032 54 0x0c8, /* common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1 */
lixianyu 0:d8f4c441e032 55 0x0c2, /* 22 May 2013: mirror x */
lixianyu 0:d8f4c441e032 56
lixianyu 0:d8f4c441e032 57 0x040, /* set display start line */
lixianyu 0:d8f4c441e032 58
lixianyu 0:d8f4c441e032 59 0x028 | 0x04, /* power control: turn on voltage converter */
lixianyu 0:d8f4c441e032 60 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 61
lixianyu 0:d8f4c441e032 62 0x028 | 0x06, /* power control: turn on voltage regulator */
lixianyu 0:d8f4c441e032 63 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 64
lixianyu 0:d8f4c441e032 65 0x028 | 0x07, /* power control: turn on voltage follower */
lixianyu 0:d8f4c441e032 66 U8G_ESC_DLY(10), /* delay 10 ms */
lixianyu 0:d8f4c441e032 67
lixianyu 0:d8f4c441e032 68 0x020| 0x06, /* set V0 voltage resistor ratio to 6 */
lixianyu 0:d8f4c441e032 69
lixianyu 0:d8f4c441e032 70 0x0af, /* display on */
lixianyu 0:d8f4c441e032 71
lixianyu 0:d8f4c441e032 72 //0x081, /* set contrast */
lixianyu 0:d8f4c441e032 73 //0x018, /* contrast value*/
lixianyu 0:d8f4c441e032 74
lixianyu 0:d8f4c441e032 75 0x0a6, /* display normal, bit val 0: LCD pixel off. */
lixianyu 0:d8f4c441e032 76
lixianyu 0:d8f4c441e032 77 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 78 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 79 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 80 };
lixianyu 0:d8f4c441e032 81
lixianyu 0:d8f4c441e032 82 static const uint8_t u8g_dev_uc1601_c128032_data_start[] PROGMEM = {
lixianyu 0:d8f4c441e032 83 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 84 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 85 0x010, /* set upper 4 bit of the col adr to 0 */
lixianyu 0:d8f4c441e032 86 0x004, /* set lower 4 bit of the col adr */
lixianyu 0:d8f4c441e032 87 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 88 };
lixianyu 0:d8f4c441e032 89
lixianyu 0:d8f4c441e032 90 static const uint8_t u8g_dev_uc1601_c128032_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 91 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 92 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 93 0x0ac, /* static indicator off */
lixianyu 0:d8f4c441e032 94 0x000, /* indicator register set (not sure if this is required) */
lixianyu 0:d8f4c441e032 95 0x0ae, /* display off */
lixianyu 0:d8f4c441e032 96 0x0a5, /* all points on */
lixianyu 0:d8f4c441e032 97 U8G_ESC_CS(1), /* disable chip */
lixianyu 0:d8f4c441e032 98 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 99 };
lixianyu 0:d8f4c441e032 100
lixianyu 0:d8f4c441e032 101 static const uint8_t u8g_dev_uc1601_c128032_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 102 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 103 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 104 0x0a4, /* all points off */
lixianyu 0:d8f4c441e032 105 0x0af, /* display on */
lixianyu 0:d8f4c441e032 106 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 107 U8G_ESC_CS(1), /* disable chip */
lixianyu 0:d8f4c441e032 108 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 109 };
lixianyu 0:d8f4c441e032 110
lixianyu 0:d8f4c441e032 111
lixianyu 0:d8f4c441e032 112 uint8_t u8g_dev_uc1601_c128032_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 113 {
lixianyu 0:d8f4c441e032 114 switch(msg)
lixianyu 0:d8f4c441e032 115 {
lixianyu 0:d8f4c441e032 116 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 117 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 118 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_init_seq);
lixianyu 0:d8f4c441e032 119 break;
lixianyu 0:d8f4c441e032 120 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 121 break;
lixianyu 0:d8f4c441e032 122 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 123 {
lixianyu 0:d8f4c441e032 124 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 125 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_data_start);
lixianyu 0:d8f4c441e032 126 u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (UC1601) */
lixianyu 0:d8f4c441e032 127 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 128 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
lixianyu 0:d8f4c441e032 129 return 0;
lixianyu 0:d8f4c441e032 130 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 131 }
lixianyu 0:d8f4c441e032 132 break;
lixianyu 0:d8f4c441e032 133 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 134 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 135 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 136 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 137 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
lixianyu 0:d8f4c441e032 138 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 139 return 1;
lixianyu 0:d8f4c441e032 140 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 141 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_sleep_on);
lixianyu 0:d8f4c441e032 142 return 1;
lixianyu 0:d8f4c441e032 143 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 144 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_sleep_off);
lixianyu 0:d8f4c441e032 145 return 1;
lixianyu 0:d8f4c441e032 146 }
lixianyu 0:d8f4c441e032 147 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 148 }
lixianyu 0:d8f4c441e032 149
lixianyu 0:d8f4c441e032 150 uint8_t u8g_dev_uc1601_c128032_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 151 {
lixianyu 0:d8f4c441e032 152 switch(msg)
lixianyu 0:d8f4c441e032 153 {
lixianyu 0:d8f4c441e032 154 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 155 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 156 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_init_seq);
lixianyu 0:d8f4c441e032 157 break;
lixianyu 0:d8f4c441e032 158 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 159 break;
lixianyu 0:d8f4c441e032 160 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 161 {
lixianyu 0:d8f4c441e032 162 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 163
lixianyu 0:d8f4c441e032 164 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_data_start);
lixianyu 0:d8f4c441e032 165 u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (UC1601) */
lixianyu 0:d8f4c441e032 166 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 167 u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
lixianyu 0:d8f4c441e032 168 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 169
lixianyu 0:d8f4c441e032 170 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_data_start);
lixianyu 0:d8f4c441e032 171 u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (UC1601) */
lixianyu 0:d8f4c441e032 172 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 173 u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
lixianyu 0:d8f4c441e032 174 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 175 }
lixianyu 0:d8f4c441e032 176 break;
lixianyu 0:d8f4c441e032 177 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 178 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 179 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 180 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 181 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
lixianyu 0:d8f4c441e032 182 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 183 return 1;
lixianyu 0:d8f4c441e032 184 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 185 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_sleep_on);
lixianyu 0:d8f4c441e032 186 return 1;
lixianyu 0:d8f4c441e032 187 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 188 u8g_WriteEscSeqP(u8g, dev, u8g_dev_uc1601_c128032_sleep_off);
lixianyu 0:d8f4c441e032 189 return 1;
lixianyu 0:d8f4c441e032 190 }
lixianyu 0:d8f4c441e032 191 return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 192 }
lixianyu 0:d8f4c441e032 193
lixianyu 0:d8f4c441e032 194 U8G_PB_DEV(u8g_dev_uc1601_c128032_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_uc1601_c128032_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 195 U8G_PB_DEV(u8g_dev_uc1601_c128032_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_uc1601_c128032_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 196
lixianyu 0:d8f4c441e032 197 uint8_t u8g_dev_uc1601_c128032_2x_buf[WIDTH*2] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 198 u8g_pb_t u8g_dev_uc1601_c128032_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_uc1601_c128032_2x_buf};
lixianyu 0:d8f4c441e032 199 u8g_dev_t u8g_dev_uc1601_c128032_2x_sw_spi = { u8g_dev_uc1601_c128032_2x_fn, &u8g_dev_uc1601_c128032_2x_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 200 u8g_dev_t u8g_dev_uc1601_c128032_2x_hw_spi = { u8g_dev_uc1601_c128032_2x_fn, &u8g_dev_uc1601_c128032_2x_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 201
lixianyu 0:d8f4c441e032 202