hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_st7687_c144mvgd.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_st7687_c144mvgd.c (1.44" TFT)
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Status: Started, but not finished
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 8
lixianyu 0:d8f4c441e032 9 Copyright (c) 2012, olikraus@gmail.com
lixianyu 0:d8f4c441e032 10 All rights reserved.
lixianyu 0:d8f4c441e032 11
lixianyu 0:d8f4c441e032 12 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 13 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 14
lixianyu 0:d8f4c441e032 15 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 16 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 17
lixianyu 0:d8f4c441e032 18 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 19 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 20 materials provided with the distribution.
lixianyu 0:d8f4c441e032 21
lixianyu 0:d8f4c441e032 22 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 23 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 24 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 25 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 26 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 27 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 28 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 30 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 31 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 32 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 34 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 35
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 */
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 #include "u8g.h"
lixianyu 0:d8f4c441e032 40 #if defined(ARDUINO)
lixianyu 0:d8f4c441e032 41 #define WIDTH 128
lixianyu 0:d8f4c441e032 42 #define HEIGHT 128
lixianyu 0:d8f4c441e032 43 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 44
lixianyu 0:d8f4c441e032 45
lixianyu 0:d8f4c441e032 46 #ifdef FIRST_VERSION
lixianyu 0:d8f4c441e032 47 /*
lixianyu 0:d8f4c441e032 48 see also: read.pudn.com/downloads115/sourcecode/app/484503/LCM_Display.c__.htm
lixianyu 0:d8f4c441e032 49 http://en.pudn.com/downloads115/sourcecode/app/detail484503_en.html
lixianyu 0:d8f4c441e032 50 */
lixianyu 0:d8f4c441e032 51
lixianyu 0:d8f4c441e032 52 static const uint8_t u8g_dev_st7687_c144mvgd_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 53 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 54 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 55 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 56 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
lixianyu 0:d8f4c441e032 57
lixianyu 0:d8f4c441e032 58 0x001, /* A0=0, SW reset */
lixianyu 0:d8f4c441e032 59 U8G_ESC_DLY(200), /* delay 200 ms */
lixianyu 0:d8f4c441e032 60
lixianyu 0:d8f4c441e032 61 0x0d7, /* EEPROM data auto re-load control */
lixianyu 0:d8f4c441e032 62 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 63 0x09f, /* ARD = 1 */
lixianyu 0:d8f4c441e032 64 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 65 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 66
lixianyu 0:d8f4c441e032 67 0x0e0, /* EEPROM control in */
lixianyu 0:d8f4c441e032 68 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 69 0x000, /* */
lixianyu 0:d8f4c441e032 70 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 71 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 72
lixianyu 0:d8f4c441e032 73 #ifdef NOT_REQUIRED
lixianyu 0:d8f4c441e032 74 0x0fa, /* EEPROM function selection 8.1.66 */
lixianyu 0:d8f4c441e032 75 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 76 0x000, /* */
lixianyu 0:d8f4c441e032 77 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 78 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 79 #endif
lixianyu 0:d8f4c441e032 80
lixianyu 0:d8f4c441e032 81 0x0e3, /* Read from EEPROM, 8.1.55 */
lixianyu 0:d8f4c441e032 82 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 83
lixianyu 0:d8f4c441e032 84 0x0e1, /* EEPROM control out, 8.1.53 */
lixianyu 0:d8f4c441e032 85 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 86
lixianyu 0:d8f4c441e032 87 //0x028, /* display off */
lixianyu 0:d8f4c441e032 88 0x011, /* Sleep out & booster on */
lixianyu 0:d8f4c441e032 89 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 90
lixianyu 0:d8f4c441e032 91 0x0c0, /* Vop setting, 8.1.42 */
lixianyu 0:d8f4c441e032 92 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 93 0x000, /* */
lixianyu 0:d8f4c441e032 94 0x001, /* 3.6 + 256*0.04 = 13.84 Volt */
lixianyu 0:d8f4c441e032 95 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 96 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 97
lixianyu 0:d8f4c441e032 98 0x0c3, /* Bias selection, 8.1.45 */
lixianyu 0:d8f4c441e032 99 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 100 0x003,
lixianyu 0:d8f4c441e032 101 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 102
lixianyu 0:d8f4c441e032 103 0x0c4, /* Booster setting 8.1.46 */
lixianyu 0:d8f4c441e032 104 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 105 0x007,
lixianyu 0:d8f4c441e032 106 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 107
lixianyu 0:d8f4c441e032 108 0x0c5, /* ??? */
lixianyu 0:d8f4c441e032 109 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 110 0x001,
lixianyu 0:d8f4c441e032 111 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 112
lixianyu 0:d8f4c441e032 113 0x0cb, /* FV3 with Booster x2 control, 8.1.47 */
lixianyu 0:d8f4c441e032 114 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 115 0x001,
lixianyu 0:d8f4c441e032 116 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 117
lixianyu 0:d8f4c441e032 118 0x036, /* Memory data access control, 8.1.28 */
lixianyu 0:d8f4c441e032 119 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 120 0x080,
lixianyu 0:d8f4c441e032 121 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 122
lixianyu 0:d8f4c441e032 123 0x0b5, /* N-line control, 8.1.37 */
lixianyu 0:d8f4c441e032 124 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 125 0x089,
lixianyu 0:d8f4c441e032 126 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 127
lixianyu 0:d8f4c441e032 128
lixianyu 0:d8f4c441e032 129 0x0d0, /* Analog circuit setting, 8.1.49 */
lixianyu 0:d8f4c441e032 130 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 131 0x01d,
lixianyu 0:d8f4c441e032 132 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 133
lixianyu 0:d8f4c441e032 134 0x0b7, /* Com/Seg Scan Direction, 8.1.38 */
lixianyu 0:d8f4c441e032 135 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 136 0x040,
lixianyu 0:d8f4c441e032 137 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 138
lixianyu 0:d8f4c441e032 139 0x025, /* Write contrast, 8.1.17 */
lixianyu 0:d8f4c441e032 140 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 141 0x03f,
lixianyu 0:d8f4c441e032 142 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 143
lixianyu 0:d8f4c441e032 144 0x03a, /* Interface pixel format, 8.1.32 */
lixianyu 0:d8f4c441e032 145 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 146 0x004, /* 3: 12 bit per pixel Type A, 4: 12 bit Type B, 5: 16bit per pixel */
lixianyu 0:d8f4c441e032 147 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 148
lixianyu 0:d8f4c441e032 149 0x0b0, /* Display Duty setting, 8.1.34 */
lixianyu 0:d8f4c441e032 150 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 151 0x07f,
lixianyu 0:d8f4c441e032 152 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 153
lixianyu 0:d8f4c441e032 154 0x0f0, /* Frame Freq. in Temp range A,B,C and D, 8.1.59 */
lixianyu 0:d8f4c441e032 155 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 156 0x007,
lixianyu 0:d8f4c441e032 157 0x00c,
lixianyu 0:d8f4c441e032 158 0x00c,
lixianyu 0:d8f4c441e032 159 0x015,
lixianyu 0:d8f4c441e032 160 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 161
lixianyu 0:d8f4c441e032 162 0x0f9, /* Frame RGB Value, 8.1.65 */
lixianyu 0:d8f4c441e032 163 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 164 0x000,
lixianyu 0:d8f4c441e032 165 0x005,
lixianyu 0:d8f4c441e032 166 0x008,
lixianyu 0:d8f4c441e032 167 0x00a,
lixianyu 0:d8f4c441e032 168 0x00c,
lixianyu 0:d8f4c441e032 169 0x00e,
lixianyu 0:d8f4c441e032 170 0x010,
lixianyu 0:d8f4c441e032 171 0x011,
lixianyu 0:d8f4c441e032 172 0x012,
lixianyu 0:d8f4c441e032 173 0x013,
lixianyu 0:d8f4c441e032 174 0x014,
lixianyu 0:d8f4c441e032 175 0x015,
lixianyu 0:d8f4c441e032 176 0x016,
lixianyu 0:d8f4c441e032 177 0x018,
lixianyu 0:d8f4c441e032 178 0x01a,
lixianyu 0:d8f4c441e032 179 0x01b,
lixianyu 0:d8f4c441e032 180 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 181
lixianyu 0:d8f4c441e032 182 0x0f9, /* Frame RGB Value, 8.1.65 */
lixianyu 0:d8f4c441e032 183 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 184 0x000,
lixianyu 0:d8f4c441e032 185 0x000,
lixianyu 0:d8f4c441e032 186 0x000,
lixianyu 0:d8f4c441e032 187 0x000,
lixianyu 0:d8f4c441e032 188 0x033,
lixianyu 0:d8f4c441e032 189 0x055,
lixianyu 0:d8f4c441e032 190 0x055,
lixianyu 0:d8f4c441e032 191 0x055,
lixianyu 0:d8f4c441e032 192 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 193
lixianyu 0:d8f4c441e032 194 0x029, /* display on */
lixianyu 0:d8f4c441e032 195
lixianyu 0:d8f4c441e032 196 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 197 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 198
lixianyu 0:d8f4c441e032 199 };
lixianyu 0:d8f4c441e032 200
lixianyu 0:d8f4c441e032 201 #else
lixianyu 0:d8f4c441e032 202
lixianyu 0:d8f4c441e032 203 /*
lixianyu 0:d8f4c441e032 204 http://www.waitingforfriday.com/images/e/e3/FTM144D01N_test.zip
lixianyu 0:d8f4c441e032 205 */
lixianyu 0:d8f4c441e032 206
lixianyu 0:d8f4c441e032 207 static const uint8_t u8g_dev_st7687_c144mvgd_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 208 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 209 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 210 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 211 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
lixianyu 0:d8f4c441e032 212
lixianyu 0:d8f4c441e032 213 0x011, /* Sleep out & booster on */
lixianyu 0:d8f4c441e032 214 U8G_ESC_DLY(5), /* delay 5 ms */
lixianyu 0:d8f4c441e032 215
lixianyu 0:d8f4c441e032 216 0x03a, /* Interface pixel format, 8.1.32 */
lixianyu 0:d8f4c441e032 217 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 218 0x004, /* 3: 12 bit per pixel Type A, 4: 12 bit Type B, 5: 16bit per pixel */
lixianyu 0:d8f4c441e032 219 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 220
lixianyu 0:d8f4c441e032 221
lixianyu 0:d8f4c441e032 222 0x026, /* SET_GAMMA_CURVE */
lixianyu 0:d8f4c441e032 223 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 224 0x004,
lixianyu 0:d8f4c441e032 225 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 226
lixianyu 0:d8f4c441e032 227 0x0f2, /* GAM_R_SEL */
lixianyu 0:d8f4c441e032 228 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 229 0x001, /* enable gamma adj */
lixianyu 0:d8f4c441e032 230 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 231
lixianyu 0:d8f4c441e032 232
lixianyu 0:d8f4c441e032 233 0x0e0, /* POSITIVE_GAMMA_CORRECT */
lixianyu 0:d8f4c441e032 234 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 235 0x3f,
lixianyu 0:d8f4c441e032 236 0x25,
lixianyu 0:d8f4c441e032 237 0x1c,
lixianyu 0:d8f4c441e032 238 0x1e,
lixianyu 0:d8f4c441e032 239 0x20,
lixianyu 0:d8f4c441e032 240 0x12,
lixianyu 0:d8f4c441e032 241 0x2a,
lixianyu 0:d8f4c441e032 242 0x90,
lixianyu 0:d8f4c441e032 243 0x24,
lixianyu 0:d8f4c441e032 244 0x11,
lixianyu 0:d8f4c441e032 245 0x00,
lixianyu 0:d8f4c441e032 246 0x00,
lixianyu 0:d8f4c441e032 247 0x00,
lixianyu 0:d8f4c441e032 248 0x00,
lixianyu 0:d8f4c441e032 249 0x00,
lixianyu 0:d8f4c441e032 250 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 251
lixianyu 0:d8f4c441e032 252 0x0e1, /* NEGATIVE_GAMMA_CORRECT */
lixianyu 0:d8f4c441e032 253 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 254 0x20,
lixianyu 0:d8f4c441e032 255 0x20,
lixianyu 0:d8f4c441e032 256 0x20,
lixianyu 0:d8f4c441e032 257 0x20,
lixianyu 0:d8f4c441e032 258 0x05,
lixianyu 0:d8f4c441e032 259 0x00,
lixianyu 0:d8f4c441e032 260 0x15,
lixianyu 0:d8f4c441e032 261 0xa7,
lixianyu 0:d8f4c441e032 262 0x3d,
lixianyu 0:d8f4c441e032 263 0x18,
lixianyu 0:d8f4c441e032 264 0x25,
lixianyu 0:d8f4c441e032 265 0x2a,
lixianyu 0:d8f4c441e032 266 0x2b,
lixianyu 0:d8f4c441e032 267 0x2b,
lixianyu 0:d8f4c441e032 268 0x3a,
lixianyu 0:d8f4c441e032 269 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 270
lixianyu 0:d8f4c441e032 271 0x0b1, /* FRAME_RATE_CONTROL1 */
lixianyu 0:d8f4c441e032 272 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 273 0x008, /* DIVA = 8 */
lixianyu 0:d8f4c441e032 274 0x008, /* VPA = 8 */
lixianyu 0:d8f4c441e032 275 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 276
lixianyu 0:d8f4c441e032 277
lixianyu 0:d8f4c441e032 278 0x0b4, /* DISPLAY_INVERSION */
lixianyu 0:d8f4c441e032 279 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 280 0x007, /* NLA = 1, NLB = 1, NLC = 1 (all on Frame Inversion) */
lixianyu 0:d8f4c441e032 281 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 282
lixianyu 0:d8f4c441e032 283 0x0c0, /* POWER_CONTROL1 */
lixianyu 0:d8f4c441e032 284 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 285 0x00a, /* VRH = 10: GVDD = 4.30 */
lixianyu 0:d8f4c441e032 286 0x002, /* VC = 2: VCI1 = 2.65 */
lixianyu 0:d8f4c441e032 287 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 288
lixianyu 0:d8f4c441e032 289 0x0c1, /* POWER_CONTROL2 */
lixianyu 0:d8f4c441e032 290 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 291 0x002, /* BT = 2: AVDD = 2xVCI1, VCL = -1xVCI1, VGH = 5xVCI1, VGL = -2xVCI1 */
lixianyu 0:d8f4c441e032 292 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 293
lixianyu 0:d8f4c441e032 294 0x0c5, /* VCOM_CONTROL1 */
lixianyu 0:d8f4c441e032 295 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 296 0x050, /* VMH = 80: VCOMH voltage = 4.5 */
lixianyu 0:d8f4c441e032 297 0x05b, /* VML = 91: VCOML voltage = -0.225 */
lixianyu 0:d8f4c441e032 298 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 299
lixianyu 0:d8f4c441e032 300 0x0c7, /* VCOM_OFFSET_CONTROL */
lixianyu 0:d8f4c441e032 301 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 302 0x040, /* nVM = 0, VMF = 64: VCOMH output = VMH, VCOML output = VML */
lixianyu 0:d8f4c441e032 303 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 304
lixianyu 0:d8f4c441e032 305 0x02a, /* SET_COLUMN_ADDRESS */
lixianyu 0:d8f4c441e032 306 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 307 0x000, /* */
lixianyu 0:d8f4c441e032 308 0x000, /* */
lixianyu 0:d8f4c441e032 309 0x000, /* */
lixianyu 0:d8f4c441e032 310 0x07f, /* */
lixianyu 0:d8f4c441e032 311 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 312
lixianyu 0:d8f4c441e032 313 0x02b, /* SET_PAGE_ADDRESS */
lixianyu 0:d8f4c441e032 314 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 315 0x000, /* */
lixianyu 0:d8f4c441e032 316 0x000, /* */
lixianyu 0:d8f4c441e032 317 0x000, /* */
lixianyu 0:d8f4c441e032 318 0x07f, /* */
lixianyu 0:d8f4c441e032 319 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 320
lixianyu 0:d8f4c441e032 321 0x036, /* SET_ADDRESS_MODE */
lixianyu 0:d8f4c441e032 322 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 323 0x000, /* Select display orientation */
lixianyu 0:d8f4c441e032 324 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 325
lixianyu 0:d8f4c441e032 326
lixianyu 0:d8f4c441e032 327 0x029, /* display on */
lixianyu 0:d8f4c441e032 328
lixianyu 0:d8f4c441e032 329 0x02c, /* write start */
lixianyu 0:d8f4c441e032 330
lixianyu 0:d8f4c441e032 331 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 332 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 333
lixianyu 0:d8f4c441e032 334 };
lixianyu 0:d8f4c441e032 335
lixianyu 0:d8f4c441e032 336 #endif
lixianyu 0:d8f4c441e032 337
lixianyu 0:d8f4c441e032 338
lixianyu 0:d8f4c441e032 339
lixianyu 0:d8f4c441e032 340
lixianyu 0:d8f4c441e032 341 /* calculate bytes for Type B 4096 color display */
lixianyu 0:d8f4c441e032 342 static uint8_t get_byte_1(uint8_t v)
lixianyu 0:d8f4c441e032 343 {
lixianyu 0:d8f4c441e032 344 v >>= 4;
lixianyu 0:d8f4c441e032 345 v &= 0x0e;
lixianyu 0:d8f4c441e032 346 return v;
lixianyu 0:d8f4c441e032 347 }
lixianyu 0:d8f4c441e032 348
lixianyu 0:d8f4c441e032 349 static uint8_t get_byte_2(uint8_t v)
lixianyu 0:d8f4c441e032 350 {
lixianyu 0:d8f4c441e032 351 uint8_t w;
lixianyu 0:d8f4c441e032 352 w = v;
lixianyu 0:d8f4c441e032 353 w &= 3;
lixianyu 0:d8f4c441e032 354 w = (w<<2) | w;
lixianyu 0:d8f4c441e032 355 v <<= 3;
lixianyu 0:d8f4c441e032 356 v &= 0x0e0;
lixianyu 0:d8f4c441e032 357 w |= v;
lixianyu 0:d8f4c441e032 358 return w;
lixianyu 0:d8f4c441e032 359 }
lixianyu 0:d8f4c441e032 360
lixianyu 0:d8f4c441e032 361 uint8_t u8g_dev_st7687_c144mvgd_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 362 {
lixianyu 0:d8f4c441e032 363 switch(msg)
lixianyu 0:d8f4c441e032 364 {
lixianyu 0:d8f4c441e032 365 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 366 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
lixianyu 0:d8f4c441e032 367 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7687_c144mvgd_init_seq);
lixianyu 0:d8f4c441e032 368 break;
lixianyu 0:d8f4c441e032 369 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 370 break;
lixianyu 0:d8f4c441e032 371 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 372 {
lixianyu 0:d8f4c441e032 373 uint8_t y, i, j;
lixianyu 0:d8f4c441e032 374 uint8_t *ptr;
lixianyu 0:d8f4c441e032 375 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 376
lixianyu 0:d8f4c441e032 377 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
lixianyu 0:d8f4c441e032 378 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 379 y = pb->p.page_y0;
lixianyu 0:d8f4c441e032 380 ptr = pb->buf;
lixianyu 0:d8f4c441e032 381
lixianyu 0:d8f4c441e032 382 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
lixianyu 0:d8f4c441e032 383 u8g_WriteByte(u8g, dev, 0x02a ); /* Column address set 8.1.20 */
lixianyu 0:d8f4c441e032 384 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 385 u8g_WriteByte(u8g, dev, 0x000 ); /* x0 */
lixianyu 0:d8f4c441e032 386 u8g_WriteByte(u8g, dev, WIDTH-1 ); /* x1 */
lixianyu 0:d8f4c441e032 387 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
lixianyu 0:d8f4c441e032 388 u8g_WriteByte(u8g, dev, 0x02b ); /* Row address set 8.1.21 */
lixianyu 0:d8f4c441e032 389 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 390 u8g_WriteByte(u8g, dev, y ); /* y0 */
lixianyu 0:d8f4c441e032 391 u8g_WriteByte(u8g, dev, y+PAGE_HEIGHT-1 ); /* y1 */
lixianyu 0:d8f4c441e032 392 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
lixianyu 0:d8f4c441e032 393 u8g_WriteByte(u8g, dev, 0x02c ); /* Memory write 8.1.22 */
lixianyu 0:d8f4c441e032 394 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 395
lixianyu 0:d8f4c441e032 396 for( i = 0; i < PAGE_HEIGHT; i ++ )
lixianyu 0:d8f4c441e032 397 {
lixianyu 0:d8f4c441e032 398
lixianyu 0:d8f4c441e032 399 for( j = 0; j < WIDTH; j ++ )
lixianyu 0:d8f4c441e032 400 {
lixianyu 0:d8f4c441e032 401 u8g_WriteByte(u8g, dev, get_byte_1(*ptr) );
lixianyu 0:d8f4c441e032 402 u8g_WriteByte(u8g, dev, get_byte_2(*ptr) );
lixianyu 0:d8f4c441e032 403 ptr++;
lixianyu 0:d8f4c441e032 404 }
lixianyu 0:d8f4c441e032 405 }
lixianyu 0:d8f4c441e032 406 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
lixianyu 0:d8f4c441e032 407 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 408 }
lixianyu 0:d8f4c441e032 409 break;
lixianyu 0:d8f4c441e032 410 }
lixianyu 0:d8f4c441e032 411 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 412 }
lixianyu 0:d8f4c441e032 413
lixianyu 0:d8f4c441e032 414
lixianyu 0:d8f4c441e032 415 uint8_t u8g_st7687_c144mvgd_8h8_buf[WIDTH*8] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 416 u8g_pb_t u8g_st7687_c144mvgd_8h8_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_st7687_c144mvgd_8h8_buf};
lixianyu 0:d8f4c441e032 417
lixianyu 0:d8f4c441e032 418 u8g_dev_t u8g_dev_st7687_c144mvgd_sw_spi = { u8g_dev_st7687_c144mvgd_fn, &u8g_st7687_c144mvgd_8h8_pb, u8g_com_arduino_sw_spi_fn };
lixianyu 0:d8f4c441e032 419
lixianyu 0:d8f4c441e032 420 u8g_dev_t u8g_dev_st7687_c144mvgd_8bit = { u8g_dev_st7687_c144mvgd_fn, &u8g_st7687_c144mvgd_8h8_pb, U8G_COM_PARALLEL };
lixianyu 0:d8f4c441e032 421
lixianyu 0:d8f4c441e032 422 #endif /* ARDUINO */