hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_st7565_64128n.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_st7565_64128n.c (Displaytech)
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Copyright (c) 2011, olikraus@gmail.com
lixianyu 0:d8f4c441e032 8 All rights reserved.
lixianyu 0:d8f4c441e032 9
lixianyu 0:d8f4c441e032 10 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 11 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 14 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 17 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 18 materials provided with the distribution.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 33
lixianyu 0:d8f4c441e032 34
lixianyu 0:d8f4c441e032 35 */
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 #include "u8g.h"
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39 #define WIDTH 128
lixianyu 0:d8f4c441e032 40 #define HEIGHT 64
lixianyu 0:d8f4c441e032 41 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 42
lixianyu 0:d8f4c441e032 43 /* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
lixianyu 0:d8f4c441e032 44 static const uint8_t u8g_dev_st7565_64128n_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 45 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 46 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 47 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 48 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
lixianyu 0:d8f4c441e032 49
lixianyu 0:d8f4c441e032 50 0x0A2, /* 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */
lixianyu 0:d8f4c441e032 51 0x0A0, /* Normal ADC Select (according to Displaytech 64128N datasheet) */
lixianyu 0:d8f4c441e032 52
lixianyu 0:d8f4c441e032 53 0x0c8, /* common output mode: set scan direction normal operation/SHL Select, 0x0c0 --> SHL = 0, normal, 0x0c8 --> SHL = 1 */
lixianyu 0:d8f4c441e032 54 0x040, /* Display start line for Displaytech 64128N */
lixianyu 0:d8f4c441e032 55
lixianyu 0:d8f4c441e032 56 0x028 | 0x04, /* power control: turn on voltage converter */
lixianyu 0:d8f4c441e032 57 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 58
lixianyu 0:d8f4c441e032 59 0x028 | 0x06, /* power control: turn on voltage regulator */
lixianyu 0:d8f4c441e032 60 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 61
lixianyu 0:d8f4c441e032 62 0x028 | 0x07, /* power control: turn on voltage follower */
lixianyu 0:d8f4c441e032 63 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 64
lixianyu 0:d8f4c441e032 65 0x010, /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */
lixianyu 0:d8f4c441e032 66
lixianyu 0:d8f4c441e032 67 0x0a6, /* display normal, bit val 0: LCD pixel off. */
lixianyu 0:d8f4c441e032 68
lixianyu 0:d8f4c441e032 69 0x081, /* set contrast */
lixianyu 0:d8f4c441e032 70 0x01e, /* Contrast value. Setting for controlling brightness of Displaytech 64128N */
lixianyu 0:d8f4c441e032 71
lixianyu 0:d8f4c441e032 72
lixianyu 0:d8f4c441e032 73 0x0af, /* display on */
lixianyu 0:d8f4c441e032 74
lixianyu 0:d8f4c441e032 75 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 76 0x0a5, /* display all points, ST7565 */
lixianyu 0:d8f4c441e032 77 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 78 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 79 0x0a4, /* normal display */
lixianyu 0:d8f4c441e032 80 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 81 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 82 };
lixianyu 0:d8f4c441e032 83
lixianyu 0:d8f4c441e032 84 static const uint8_t u8g_dev_st7565_64128n_data_start[] PROGMEM = {
lixianyu 0:d8f4c441e032 85 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 86 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 87 0x010, /* set upper 4 bit of the col adr to 0x10 */
lixianyu 0:d8f4c441e032 88 0x000, /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
lixianyu 0:d8f4c441e032 89 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 90 };
lixianyu 0:d8f4c441e032 91
lixianyu 0:d8f4c441e032 92 static const uint8_t u8g_dev_st7565_64128n_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 93 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 94 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 95 0x0ac, /* static indicator off */
lixianyu 0:d8f4c441e032 96 0x000, /* indicator register set (not sure if this is required) */
lixianyu 0:d8f4c441e032 97 0x0ae, /* display off */
lixianyu 0:d8f4c441e032 98 0x0a5, /* all points on */
lixianyu 0:d8f4c441e032 99 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 100 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 101 };
lixianyu 0:d8f4c441e032 102
lixianyu 0:d8f4c441e032 103 static const uint8_t u8g_dev_st7565_64128n_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 104 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 105 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 106 0x0a4, /* all points off */
lixianyu 0:d8f4c441e032 107 0x0af, /* display on */
lixianyu 0:d8f4c441e032 108 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 109 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 110 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 111 };
lixianyu 0:d8f4c441e032 112
lixianyu 0:d8f4c441e032 113 uint8_t u8g_dev_st7565_64128n_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 114 {
lixianyu 0:d8f4c441e032 115 switch(msg)
lixianyu 0:d8f4c441e032 116 {
lixianyu 0:d8f4c441e032 117 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 118 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
lixianyu 0:d8f4c441e032 119 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_init_seq);
lixianyu 0:d8f4c441e032 120 break;
lixianyu 0:d8f4c441e032 121 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 122 break;
lixianyu 0:d8f4c441e032 123 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 124 {
lixianyu 0:d8f4c441e032 125 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 126 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);
lixianyu 0:d8f4c441e032 127 u8g_WriteByte(u8g, dev, 0x0b0 | pb->p.page); /* select current page (ST7565R) */
lixianyu 0:d8f4c441e032 128 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 129 if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
lixianyu 0:d8f4c441e032 130 return 0;
lixianyu 0:d8f4c441e032 131 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 132 }
lixianyu 0:d8f4c441e032 133 break;
lixianyu 0:d8f4c441e032 134 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 135 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 136 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 137 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 138 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
lixianyu 0:d8f4c441e032 139 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 140 return 1;
lixianyu 0:d8f4c441e032 141 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 142 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_on);
lixianyu 0:d8f4c441e032 143 return 1;
lixianyu 0:d8f4c441e032 144 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 145 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_off);
lixianyu 0:d8f4c441e032 146 return 1;
lixianyu 0:d8f4c441e032 147 }
lixianyu 0:d8f4c441e032 148 return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 149 }
lixianyu 0:d8f4c441e032 150
lixianyu 0:d8f4c441e032 151 uint8_t u8g_dev_st7565_64128n_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 152 {
lixianyu 0:d8f4c441e032 153 switch(msg)
lixianyu 0:d8f4c441e032 154 {
lixianyu 0:d8f4c441e032 155 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 156 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
lixianyu 0:d8f4c441e032 157 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_init_seq);
lixianyu 0:d8f4c441e032 158 break;
lixianyu 0:d8f4c441e032 159 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 160 break;
lixianyu 0:d8f4c441e032 161 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 162 {
lixianyu 0:d8f4c441e032 163 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 164
lixianyu 0:d8f4c441e032 165 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);
lixianyu 0:d8f4c441e032 166 u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page)); /* select current page (ST7565R) */
lixianyu 0:d8f4c441e032 167 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 168 u8g_WriteSequence(u8g, dev, pb->width, pb->buf);
lixianyu 0:d8f4c441e032 169 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 170
lixianyu 0:d8f4c441e032 171 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_data_start);
lixianyu 0:d8f4c441e032 172 u8g_WriteByte(u8g, dev, 0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
lixianyu 0:d8f4c441e032 173 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 174 u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
lixianyu 0:d8f4c441e032 175 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 176 }
lixianyu 0:d8f4c441e032 177 break;
lixianyu 0:d8f4c441e032 178 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 179 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 180 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 181 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 182 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 2);
lixianyu 0:d8f4c441e032 183 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 184 return 1;
lixianyu 0:d8f4c441e032 185 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 186 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_on);
lixianyu 0:d8f4c441e032 187 return 1;
lixianyu 0:d8f4c441e032 188 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 189 u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_sleep_off);
lixianyu 0:d8f4c441e032 190 return 1;
lixianyu 0:d8f4c441e032 191 }
lixianyu 0:d8f4c441e032 192 return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 193 }
lixianyu 0:d8f4c441e032 194
lixianyu 0:d8f4c441e032 195 U8G_PB_DEV(u8g_dev_st7565_64128n_sw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 196 U8G_PB_DEV(u8g_dev_st7565_64128n_hw_spi, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 197 U8G_PB_DEV(u8g_dev_st7565_64128n_parallel, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_st7565_64128n_fn, U8G_COM_PARALLEL);
lixianyu 0:d8f4c441e032 198
lixianyu 0:d8f4c441e032 199 uint8_t u8g_dev_st7565_64128n_2x_buf[WIDTH*2] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 200 u8g_pb_t u8g_dev_st7565_64128n_2x_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7565_64128n_2x_buf};
lixianyu 0:d8f4c441e032 201 u8g_dev_t u8g_dev_st7565_64128n_2x_sw_spi = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 202 u8g_dev_t u8g_dev_st7565_64128n_2x_hw_spi = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 203 u8g_dev_t u8g_dev_st7565_64128n_2x_hw_parallel = { u8g_dev_st7565_64128n_2x_fn, &u8g_dev_st7565_64128n_2x_pb, U8G_COM_PARALLEL };
lixianyu 0:d8f4c441e032 204