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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1353_160x128.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2 u8g_dev_ssd1353_160x128.c
lixianyu 0:d8f4c441e032 3
lixianyu 0:d8f4c441e032 4 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 5
lixianyu 0:d8f4c441e032 6 Copyright (c) 2015, hugodan3@googlemail.com
lixianyu 0:d8f4c441e032 7 Copyright (c) 2013, jamjardavies@gmail.com
lixianyu 0:d8f4c441e032 8 Copyright (c) 2013, olikraus@gmail.com
lixianyu 0:d8f4c441e032 9 All rights reserved.
lixianyu 0:d8f4c441e032 10
lixianyu 0:d8f4c441e032 11 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 12 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 13
lixianyu 0:d8f4c441e032 14 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 15 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 16
lixianyu 0:d8f4c441e032 17 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 18 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 19 materials provided with the distribution.
lixianyu 0:d8f4c441e032 20
lixianyu 0:d8f4c441e032 21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 22 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 23 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 24 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 25 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 26 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 27 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 30 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 31 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 33 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 34
lixianyu 0:d8f4c441e032 35 History:
lixianyu 0:d8f4c441e032 36 Initial version 8 Mar 2015 hugodan3@googlemail.com. This version has
lixianyu 0:d8f4c441e032 37 been derived from the ssd1351 driver by jamjarda. It has
lixianyu 0:d8f4c441e032 38 been improved by in-lining time critical functions.
lixianyu 0:d8f4c441e032 39
lixianyu 0:d8f4c441e032 40
lixianyu 0:d8f4c441e032 41
lixianyu 0:d8f4c441e032 42 */
lixianyu 0:d8f4c441e032 43
lixianyu 0:d8f4c441e032 44 #include "u8g.h"
lixianyu 0:d8f4c441e032 45
lixianyu 0:d8f4c441e032 46 #define WIDTH 160
lixianyu 0:d8f4c441e032 47 #define HEIGHT 128
lixianyu 0:d8f4c441e032 48 #define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 49
lixianyu 0:d8f4c441e032 50 #define USE_GREY_TABLE 0
lixianyu 0:d8f4c441e032 51
lixianyu 0:d8f4c441e032 52 static const uint8_t u8g_dev_ssd1353_160x128_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 53 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 54 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 55 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 56 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 57 U8G_ESC_DLY(50),
lixianyu 0:d8f4c441e032 58 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 59
lixianyu 0:d8f4c441e032 60 0xFD, /* Command unlock */
lixianyu 0:d8f4c441e032 61 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 62 0x12,
lixianyu 0:d8f4c441e032 63
lixianyu 0:d8f4c441e032 64 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 65 0xAE, /* Set Display Off */
lixianyu 0:d8f4c441e032 66
lixianyu 0:d8f4c441e032 67 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 68 0xA8,
lixianyu 0:d8f4c441e032 69 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 70 0x7F, /* Set Multiplex Ratio */
lixianyu 0:d8f4c441e032 71
lixianyu 0:d8f4c441e032 72 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 73 0xA0,
lixianyu 0:d8f4c441e032 74 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 75 0xB4, /* Set remapping */
lixianyu 0:d8f4c441e032 76
lixianyu 0:d8f4c441e032 77 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 78 0xA1,
lixianyu 0:d8f4c441e032 79 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 80 0x00, /* Set Display Start Line */
lixianyu 0:d8f4c441e032 81
lixianyu 0:d8f4c441e032 82 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 83 0xA2,
lixianyu 0:d8f4c441e032 84 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 85 0x00, /* Set Display Offset */
lixianyu 0:d8f4c441e032 86
lixianyu 0:d8f4c441e032 87 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 88 0xB1,
lixianyu 0:d8f4c441e032 89 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 90 0x32, /* Set Phase Length */
lixianyu 0:d8f4c441e032 91
lixianyu 0:d8f4c441e032 92 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 93 0xB4,
lixianyu 0:d8f4c441e032 94 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 95 0x04, /* Set Second Precharge Period */
lixianyu 0:d8f4c441e032 96
lixianyu 0:d8f4c441e032 97 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 98 0xA4, /* Set Display Mode ON */
lixianyu 0:d8f4c441e032 99
lixianyu 0:d8f4c441e032 100 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 101 0xB3,
lixianyu 0:d8f4c441e032 102 U8G_ESC_ADR(1), /* frame rate */
lixianyu 0:d8f4c441e032 103 0x40,
lixianyu 0:d8f4c441e032 104
lixianyu 0:d8f4c441e032 105 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 106 0xBB,
lixianyu 0:d8f4c441e032 107 U8G_ESC_ADR(1), /* pre-charge level */
lixianyu 0:d8f4c441e032 108 0x08,
lixianyu 0:d8f4c441e032 109
lixianyu 0:d8f4c441e032 110 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 111 0xBE,
lixianyu 0:d8f4c441e032 112 U8G_ESC_ADR(1), /* vcomh */
lixianyu 0:d8f4c441e032 113 0x3C,
lixianyu 0:d8f4c441e032 114
lixianyu 0:d8f4c441e032 115 /* color adjustments */
lixianyu 0:d8f4c441e032 116 #if USE_GREY_TABLE != 1
lixianyu 0:d8f4c441e032 117 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 118 0x81,
lixianyu 0:d8f4c441e032 119 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 120 0xC8, /* Set Contrast Color 1*/
lixianyu 0:d8f4c441e032 121 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 122 0x82,
lixianyu 0:d8f4c441e032 123 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 124 0x80, /* Set Contrast Color 2*/
lixianyu 0:d8f4c441e032 125 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 126 0x83,
lixianyu 0:d8f4c441e032 127 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 128 0xF8, /* Set Contrast Color 3*/
lixianyu 0:d8f4c441e032 129 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 130 0x87,
lixianyu 0:d8f4c441e032 131 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 132 0x09, /* Set Master Contrast MAX */
lixianyu 0:d8f4c441e032 133 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 134 0xB9, /* Set CMD Grayscale Linear */
lixianyu 0:d8f4c441e032 135 #else
lixianyu 0:d8f4c441e032 136 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 137 0x81,
lixianyu 0:d8f4c441e032 138 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 139 0xC8, /* Set Contrast Color 1*/
lixianyu 0:d8f4c441e032 140 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 141 0x82,
lixianyu 0:d8f4c441e032 142 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 143 0xA0, /* Set Contrast Color 2*/
lixianyu 0:d8f4c441e032 144 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 145 0x83,
lixianyu 0:d8f4c441e032 146 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 147 0xB0, /* Set Contrast Color 3*/
lixianyu 0:d8f4c441e032 148 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 149 0x87,
lixianyu 0:d8f4c441e032 150 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 151 0x0F, /* Set Master Contrast MAX */
lixianyu 0:d8f4c441e032 152
lixianyu 0:d8f4c441e032 153 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 154 0xB8, /* Set CMD Grayscale Lookup */
lixianyu 0:d8f4c441e032 155 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 156 0x05, 0x06, 0x07, 0x08,
lixianyu 0:d8f4c441e032 157 0x09, 0x0a, 0x0b, 0x0c,
lixianyu 0:d8f4c441e032 158 0x0D, 0x0E, 0x0F, 0x10,
lixianyu 0:d8f4c441e032 159 0x11, 0x12, 0x13, 0x14,
lixianyu 0:d8f4c441e032 160 0x15, 0x16, 0x18, 0x1a,
lixianyu 0:d8f4c441e032 161 0x1b, 0x1C, 0x1D, 0x1F,
lixianyu 0:d8f4c441e032 162 0x21, 0x23, 0x25, 0x27,
lixianyu 0:d8f4c441e032 163 0x2A, 0x2D, 0x30, 0x33,
lixianyu 0:d8f4c441e032 164 0x36, 0x39, 0x3C, 0x3F,
lixianyu 0:d8f4c441e032 165 0x42, 0x45, 0x48, 0x4C,
lixianyu 0:d8f4c441e032 166 0x50, 0x54, 0x58, 0x5C,
lixianyu 0:d8f4c441e032 167 0x60, 0x64, 0x68, 0x6C,
lixianyu 0:d8f4c441e032 168 0x70, 0x74, 0x78, 0x7D,
lixianyu 0:d8f4c441e032 169 0x82, 0x87, 0x8C, 0x91,
lixianyu 0:d8f4c441e032 170 0x96, 0x9B, 0xA0, 0xA5,
lixianyu 0:d8f4c441e032 171 0xAA, 0xAF, 0xB4,
lixianyu 0:d8f4c441e032 172 #endif
lixianyu 0:d8f4c441e032 173 U8G_ESC_ADR(0),
lixianyu 0:d8f4c441e032 174 0xAF, /* Set Display On */
lixianyu 0:d8f4c441e032 175 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 176 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 177 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 178 };
lixianyu 0:d8f4c441e032 179
lixianyu 0:d8f4c441e032 180
lixianyu 0:d8f4c441e032 181 static const uint8_t u8g_dev_ssd1353_160x128_column_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 182 U8G_ESC_CS(1),
lixianyu 0:d8f4c441e032 183 U8G_ESC_ADR(0), 0x15,
lixianyu 0:d8f4c441e032 184 U8G_ESC_ADR(1), 0x00, 0x9f,
lixianyu 0:d8f4c441e032 185 U8G_ESC_ADR(0), 0x75,
lixianyu 0:d8f4c441e032 186 U8G_ESC_ADR(1), 0x00, 0x7f,
lixianyu 0:d8f4c441e032 187 U8G_ESC_ADR(0), 0x5c,
lixianyu 0:d8f4c441e032 188 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 189 U8G_ESC_CS(0),
lixianyu 0:d8f4c441e032 190 U8G_ESC_END
lixianyu 0:d8f4c441e032 191 };
lixianyu 0:d8f4c441e032 192
lixianyu 0:d8f4c441e032 193 static const uint8_t u8g_dev_ssd1353_160x128_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 194 U8G_ESC_CS(1),
lixianyu 0:d8f4c441e032 195 U8G_ESC_ADR(0), 0xAE,
lixianyu 0:d8f4c441e032 196 U8G_ESC_CS(0),
lixianyu 0:d8f4c441e032 197 U8G_ESC_END
lixianyu 0:d8f4c441e032 198 };
lixianyu 0:d8f4c441e032 199
lixianyu 0:d8f4c441e032 200 static const uint8_t u8g_dev_ssd1353_160x128_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 201 U8G_ESC_CS(1),
lixianyu 0:d8f4c441e032 202 U8G_ESC_ADR(0), 0xAF,
lixianyu 0:d8f4c441e032 203 U8G_ESC_CS(0),
lixianyu 0:d8f4c441e032 204 U8G_ESC_END
lixianyu 0:d8f4c441e032 205 };
lixianyu 0:d8f4c441e032 206
lixianyu 0:d8f4c441e032 207
lixianyu 0:d8f4c441e032 208 #define RGB332_STREAM_BYTES 8
lixianyu 0:d8f4c441e032 209 static uint8_t u8g_ssd1353_stream_bytes[RGB332_STREAM_BYTES*3];
lixianyu 0:d8f4c441e032 210
lixianyu 0:d8f4c441e032 211 uint8_t u8g_dev_ssd1353_160x128_332_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 212 {
lixianyu 0:d8f4c441e032 213 switch(msg)
lixianyu 0:d8f4c441e032 214 {
lixianyu 0:d8f4c441e032 215 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 216 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 217 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_init_seq);
lixianyu 0:d8f4c441e032 218 break;
lixianyu 0:d8f4c441e032 219
lixianyu 0:d8f4c441e032 220 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 221 break;
lixianyu 0:d8f4c441e032 222
lixianyu 0:d8f4c441e032 223 case U8G_DEV_MSG_PAGE_FIRST:
lixianyu 0:d8f4c441e032 224 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_column_seq);
lixianyu 0:d8f4c441e032 225 break;
lixianyu 0:d8f4c441e032 226
lixianyu 0:d8f4c441e032 227 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 228 {
lixianyu 0:d8f4c441e032 229 u8g_uint_t x;
lixianyu 0:d8f4c441e032 230 uint8_t page_height;
lixianyu 0:d8f4c441e032 231 uint8_t i;
lixianyu 0:d8f4c441e032 232 uint8_t cnt;
lixianyu 0:d8f4c441e032 233 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 234 uint8_t *ptr = pb->buf;
lixianyu 0:d8f4c441e032 235
lixianyu 0:d8f4c441e032 236 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 237
lixianyu 0:d8f4c441e032 238 page_height = pb->p.page_y1;
lixianyu 0:d8f4c441e032 239 page_height -= pb->p.page_y0;
lixianyu 0:d8f4c441e032 240 page_height++;
lixianyu 0:d8f4c441e032 241 for( i = 0; i < page_height; i++ )
lixianyu 0:d8f4c441e032 242 {
lixianyu 0:d8f4c441e032 243
lixianyu 0:d8f4c441e032 244 for (x = 0; x < pb->width; x+=RGB332_STREAM_BYTES)
lixianyu 0:d8f4c441e032 245 {
lixianyu 0:d8f4c441e032 246 /* inline operation for better perf */
lixianyu 0:d8f4c441e032 247 uint8_t *dest = u8g_ssd1353_stream_bytes;
lixianyu 0:d8f4c441e032 248 for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
lixianyu 0:d8f4c441e032 249 {
lixianyu 0:d8f4c441e032 250 uint8_t val = *ptr++;
lixianyu 0:d8f4c441e032 251 *dest++ = ((val & 0xe0) >> 2);
lixianyu 0:d8f4c441e032 252 *dest++ = ((val & 0x1c) << 1);
lixianyu 0:d8f4c441e032 253 *dest++ = ((val & 0x03) << 4);
lixianyu 0:d8f4c441e032 254 }
lixianyu 0:d8f4c441e032 255 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1353_stream_bytes);
lixianyu 0:d8f4c441e032 256 }
lixianyu 0:d8f4c441e032 257 }
lixianyu 0:d8f4c441e032 258 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 259 }
lixianyu 0:d8f4c441e032 260
lixianyu 0:d8f4c441e032 261 break;
lixianyu 0:d8f4c441e032 262
lixianyu 0:d8f4c441e032 263 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 264 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_sleep_on);
lixianyu 0:d8f4c441e032 265 break;
lixianyu 0:d8f4c441e032 266 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 267 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_sleep_off);
lixianyu 0:d8f4c441e032 268 break;
lixianyu 0:d8f4c441e032 269 }
lixianyu 0:d8f4c441e032 270
lixianyu 0:d8f4c441e032 271 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 272 }
lixianyu 0:d8f4c441e032 273
lixianyu 0:d8f4c441e032 274 /*
lixianyu 0:d8f4c441e032 275 * not tested and not released, just taken from ssd1351
lixianyu 0:d8f4c441e032 276 */
lixianyu 0:d8f4c441e032 277 static uint8_t u8g_dev_ssd1353_160x128_r[256];
lixianyu 0:d8f4c441e032 278 static uint8_t u8g_dev_ssd1353_160x128_g[256];
lixianyu 0:d8f4c441e032 279 static uint8_t u8g_dev_ssd1353_160x128_b[256];
lixianyu 0:d8f4c441e032 280
lixianyu 0:d8f4c441e032 281 uint8_t u8g_dev_ssd1353_160x128_idx_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 282 {
lixianyu 0:d8f4c441e032 283 // u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 284
lixianyu 0:d8f4c441e032 285 switch(msg)
lixianyu 0:d8f4c441e032 286 {
lixianyu 0:d8f4c441e032 287 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 288 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 289 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_init_seq);
lixianyu 0:d8f4c441e032 290 break;
lixianyu 0:d8f4c441e032 291
lixianyu 0:d8f4c441e032 292 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 293 break;
lixianyu 0:d8f4c441e032 294
lixianyu 0:d8f4c441e032 295 case U8G_DEV_MSG_SET_COLOR_ENTRY:
lixianyu 0:d8f4c441e032 296 u8g_dev_ssd1353_160x128_r[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->r;
lixianyu 0:d8f4c441e032 297 u8g_dev_ssd1353_160x128_g[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->g;
lixianyu 0:d8f4c441e032 298 u8g_dev_ssd1353_160x128_b[ ((u8g_dev_arg_irgb_t *)arg)->idx ] = ((u8g_dev_arg_irgb_t *)arg)->b;
lixianyu 0:d8f4c441e032 299 break;
lixianyu 0:d8f4c441e032 300
lixianyu 0:d8f4c441e032 301 case U8G_DEV_MSG_PAGE_FIRST:
lixianyu 0:d8f4c441e032 302 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_column_seq);
lixianyu 0:d8f4c441e032 303 break;
lixianyu 0:d8f4c441e032 304
lixianyu 0:d8f4c441e032 305 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 306 {
lixianyu 0:d8f4c441e032 307 int x;
lixianyu 0:d8f4c441e032 308 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 309 uint8_t *ptr = pb->buf;
lixianyu 0:d8f4c441e032 310
lixianyu 0:d8f4c441e032 311 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 312
lixianyu 0:d8f4c441e032 313 for (x = 0; x < pb->width; x++)
lixianyu 0:d8f4c441e032 314 {
lixianyu 0:d8f4c441e032 315 u8g_WriteByte(u8g, dev, u8g_dev_ssd1353_160x128_r[(*ptr)>>2]);
lixianyu 0:d8f4c441e032 316 u8g_WriteByte(u8g, dev, u8g_dev_ssd1353_160x128_g[(*ptr)>>2]);
lixianyu 0:d8f4c441e032 317 u8g_WriteByte(u8g, dev, u8g_dev_ssd1353_160x128_b[(*ptr)>>2]);
lixianyu 0:d8f4c441e032 318
lixianyu 0:d8f4c441e032 319 ptr++;
lixianyu 0:d8f4c441e032 320 }
lixianyu 0:d8f4c441e032 321
lixianyu 0:d8f4c441e032 322 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 323 }
lixianyu 0:d8f4c441e032 324
lixianyu 0:d8f4c441e032 325 break;
lixianyu 0:d8f4c441e032 326 case U8G_DEV_MSG_GET_MODE:
lixianyu 0:d8f4c441e032 327 return U8G_MODE_INDEX;
lixianyu 0:d8f4c441e032 328 }
lixianyu 0:d8f4c441e032 329
lixianyu 0:d8f4c441e032 330 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 331 }
lixianyu 0:d8f4c441e032 332
lixianyu 0:d8f4c441e032 333 uint8_t u8g_dev_ssd1353_160x128_hicolor_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 334 {
lixianyu 0:d8f4c441e032 335 switch(msg)
lixianyu 0:d8f4c441e032 336 {
lixianyu 0:d8f4c441e032 337 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 338 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 339 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_init_seq);
lixianyu 0:d8f4c441e032 340 break;
lixianyu 0:d8f4c441e032 341 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 342 break;
lixianyu 0:d8f4c441e032 343 case U8G_DEV_MSG_PAGE_FIRST:
lixianyu 0:d8f4c441e032 344 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_column_seq);
lixianyu 0:d8f4c441e032 345 break;
lixianyu 0:d8f4c441e032 346 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 347 {
lixianyu 0:d8f4c441e032 348 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 349 uint8_t i, j;
lixianyu 0:d8f4c441e032 350 uint8_t page_height;
lixianyu 0:d8f4c441e032 351 uint8_t *ptr = pb->buf;
lixianyu 0:d8f4c441e032 352
lixianyu 0:d8f4c441e032 353 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 354
lixianyu 0:d8f4c441e032 355 page_height = pb->p.page_y1;
lixianyu 0:d8f4c441e032 356 page_height -= pb->p.page_y0;
lixianyu 0:d8f4c441e032 357 page_height++;
lixianyu 0:d8f4c441e032 358 for( j = 0; j < page_height; j++ )
lixianyu 0:d8f4c441e032 359 {
lixianyu 0:d8f4c441e032 360 for (i = 0; i < pb->width; i+=RGB332_STREAM_BYTES)
lixianyu 0:d8f4c441e032 361 {
lixianyu 0:d8f4c441e032 362 register uint8_t cnt, low, high, r, g, b;
lixianyu 0:d8f4c441e032 363 uint8_t *dest = u8g_ssd1353_stream_bytes;
lixianyu 0:d8f4c441e032 364 for( cnt = 0; cnt < RGB332_STREAM_BYTES; cnt++ )
lixianyu 0:d8f4c441e032 365 {
lixianyu 0:d8f4c441e032 366 low = *ptr++;
lixianyu 0:d8f4c441e032 367 high = *ptr++;
lixianyu 0:d8f4c441e032 368
lixianyu 0:d8f4c441e032 369 r = high & ~7;
lixianyu 0:d8f4c441e032 370 r >>= 2;
lixianyu 0:d8f4c441e032 371 b = low & 31;
lixianyu 0:d8f4c441e032 372 b <<= 1;
lixianyu 0:d8f4c441e032 373 g = high & 7;
lixianyu 0:d8f4c441e032 374 g <<= 3;
lixianyu 0:d8f4c441e032 375 g |= (low>>5)&7;
lixianyu 0:d8f4c441e032 376
lixianyu 0:d8f4c441e032 377 *dest++ = r;
lixianyu 0:d8f4c441e032 378 *dest++ = g;
lixianyu 0:d8f4c441e032 379 *dest++ = b;
lixianyu 0:d8f4c441e032 380 }
lixianyu 0:d8f4c441e032 381 u8g_WriteSequence(u8g, dev, RGB332_STREAM_BYTES*3, u8g_ssd1353_stream_bytes);
lixianyu 0:d8f4c441e032 382 }
lixianyu 0:d8f4c441e032 383 }
lixianyu 0:d8f4c441e032 384 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 385 }
lixianyu 0:d8f4c441e032 386 break; /* continue to base fn */
lixianyu 0:d8f4c441e032 387 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 388 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_sleep_on);
lixianyu 0:d8f4c441e032 389 break;
lixianyu 0:d8f4c441e032 390 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 391 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1353_160x128_sleep_off);
lixianyu 0:d8f4c441e032 392 break;
lixianyu 0:d8f4c441e032 393 }
lixianyu 0:d8f4c441e032 394 return u8g_dev_pbxh16_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 395 }
lixianyu 0:d8f4c441e032 396
lixianyu 0:d8f4c441e032 397
lixianyu 0:d8f4c441e032 398 uint8_t u8g_dev_ssd1353_160x128_byte_buf[WIDTH*PAGE_HEIGHT] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 399
lixianyu 0:d8f4c441e032 400 u8g_pb_t u8g_dev_ssd1353_160x128_byte_pb = { {PAGE_HEIGHT, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1353_160x128_byte_buf};
lixianyu 0:d8f4c441e032 401 u8g_dev_t u8g_dev_ssd1353_160x128_332_sw_spi = { u8g_dev_ssd1353_160x128_332_fn, &u8g_dev_ssd1353_160x128_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 402 u8g_dev_t u8g_dev_ssd1353_160x128_332_hw_spi = { u8g_dev_ssd1353_160x128_332_fn, &u8g_dev_ssd1353_160x128_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 403
lixianyu 0:d8f4c441e032 404 //u8g_dev_t u8g_dev_ssd1353_160x128_idx_sw_spi = { u8g_dev_ssd1353_160x128_idx_fn, &u8g_dev_ssd1353_160x128_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 405 //u8g_dev_t u8g_dev_ssd1353_160x128_idx_hw_spi = { u8g_dev_ssd1353_160x128_idx_fn, &u8g_dev_ssd1353_160x128_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 406
lixianyu 0:d8f4c441e032 407
lixianyu 0:d8f4c441e032 408 /* only half of the height, because two bytes are needed for one pixel */
lixianyu 0:d8f4c441e032 409 u8g_pb_t u8g_dev_ssd1353_160x128_hicolor_byte_pb = { {PAGE_HEIGHT/2, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1353_160x128_byte_buf};
lixianyu 0:d8f4c441e032 410 u8g_dev_t u8g_dev_ssd1353_160x128_hicolor_sw_spi = { u8g_dev_ssd1353_160x128_hicolor_fn, &u8g_dev_ssd1353_160x128_hicolor_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 411 u8g_dev_t u8g_dev_ssd1353_160x128_hicolor_hw_spi = { u8g_dev_ssd1353_160x128_hicolor_fn, &u8g_dev_ssd1353_160x128_hicolor_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 412
lixianyu 0:d8f4c441e032 413
lixianyu 0:d8f4c441e032 414 /* the 4x buffer is removed since it does not fit the RAM space of very small MCUs */
lixianyu 0:d8f4c441e032 415 #if 0
lixianyu 0:d8f4c441e032 416 uint8_t u8g_dev_ssd1353_160x128_4x_byte_buf[WIDTH*PAGE_HEIGHT*4] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 417
lixianyu 0:d8f4c441e032 418 u8g_pb_t u8g_dev_ssd1353_160x128_4x_332_byte_pb = { {PAGE_HEIGHT*4, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1353_160x128_4x_byte_buf};
lixianyu 0:d8f4c441e032 419 u8g_dev_t u8g_dev_ssd1353_160x128_4x_332_sw_spi = { u8g_dev_ssd1353_160x128_332_fn, &u8g_dev_ssd1353_160x128_4x_332_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 420 u8g_dev_t u8g_dev_ssd1353_160x128_4x_332_hw_spi = { u8g_dev_ssd1353_160x128_332_fn, &u8g_dev_ssd1353_160x128_4x_332_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 421
lixianyu 0:d8f4c441e032 422 u8g_pb_t u8g_dev_ssd1353_160x128_4x_hicolor_byte_pb = { {PAGE_HEIGHT/2*4, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1353_160x128_4x_byte_buf};
lixianyu 0:d8f4c441e032 423 u8g_dev_t u8g_dev_ssd1353_160x128_4x_hicolor_sw_spi = { u8g_dev_ssd1353_160x128_hicolor_fn, &u8g_dev_ssd1353_160x128_4x_hicolor_byte_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 424 u8g_dev_t u8g_dev_ssd1353_160x128_4x_hicolor_hw_spi = { u8g_dev_ssd1353_160x128_hicolor_fn, &u8g_dev_ssd1353_160x128_4x_hicolor_byte_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 425 #endif
lixianyu 0:d8f4c441e032 426