hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1327_96x96_gr.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ssd1327_96x96_gr.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 2-Bit (graylevel) Driver for SSD1327 Controller (OLED Display)
lixianyu 0:d8f4c441e032 6 Tested with Seedstudio 96x96 Oled (LY120)
lixianyu 0:d8f4c441e032 7 http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96
lixianyu 0:d8f4c441e032 8
lixianyu 0:d8f4c441e032 9 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 10
lixianyu 0:d8f4c441e032 11 Copyright (c) 2012, olikraus@gmail.com
lixianyu 0:d8f4c441e032 12 All rights reserved.
lixianyu 0:d8f4c441e032 13
lixianyu 0:d8f4c441e032 14 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 15 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 16
lixianyu 0:d8f4c441e032 17 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 18 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 21 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 22 materials provided with the distribution.
lixianyu 0:d8f4c441e032 23
lixianyu 0:d8f4c441e032 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 26 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 27 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 28 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 29 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 30 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 32 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 33 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 34 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 35 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 36 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 37
lixianyu 0:d8f4c441e032 38 SSD130x Monochrom OLED Controller
lixianyu 0:d8f4c441e032 39 SSD131x Character OLED Controller
lixianyu 0:d8f4c441e032 40 SSD132x Graylevel OLED Controller
lixianyu 0:d8f4c441e032 41 SSD1331 Color OLED Controller
lixianyu 0:d8f4c441e032 42
lixianyu 0:d8f4c441e032 43 */
lixianyu 0:d8f4c441e032 44
lixianyu 0:d8f4c441e032 45 #include "u8g.h"
lixianyu 0:d8f4c441e032 46
lixianyu 0:d8f4c441e032 47 #define WIDTH 96
lixianyu 0:d8f4c441e032 48 #define HEIGHT 96
lixianyu 0:d8f4c441e032 49 #define XOFFSET 8
lixianyu 0:d8f4c441e032 50
lixianyu 0:d8f4c441e032 51 /*
lixianyu 0:d8f4c441e032 52 http://www.seeedstudio.com/wiki/index.php?title=Twig_-_OLED_96x96
lixianyu 0:d8f4c441e032 53 */
lixianyu 0:d8f4c441e032 54 static const uint8_t u8g_dev_ssd1327_2bit_96x96_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 55 U8G_ESC_DLY(10), /* delay 10 ms */
lixianyu 0:d8f4c441e032 56 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 57 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 58 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 59 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 60 0x0fd, 0x012, /* unlock display, usually not required because the display is unlocked after reset */
lixianyu 0:d8f4c441e032 61 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 62 0x0a8, 0x05f, /* multiplex ratio: 0x05f * 1/64 duty */
lixianyu 0:d8f4c441e032 63 0x0a1, 0x000, /* display start line */
lixianyu 0:d8f4c441e032 64 0x0a2, 0x060, /* display offset, shift mapping ram counter */
lixianyu 0:d8f4c441e032 65 //0x0a2, 0x04c, /* NHD: display offset, shift mapping ram counter */
lixianyu 0:d8f4c441e032 66 0x0a0, 0x046, /* remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
lixianyu 0:d8f4c441e032 67 //0x0a0, 0x056, /* NHD: remap configuration, vertical address increment, enable nibble remap (upper nibble is left) */
lixianyu 0:d8f4c441e032 68 0x0ab, 0x001, /* Enable internal VDD regulator (RESET) */
lixianyu 0:d8f4c441e032 69 0x081, 0x053, /* contrast, brightness, 0..128, Newhaven: 0x040, LY120 0x053, 0x070 seems also ok */
lixianyu 0:d8f4c441e032 70 0x0b1, 0x051, /* phase length */
lixianyu 0:d8f4c441e032 71 0x0b3, 0x001, /* set display clock divide ratio/oscillator frequency */
lixianyu 0:d8f4c441e032 72 0x0b9, /* use linear lookup table */
lixianyu 0:d8f4c441e032 73 #if 0
lixianyu 0:d8f4c441e032 74 0x0b8, /* set gray scale table */
lixianyu 0:d8f4c441e032 75 //0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
lixianyu 0:d8f4c441e032 76 0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x077, 0x077, // 4L mode uses 0, 2, 4, 7
lixianyu 0:d8f4c441e032 77 #endif
lixianyu 0:d8f4c441e032 78 0x0bc, 0x008, /* pre-charge voltage level */
lixianyu 0:d8f4c441e032 79 0x0be, 0x007, /* VCOMH voltage */
lixianyu 0:d8f4c441e032 80 0x0b6, 0x001, /* second precharge */
lixianyu 0:d8f4c441e032 81 0x0d5, 0x062, /* enable second precharge, internal vsl (bit0 = 0) */
lixianyu 0:d8f4c441e032 82
lixianyu 0:d8f4c441e032 83 #if 0
lixianyu 0:d8f4c441e032 84 // the following commands are not used by the SeeedGrayOLED sequence */
lixianyu 0:d8f4c441e032 85 0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
lixianyu 0:d8f4c441e032 86 0x086, /* full current range (0x084, 0x085, 0x086) */
lixianyu 0:d8f4c441e032 87 0x0b2, 0x051, /* frame frequency (row period) */
lixianyu 0:d8f4c441e032 88 0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 89 0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 90 0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 91 #endif
lixianyu 0:d8f4c441e032 92
lixianyu 0:d8f4c441e032 93 0x0a5, /* all pixel on */
lixianyu 0:d8f4c441e032 94 //0x02e, /* no scroll (according to SeeedGrayOLED sequence) */
lixianyu 0:d8f4c441e032 95 0x0af, /* display on */
lixianyu 0:d8f4c441e032 96 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 97 0x0a4, /* normal display mode */
lixianyu 0:d8f4c441e032 98 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 99 0x0a5, /* all pixel on */
lixianyu 0:d8f4c441e032 100 0x0af, /* display on */
lixianyu 0:d8f4c441e032 101 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 102 0x0a4, /* normal display mode */
lixianyu 0:d8f4c441e032 103
lixianyu 0:d8f4c441e032 104 0x015, /* column address... */
lixianyu 0:d8f4c441e032 105 0x008, /* start at column 8, special for the LY120 ??? */
lixianyu 0:d8f4c441e032 106 0x037, /* end at column 55, note: there are two pixel in one column */
lixianyu 0:d8f4c441e032 107
lixianyu 0:d8f4c441e032 108 0x075, /* row address... */
lixianyu 0:d8f4c441e032 109 0x008,
lixianyu 0:d8f4c441e032 110 0x05f,
lixianyu 0:d8f4c441e032 111
lixianyu 0:d8f4c441e032 112 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 113 0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
lixianyu 0:d8f4c441e032 114 0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
lixianyu 0:d8f4c441e032 115 0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
lixianyu 0:d8f4c441e032 116 0x000f, 0x000f, 0x0000, 0x0000, 0x000f,0x000f,0x0000,0x0000,
lixianyu 0:d8f4c441e032 117
lixianyu 0:d8f4c441e032 118 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 119 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 120 };
lixianyu 0:d8f4c441e032 121
lixianyu 0:d8f4c441e032 122 static const uint8_t u8g_dev_ssd1327_2bit_96x96_prepare_page_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 123 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 124 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 125 0x015, /* column address... */
lixianyu 0:d8f4c441e032 126 XOFFSET, /* start at column 8, special for the LY120 ??? */
lixianyu 0:d8f4c441e032 127 0x037, /* end at column 55, note: there are two pixel in one column */
lixianyu 0:d8f4c441e032 128 0x075, /* row address... */
lixianyu 0:d8f4c441e032 129 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 130 };
lixianyu 0:d8f4c441e032 131
lixianyu 0:d8f4c441e032 132
lixianyu 0:d8f4c441e032 133 static void u8g_dev_ssd1327_2bit_prepare_page(u8g_t *u8g, u8g_dev_t *dev)
lixianyu 0:d8f4c441e032 134 {
lixianyu 0:d8f4c441e032 135 uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
lixianyu 0:d8f4c441e032 136
lixianyu 0:d8f4c441e032 137 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_prepare_page_seq);
lixianyu 0:d8f4c441e032 138
lixianyu 0:d8f4c441e032 139 page <<= 2;
lixianyu 0:d8f4c441e032 140 u8g_WriteByte(u8g, dev, page); /* start at the selected page */
lixianyu 0:d8f4c441e032 141 page += 3;
lixianyu 0:d8f4c441e032 142 u8g_WriteByte(u8g, dev, page); /* end within the selected page */
lixianyu 0:d8f4c441e032 143
lixianyu 0:d8f4c441e032 144 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 145 }
lixianyu 0:d8f4c441e032 146
lixianyu 0:d8f4c441e032 147 static void u8g_dev_ssd1327_2bit_2x_prepare_page(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
lixianyu 0:d8f4c441e032 148 {
lixianyu 0:d8f4c441e032 149 uint8_t page = ((u8g_pb_t *)(dev->dev_mem))->p.page;
lixianyu 0:d8f4c441e032 150
lixianyu 0:d8f4c441e032 151 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_prepare_page_seq);
lixianyu 0:d8f4c441e032 152
lixianyu 0:d8f4c441e032 153 page <<= 1;
lixianyu 0:d8f4c441e032 154 page += is_odd;
lixianyu 0:d8f4c441e032 155
lixianyu 0:d8f4c441e032 156 page <<= 2;
lixianyu 0:d8f4c441e032 157 u8g_WriteByte(u8g, dev, page); /* start at the selected page */
lixianyu 0:d8f4c441e032 158 page += 3;
lixianyu 0:d8f4c441e032 159 u8g_WriteByte(u8g, dev, page); /* end within the selected page */
lixianyu 0:d8f4c441e032 160
lixianyu 0:d8f4c441e032 161 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 162 }
lixianyu 0:d8f4c441e032 163
lixianyu 0:d8f4c441e032 164 /* assumes row autoincrement and activated nibble remap */
lixianyu 0:d8f4c441e032 165 static void u8g_dev_ssd1327_2bit_write_4_pixel(u8g_t *u8g, u8g_dev_t *dev, uint8_t left, uint8_t right)
lixianyu 0:d8f4c441e032 166 {
lixianyu 0:d8f4c441e032 167 uint8_t d, tmp, cnt;
lixianyu 0:d8f4c441e032 168 static uint8_t buf[4];
lixianyu 0:d8f4c441e032 169 buf[0] = 0;
lixianyu 0:d8f4c441e032 170 buf[1] = 0;
lixianyu 0:d8f4c441e032 171 buf[2] = 0;
lixianyu 0:d8f4c441e032 172 buf[3] = 0;
lixianyu 0:d8f4c441e032 173 cnt = 0;
lixianyu 0:d8f4c441e032 174 do
lixianyu 0:d8f4c441e032 175 {
lixianyu 0:d8f4c441e032 176 if ( left == 0 && right == 0 )
lixianyu 0:d8f4c441e032 177 break;
lixianyu 0:d8f4c441e032 178 d = left;
lixianyu 0:d8f4c441e032 179 d &= 3;
lixianyu 0:d8f4c441e032 180 d <<= 4;
lixianyu 0:d8f4c441e032 181 tmp = right;
lixianyu 0:d8f4c441e032 182 tmp &= 3;
lixianyu 0:d8f4c441e032 183 d |= tmp;
lixianyu 0:d8f4c441e032 184 d <<= 2;
lixianyu 0:d8f4c441e032 185 buf[cnt] = d;
lixianyu 0:d8f4c441e032 186 left >>= 2;
lixianyu 0:d8f4c441e032 187 right >>= 2;
lixianyu 0:d8f4c441e032 188 cnt++;
lixianyu 0:d8f4c441e032 189 }while ( cnt < 4 );
lixianyu 0:d8f4c441e032 190 u8g_WriteSequence(u8g, dev, 4, buf);
lixianyu 0:d8f4c441e032 191 }
lixianyu 0:d8f4c441e032 192
lixianyu 0:d8f4c441e032 193 static void u8g_dev_ssd1327_2bit_write_buffer(u8g_t *u8g, u8g_dev_t *dev)
lixianyu 0:d8f4c441e032 194 {
lixianyu 0:d8f4c441e032 195 uint8_t cnt, left, right;
lixianyu 0:d8f4c441e032 196 uint8_t *ptr;
lixianyu 0:d8f4c441e032 197 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 198
lixianyu 0:d8f4c441e032 199 cnt = pb->width;
lixianyu 0:d8f4c441e032 200 cnt >>= 1;
lixianyu 0:d8f4c441e032 201 ptr = pb->buf;
lixianyu 0:d8f4c441e032 202 do
lixianyu 0:d8f4c441e032 203 {
lixianyu 0:d8f4c441e032 204 left = *ptr++;
lixianyu 0:d8f4c441e032 205 right = *ptr++;
lixianyu 0:d8f4c441e032 206 u8g_dev_ssd1327_2bit_write_4_pixel(u8g, dev, left, right);
lixianyu 0:d8f4c441e032 207 cnt--;
lixianyu 0:d8f4c441e032 208 } while( cnt > 0 );
lixianyu 0:d8f4c441e032 209 }
lixianyu 0:d8f4c441e032 210
lixianyu 0:d8f4c441e032 211 static void u8g_dev_ssd1327_2bit_2x_write_buffer(u8g_t *u8g, u8g_dev_t *dev, uint8_t is_odd)
lixianyu 0:d8f4c441e032 212 {
lixianyu 0:d8f4c441e032 213 uint8_t cnt, left, right;
lixianyu 0:d8f4c441e032 214 uint8_t *ptr;
lixianyu 0:d8f4c441e032 215 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 216
lixianyu 0:d8f4c441e032 217 ptr = pb->buf;
lixianyu 0:d8f4c441e032 218 cnt = pb->width;
lixianyu 0:d8f4c441e032 219 if ( is_odd )
lixianyu 0:d8f4c441e032 220 ptr += cnt;
lixianyu 0:d8f4c441e032 221 cnt >>= 1;
lixianyu 0:d8f4c441e032 222 do
lixianyu 0:d8f4c441e032 223 {
lixianyu 0:d8f4c441e032 224 left = *ptr++;
lixianyu 0:d8f4c441e032 225 right = *ptr++;
lixianyu 0:d8f4c441e032 226 u8g_dev_ssd1327_2bit_write_4_pixel(u8g, dev, left, right);
lixianyu 0:d8f4c441e032 227 cnt--;
lixianyu 0:d8f4c441e032 228 } while( cnt > 0 );
lixianyu 0:d8f4c441e032 229 }
lixianyu 0:d8f4c441e032 230
lixianyu 0:d8f4c441e032 231 uint8_t u8g_dev_ssd1327_96x96_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 232 {
lixianyu 0:d8f4c441e032 233 switch(msg)
lixianyu 0:d8f4c441e032 234 {
lixianyu 0:d8f4c441e032 235 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 236 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 237 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_init_seq);
lixianyu 0:d8f4c441e032 238 break;
lixianyu 0:d8f4c441e032 239 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 240 break;
lixianyu 0:d8f4c441e032 241 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 242 {
lixianyu 0:d8f4c441e032 243 u8g_dev_ssd1327_2bit_prepare_page(u8g, dev);
lixianyu 0:d8f4c441e032 244 u8g_dev_ssd1327_2bit_write_buffer(u8g, dev);
lixianyu 0:d8f4c441e032 245 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 246 }
lixianyu 0:d8f4c441e032 247 break;
lixianyu 0:d8f4c441e032 248 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 249 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 250 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 251 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 252 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
lixianyu 0:d8f4c441e032 253 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 254 return 1;
lixianyu 0:d8f4c441e032 255 }
lixianyu 0:d8f4c441e032 256 return u8g_dev_pb8v2_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 257 }
lixianyu 0:d8f4c441e032 258
lixianyu 0:d8f4c441e032 259 uint8_t u8g_dev_ssd1327_96x96_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 260 {
lixianyu 0:d8f4c441e032 261 switch(msg)
lixianyu 0:d8f4c441e032 262 {
lixianyu 0:d8f4c441e032 263 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 264 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 265 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1327_2bit_96x96_init_seq);
lixianyu 0:d8f4c441e032 266 break;
lixianyu 0:d8f4c441e032 267 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 268 break;
lixianyu 0:d8f4c441e032 269 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 270 {
lixianyu 0:d8f4c441e032 271 u8g_dev_ssd1327_2bit_2x_prepare_page(u8g, dev, 0);
lixianyu 0:d8f4c441e032 272 u8g_dev_ssd1327_2bit_2x_write_buffer(u8g, dev, 0);
lixianyu 0:d8f4c441e032 273 u8g_dev_ssd1327_2bit_2x_prepare_page(u8g, dev, 1);
lixianyu 0:d8f4c441e032 274 u8g_dev_ssd1327_2bit_2x_write_buffer(u8g, dev, 1);
lixianyu 0:d8f4c441e032 275 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 276 }
lixianyu 0:d8f4c441e032 277 break;
lixianyu 0:d8f4c441e032 278 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 279 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 280 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 281 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 282 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
lixianyu 0:d8f4c441e032 283 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 284 return 1;
lixianyu 0:d8f4c441e032 285 }
lixianyu 0:d8f4c441e032 286 return u8g_dev_pb16v2_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 287 }
lixianyu 0:d8f4c441e032 288
lixianyu 0:d8f4c441e032 289 U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 290 U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 291 U8G_PB_DEV(u8g_dev_ssd1327_96x96_gr_i2c , WIDTH, HEIGHT, 4, u8g_dev_ssd1327_96x96_gr_fn, U8G_COM_SSD_I2C);
lixianyu 0:d8f4c441e032 292
lixianyu 0:d8f4c441e032 293 #define DWIDTH (2*WIDTH)
lixianyu 0:d8f4c441e032 294 uint8_t u8g_dev_ssd1327_96x96_2x_buf[DWIDTH] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 295 u8g_pb_t u8g_dev_ssd1327_96x96_2x_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1327_96x96_2x_buf};
lixianyu 0:d8f4c441e032 296 u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_sw_spi = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 297 u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_hw_spi = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 298 u8g_dev_t u8g_dev_ssd1327_96x96_2x_gr_i2c = { u8g_dev_ssd1327_96x96_2x_gr_fn, &u8g_dev_ssd1327_96x96_2x_pb, U8G_COM_SSD_I2C };
lixianyu 0:d8f4c441e032 299
lixianyu 0:d8f4c441e032 300