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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1325_nhd27oled_bw_new.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ssd1325_nhd27oled_bw.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 1-Bit (BW) Driver for SSD1325 Controller (OLED Display)
lixianyu 0:d8f4c441e032 6 Horizontal architecture, completly rewritten
lixianyu 0:d8f4c441e032 7 Tested with NHD-2.7-12864UCY3
lixianyu 0:d8f4c441e032 8
lixianyu 0:d8f4c441e032 9 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 10
lixianyu 0:d8f4c441e032 11 Copyright (c) 2012, olikraus@gmail.com
lixianyu 0:d8f4c441e032 12 All rights reserved.
lixianyu 0:d8f4c441e032 13
lixianyu 0:d8f4c441e032 14 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 15 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 16
lixianyu 0:d8f4c441e032 17 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 18 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 21 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 22 materials provided with the distribution.
lixianyu 0:d8f4c441e032 23
lixianyu 0:d8f4c441e032 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 26 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 27 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 28 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 29 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 30 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 32 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 33 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 34 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 35 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 36 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 37
lixianyu 0:d8f4c441e032 38 SSD130x Monochrom OLED Controller
lixianyu 0:d8f4c441e032 39 SSD131x Character OLED Controller
lixianyu 0:d8f4c441e032 40 SSD132x Graylevel OLED Controller
lixianyu 0:d8f4c441e032 41 SSD1331 Color OLED Controller
lixianyu 0:d8f4c441e032 42
lixianyu 0:d8f4c441e032 43 */
lixianyu 0:d8f4c441e032 44
lixianyu 0:d8f4c441e032 45 #include "u8g.h"
lixianyu 0:d8f4c441e032 46
lixianyu 0:d8f4c441e032 47 /* width must be multiple of 8, largest value is 248 unless u8g 16 bit mode is enabled */
lixianyu 0:d8f4c441e032 48 #define WIDTH 128
lixianyu 0:d8f4c441e032 49 #define HEIGHT 64
lixianyu 0:d8f4c441e032 50
lixianyu 0:d8f4c441e032 51 /* http://www.newhavendisplay.com/app_notes/OLED_2_7_12864.txt */
lixianyu 0:d8f4c441e032 52 static const uint8_t u8g_dev_ssd1325_nhd_27_12864_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 53 U8G_ESC_DLY(10), /* delay 10 ms */
lixianyu 0:d8f4c441e032 54 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 55 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 56 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 57 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 58 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 59 0x0b3, 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 135 frames/sec) */
lixianyu 0:d8f4c441e032 60 0x0a8, 0x03f, /* multiplex ratio: 0x03f * 1/64 duty */
lixianyu 0:d8f4c441e032 61 0x0a2, 0x04c, /* display offset, shift mapping ram counter */
lixianyu 0:d8f4c441e032 62 0x0a1, 0x000, /* display start line */
lixianyu 0:d8f4c441e032 63 0x0ad, 0x002, /* master configuration: disable embedded DC-DC, enable internal VCOMH */
lixianyu 0:d8f4c441e032 64 0x0a0, 0x052, /* remap configuration, horizontal address increment (bit 2 = 0), enable nibble remap (upper nibble is left, bit 1 = 1) */
lixianyu 0:d8f4c441e032 65 0x086, /* full current range (0x084, 0x085, 0x086) */
lixianyu 0:d8f4c441e032 66 0x0b8, /* set gray scale table */
lixianyu 0:d8f4c441e032 67 0x01, 0x011, 0x022, 0x032, 0x043, 0x054, 0x065, 0x076,
lixianyu 0:d8f4c441e032 68
lixianyu 0:d8f4c441e032 69 0x081, 0x070, /* contrast, brightness, 0..128, Newhaven: 0x040 */
lixianyu 0:d8f4c441e032 70 0x0b2, 0x051, /* frame frequency (row period) */
lixianyu 0:d8f4c441e032 71 0x0b1, 0x055, /* phase length */
lixianyu 0:d8f4c441e032 72 0x0bc, 0x010, /* pre-charge voltage level */
lixianyu 0:d8f4c441e032 73 0x0b4, 0x002, /* set pre-charge compensation level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 74 0x0b0, 0x028, /* enable pre-charge compensation (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 75 0x0be, 0x01c, /* VCOMH voltage */
lixianyu 0:d8f4c441e032 76 0x0bf, 0x002|0x00d, /* VSL voltage level (not documented in the SDD1325 datasheet, but used in the NHD init seq.) */
lixianyu 0:d8f4c441e032 77 0x0a4, /* normal display mode */
lixianyu 0:d8f4c441e032 78 0x0af, /* display on */
lixianyu 0:d8f4c441e032 79 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 80 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 81 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 82 };
lixianyu 0:d8f4c441e032 83
lixianyu 0:d8f4c441e032 84 static const uint8_t u8g_dev_ssd1325_prepare_row_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 85 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 86 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 87 0x015, /* column address... */
lixianyu 0:d8f4c441e032 88 0x000, /* start at column 0 */
lixianyu 0:d8f4c441e032 89 0x03f, /* end at column 63 (which is y == 127), because there are two pixel in one column */
lixianyu 0:d8f4c441e032 90 0x075, /* row address... */
lixianyu 0:d8f4c441e032 91 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 92 };
lixianyu 0:d8f4c441e032 93
lixianyu 0:d8f4c441e032 94 static void u8g_dev_ssd1325_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
lixianyu 0:d8f4c441e032 95 {
lixianyu 0:d8f4c441e032 96 uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
lixianyu 0:d8f4c441e032 97
lixianyu 0:d8f4c441e032 98 row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
lixianyu 0:d8f4c441e032 99 row += delta_row;
lixianyu 0:d8f4c441e032 100
lixianyu 0:d8f4c441e032 101 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_prepare_row_seq);
lixianyu 0:d8f4c441e032 102
lixianyu 0:d8f4c441e032 103 u8g_WriteByte(u8g, dev, row); /* start at the selected row */
lixianyu 0:d8f4c441e032 104 u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
lixianyu 0:d8f4c441e032 105
lixianyu 0:d8f4c441e032 106 //u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
lixianyu 0:d8f4c441e032 107 //u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
lixianyu 0:d8f4c441e032 108 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 109 }
lixianyu 0:d8f4c441e032 110
lixianyu 0:d8f4c441e032 111 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 112 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 113 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 114 0x0ae, /* display off */
lixianyu 0:d8f4c441e032 115 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 116 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 117 };
lixianyu 0:d8f4c441e032 118
lixianyu 0:d8f4c441e032 119 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 120 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 121 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 122 0x0af, /* display on */
lixianyu 0:d8f4c441e032 123 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 124 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 125 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 126 };
lixianyu 0:d8f4c441e032 127
lixianyu 0:d8f4c441e032 128
lixianyu 0:d8f4c441e032 129 static uint8_t u8g_dev_ssd1325_nhd27oled_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 130 {
lixianyu 0:d8f4c441e032 131 switch(msg)
lixianyu 0:d8f4c441e032 132 {
lixianyu 0:d8f4c441e032 133 //case U8G_DEV_MSG_IS_BBX_INTERSECTION:
lixianyu 0:d8f4c441e032 134 // return u8g_pb_IsIntersection((u8g_pb_t *)(dev->dev_mem), (u8g_dev_arg_bbx_t *)arg);
lixianyu 0:d8f4c441e032 135 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 136 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 137 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_nhd_27_12864_init_seq);
lixianyu 0:d8f4c441e032 138 break;
lixianyu 0:d8f4c441e032 139 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 140 break;
lixianyu 0:d8f4c441e032 141 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 142 {
lixianyu 0:d8f4c441e032 143 uint8_t i;
lixianyu 0:d8f4c441e032 144 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 145 uint8_t *p = pb->buf;
lixianyu 0:d8f4c441e032 146 u8g_uint_t cnt;
lixianyu 0:d8f4c441e032 147 cnt = pb->width;
lixianyu 0:d8f4c441e032 148 cnt >>= 3;
lixianyu 0:d8f4c441e032 149
lixianyu 0:d8f4c441e032 150 for( i = 0; i < pb->p.page_height; i++ )
lixianyu 0:d8f4c441e032 151 {
lixianyu 0:d8f4c441e032 152 u8g_dev_ssd1325_prepare_row(u8g, dev, i); /* this will also enable chip select */
lixianyu 0:d8f4c441e032 153 u8g_WriteSequenceBWTo16GrDevice(u8g, dev, cnt, p);
lixianyu 0:d8f4c441e032 154 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 155 p+=cnt;
lixianyu 0:d8f4c441e032 156 }
lixianyu 0:d8f4c441e032 157 }
lixianyu 0:d8f4c441e032 158 break;
lixianyu 0:d8f4c441e032 159 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 160 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 161 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 162 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 163 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
lixianyu 0:d8f4c441e032 164 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 165 break;
lixianyu 0:d8f4c441e032 166 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 167 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 168 return 1;
lixianyu 0:d8f4c441e032 169 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 170 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 171 return 1;
lixianyu 0:d8f4c441e032 172 }
lixianyu 0:d8f4c441e032 173 return u8g_dev_pb8h1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 174 }
lixianyu 0:d8f4c441e032 175
lixianyu 0:d8f4c441e032 176 static uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 177 {
lixianyu 0:d8f4c441e032 178 switch(msg)
lixianyu 0:d8f4c441e032 179 {
lixianyu 0:d8f4c441e032 180 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 181 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 182 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1325_nhd_27_12864_init_seq);
lixianyu 0:d8f4c441e032 183 break;
lixianyu 0:d8f4c441e032 184 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 185 break;
lixianyu 0:d8f4c441e032 186 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 187 {
lixianyu 0:d8f4c441e032 188 uint8_t i;
lixianyu 0:d8f4c441e032 189 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 190 uint8_t *p = pb->buf;
lixianyu 0:d8f4c441e032 191 u8g_uint_t cnt;
lixianyu 0:d8f4c441e032 192 cnt = pb->width;
lixianyu 0:d8f4c441e032 193 cnt >>= 3;
lixianyu 0:d8f4c441e032 194
lixianyu 0:d8f4c441e032 195 for( i = 0; i < pb->p.page_height; i++ )
lixianyu 0:d8f4c441e032 196 {
lixianyu 0:d8f4c441e032 197 u8g_dev_ssd1325_prepare_row(u8g, dev, i); /* this will also enable chip select */
lixianyu 0:d8f4c441e032 198 u8g_WriteSequenceBWTo16GrDevice(u8g, dev, cnt, p);
lixianyu 0:d8f4c441e032 199 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 200 p+=cnt;
lixianyu 0:d8f4c441e032 201 }
lixianyu 0:d8f4c441e032 202 }
lixianyu 0:d8f4c441e032 203 break;
lixianyu 0:d8f4c441e032 204 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 205 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 206 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 207 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 208 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
lixianyu 0:d8f4c441e032 209 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 210 break;
lixianyu 0:d8f4c441e032 211 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 212 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 213 return 1;
lixianyu 0:d8f4c441e032 214 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 215 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 216 return 1;
lixianyu 0:d8f4c441e032 217 }
lixianyu 0:d8f4c441e032 218 return u8g_dev_pb16h1_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 219 }
lixianyu 0:d8f4c441e032 220
lixianyu 0:d8f4c441e032 221
lixianyu 0:d8f4c441e032 222
lixianyu 0:d8f4c441e032 223 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_sw_spi , WIDTH, HEIGHT, 8, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 224 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_hw_spi , WIDTH, HEIGHT, 8, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 225 U8G_PB_DEV(u8g_dev_ssd1325_nhd27oled_bw_parallel , WIDTH, HEIGHT, 8, u8g_dev_ssd1325_nhd27oled_bw_fn, U8G_COM_FAST_PARALLEL);
lixianyu 0:d8f4c441e032 226
lixianyu 0:d8f4c441e032 227 uint8_t u8g_dev_ssd1325_nhd27oled_2x_bw_buf[WIDTH*2] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 228 u8g_pb_t u8g_dev_ssd1325_nhd27oled_2x_bw_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1325_nhd27oled_2x_bw_buf};
lixianyu 0:d8f4c441e032 229 u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_sw_spi = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 230 u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_hw_spi = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 231 u8g_dev_t u8g_dev_ssd1325_nhd27oled_2x_bw_parallel = { u8g_dev_ssd1325_nhd27oled_2x_bw_fn, &u8g_dev_ssd1325_nhd27oled_2x_bw_pb, U8G_COM_FAST_PARALLEL };
lixianyu 0:d8f4c441e032 232
lixianyu 0:d8f4c441e032 233