hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ssd1322_nhd31oled_gr.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ssd1322_nhd31oled_gr.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 2-Bit (4L) Driver for SSD1322 Controller (OLED Display)
lixianyu 0:d8f4c441e032 6 Tested with NHD-3.12-25664
lixianyu 0:d8f4c441e032 7
lixianyu 0:d8f4c441e032 8 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 9
lixianyu 0:d8f4c441e032 10 Copyright (c) 2012, olikraus@gmail.com
lixianyu 0:d8f4c441e032 11 All rights reserved.
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 14 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 17 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 18
lixianyu 0:d8f4c441e032 19 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 20 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 21 materials provided with the distribution.
lixianyu 0:d8f4c441e032 22
lixianyu 0:d8f4c441e032 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 24 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 25 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 26 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 27 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 28 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 29 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 31 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 32 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 33 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 35 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 36
lixianyu 0:d8f4c441e032 37 SSD130x Monochrom OLED Controller
lixianyu 0:d8f4c441e032 38 SSD131x Character OLED Controller
lixianyu 0:d8f4c441e032 39 SSD132x Graylevel OLED Controller
lixianyu 0:d8f4c441e032 40 SSD1331 Color OLED Controller
lixianyu 0:d8f4c441e032 41
lixianyu 0:d8f4c441e032 42 */
lixianyu 0:d8f4c441e032 43
lixianyu 0:d8f4c441e032 44 #include "u8g.h"
lixianyu 0:d8f4c441e032 45
lixianyu 0:d8f4c441e032 46 /* width must be multiple of 8, largest value is 248 unless u8g 16 bit mode is enabled */
lixianyu 0:d8f4c441e032 47 #if defined(U8G_16BIT)
lixianyu 0:d8f4c441e032 48 #define WIDTH 256
lixianyu 0:d8f4c441e032 49 #else
lixianyu 0:d8f4c441e032 50 #define WIDTH 248
lixianyu 0:d8f4c441e032 51 #endif
lixianyu 0:d8f4c441e032 52 #define HEIGHT 64
lixianyu 0:d8f4c441e032 53 //#define PAGE_HEIGHT 8
lixianyu 0:d8f4c441e032 54
lixianyu 0:d8f4c441e032 55 /*
lixianyu 0:d8f4c441e032 56 http://www.newhavendisplay.com/app_notes/OLED_25664.txt
lixianyu 0:d8f4c441e032 57 http://www.newhavendisplay.com/forum/viewtopic.php?f=15&t=3758
lixianyu 0:d8f4c441e032 58 */
lixianyu 0:d8f4c441e032 59
lixianyu 0:d8f4c441e032 60 static const uint8_t u8g_dev_ssd1322_2bit_nhd_312_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 61 U8G_ESC_DLY(10), /* delay 10 ms */
lixianyu 0:d8f4c441e032 62 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 63 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 64 U8G_ESC_RST(1), /* do reset low pulse with (1*16)+2 milliseconds */
lixianyu 0:d8f4c441e032 65 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 66
lixianyu 0:d8f4c441e032 67 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 68 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 69
lixianyu 0:d8f4c441e032 70 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 71 0x0fd, /* lock command */
lixianyu 0:d8f4c441e032 72 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 73 0x012, /* unlock */
lixianyu 0:d8f4c441e032 74
lixianyu 0:d8f4c441e032 75 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 76 0x0ae, /* display off, sleep mode */
lixianyu 0:d8f4c441e032 77
lixianyu 0:d8f4c441e032 78 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 79 0x0b3,
lixianyu 0:d8f4c441e032 80 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 81 0x091, /* set display clock divide ratio/oscillator frequency (set clock as 80 frames/sec) */
lixianyu 0:d8f4c441e032 82
lixianyu 0:d8f4c441e032 83 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 84 0x0ca, /* multiplex ratio */
lixianyu 0:d8f4c441e032 85 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 86 0x03f, /* 1/64 Duty (0x0F~0x3F) */
lixianyu 0:d8f4c441e032 87
lixianyu 0:d8f4c441e032 88 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 89 0x0a2,
lixianyu 0:d8f4c441e032 90 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 91 0x000, /* display offset, shift mapping ram counter */
lixianyu 0:d8f4c441e032 92
lixianyu 0:d8f4c441e032 93 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 94 0x0a1,
lixianyu 0:d8f4c441e032 95 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 96 0x000, /* display start line */
lixianyu 0:d8f4c441e032 97
lixianyu 0:d8f4c441e032 98 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 99 0x0a0, /* Set Re-Map / Dual COM Line Mode */
lixianyu 0:d8f4c441e032 100 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 101 0x014, /* was 0x014 */
lixianyu 0:d8f4c441e032 102 0x011, /* was 0x011 */
lixianyu 0:d8f4c441e032 103
lixianyu 0:d8f4c441e032 104 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 105 0x0ab,
lixianyu 0:d8f4c441e032 106 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 107 0x001, /* Enable Internal VDD Regulator */
lixianyu 0:d8f4c441e032 108
lixianyu 0:d8f4c441e032 109 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 110 0x0b4, /* Display Enhancement A */
lixianyu 0:d8f4c441e032 111 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 112 0x0a0,
lixianyu 0:d8f4c441e032 113 0x005|0x0fd,
lixianyu 0:d8f4c441e032 114
lixianyu 0:d8f4c441e032 115 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 116 0x0c1, /* contrast */
lixianyu 0:d8f4c441e032 117 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 118 0x09f,
lixianyu 0:d8f4c441e032 119
lixianyu 0:d8f4c441e032 120 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 121 0x0c7, /* Set Scale Factor of Segment Output Current Control */
lixianyu 0:d8f4c441e032 122 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 123 0x00f,
lixianyu 0:d8f4c441e032 124
lixianyu 0:d8f4c441e032 125 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 126 0x0b9, /* linear gray scale */
lixianyu 0:d8f4c441e032 127
lixianyu 0:d8f4c441e032 128 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 129 0x0b1, /* Phase 1 (Reset) & Phase 2 (Pre-Charge) Period Adjustment */
lixianyu 0:d8f4c441e032 130 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 131 0x0e2,
lixianyu 0:d8f4c441e032 132
lixianyu 0:d8f4c441e032 133 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 134 0x0d1, /* Display Enhancement B */
lixianyu 0:d8f4c441e032 135 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 136 0x082|0x020,
lixianyu 0:d8f4c441e032 137 0x020,
lixianyu 0:d8f4c441e032 138
lixianyu 0:d8f4c441e032 139 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 140 0x0bb, /* precharge voltage */
lixianyu 0:d8f4c441e032 141 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 142 0x01f,
lixianyu 0:d8f4c441e032 143
lixianyu 0:d8f4c441e032 144 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 145 0x0b6, /* precharge period */
lixianyu 0:d8f4c441e032 146 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 147 0x008,
lixianyu 0:d8f4c441e032 148
lixianyu 0:d8f4c441e032 149 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 150 0x0be, /* vcomh */
lixianyu 0:d8f4c441e032 151 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 152 0x007,
lixianyu 0:d8f4c441e032 153
lixianyu 0:d8f4c441e032 154 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 155 0x0a6, /* normal display */
lixianyu 0:d8f4c441e032 156
lixianyu 0:d8f4c441e032 157 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 158 0x0a9, /* exit partial display */
lixianyu 0:d8f4c441e032 159
lixianyu 0:d8f4c441e032 160 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 161 0x0af, /* display on */
lixianyu 0:d8f4c441e032 162
lixianyu 0:d8f4c441e032 163
lixianyu 0:d8f4c441e032 164 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 165 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 166 };
lixianyu 0:d8f4c441e032 167
lixianyu 0:d8f4c441e032 168 static const uint8_t u8g_dev_ssd1322_2bit_nhd_312_prepare_page_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 169 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 170 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 171 0x015, /* column address... */
lixianyu 0:d8f4c441e032 172 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 173 0x01c, /* start at column 0 */
lixianyu 0:d8f4c441e032 174 0x05b, /* end column */
lixianyu 0:d8f4c441e032 175 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 176 0x075, /* row address... */
lixianyu 0:d8f4c441e032 177 U8G_ESC_ADR(1), /* data mode */
lixianyu 0:d8f4c441e032 178 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 179 };
lixianyu 0:d8f4c441e032 180
lixianyu 0:d8f4c441e032 181 static void u8g_dev_ssd1322_2bit_prepare_row(u8g_t *u8g, u8g_dev_t *dev, uint8_t delta_row)
lixianyu 0:d8f4c441e032 182 {
lixianyu 0:d8f4c441e032 183 uint8_t row = ((u8g_pb_t *)(dev->dev_mem))->p.page;
lixianyu 0:d8f4c441e032 184
lixianyu 0:d8f4c441e032 185 row *= ((u8g_pb_t *)(dev->dev_mem))->p.page_height;
lixianyu 0:d8f4c441e032 186 row += delta_row;
lixianyu 0:d8f4c441e032 187
lixianyu 0:d8f4c441e032 188 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_prepare_page_seq);
lixianyu 0:d8f4c441e032 189
lixianyu 0:d8f4c441e032 190 u8g_WriteByte(u8g, dev, row); /* start at the selected row */
lixianyu 0:d8f4c441e032 191 u8g_WriteByte(u8g, dev, row+1); /* end within the selected row */
lixianyu 0:d8f4c441e032 192
lixianyu 0:d8f4c441e032 193 u8g_SetAddress(u8g, dev, 0); /* instruction mode mode */
lixianyu 0:d8f4c441e032 194 u8g_WriteByte(u8g, dev, 0x05c); /* write to ram */
lixianyu 0:d8f4c441e032 195 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 196 }
lixianyu 0:d8f4c441e032 197
lixianyu 0:d8f4c441e032 198 static const uint8_t u8g_dev_ssd13xx_sleep_on[] PROGMEM = {
lixianyu 0:d8f4c441e032 199 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 200 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 201 0x0ae, /* display off */
lixianyu 0:d8f4c441e032 202 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 203 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 204 };
lixianyu 0:d8f4c441e032 205
lixianyu 0:d8f4c441e032 206 static const uint8_t u8g_dev_ssd13xx_sleep_off[] PROGMEM = {
lixianyu 0:d8f4c441e032 207 U8G_ESC_ADR(0), /* instruction mode */
lixianyu 0:d8f4c441e032 208 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 209 0x0af, /* display on */
lixianyu 0:d8f4c441e032 210 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 211 U8G_ESC_CS(0), /* disable chip, bugfix 12 nov 2014 */
lixianyu 0:d8f4c441e032 212 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 213 };
lixianyu 0:d8f4c441e032 214
lixianyu 0:d8f4c441e032 215 uint8_t u8g_dev_ssd1322_nhd31oled_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 216 {
lixianyu 0:d8f4c441e032 217 switch(msg)
lixianyu 0:d8f4c441e032 218 {
lixianyu 0:d8f4c441e032 219 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 220 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 221 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_init_seq);
lixianyu 0:d8f4c441e032 222 break;
lixianyu 0:d8f4c441e032 223 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 224 break;
lixianyu 0:d8f4c441e032 225 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 226 {
lixianyu 0:d8f4c441e032 227 uint8_t i;
lixianyu 0:d8f4c441e032 228 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 229 uint8_t *p = pb->buf;
lixianyu 0:d8f4c441e032 230 u8g_uint_t cnt;
lixianyu 0:d8f4c441e032 231 cnt = pb->width;
lixianyu 0:d8f4c441e032 232 cnt >>= 2;
lixianyu 0:d8f4c441e032 233
lixianyu 0:d8f4c441e032 234 for( i = 0; i < pb->p.page_height; i++ )
lixianyu 0:d8f4c441e032 235 {
lixianyu 0:d8f4c441e032 236 u8g_dev_ssd1322_2bit_prepare_row(u8g, dev, i); /* this will also enable chip select */
lixianyu 0:d8f4c441e032 237 #if !defined(U8G_16BIT)
lixianyu 0:d8f4c441e032 238 u8g_WriteByte(u8g, dev, 0x00);
lixianyu 0:d8f4c441e032 239 u8g_WriteByte(u8g, dev, 0x00);
lixianyu 0:d8f4c441e032 240 #endif
lixianyu 0:d8f4c441e032 241 u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
lixianyu 0:d8f4c441e032 242 #if !defined(U8G_16BIT)
lixianyu 0:d8f4c441e032 243 u8g_WriteByte(u8g, dev, 0x00);
lixianyu 0:d8f4c441e032 244 u8g_WriteByte(u8g, dev, 0x00);
lixianyu 0:d8f4c441e032 245 #endif
lixianyu 0:d8f4c441e032 246 u8g_MicroDelay(); // for DUE?
lixianyu 0:d8f4c441e032 247 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 248 p+=cnt;
lixianyu 0:d8f4c441e032 249 }
lixianyu 0:d8f4c441e032 250 }
lixianyu 0:d8f4c441e032 251 break;
lixianyu 0:d8f4c441e032 252 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 253 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 254 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 255 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 256 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 257 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
lixianyu 0:d8f4c441e032 258 u8g_MicroDelay(); // for DUE?
lixianyu 0:d8f4c441e032 259 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 260 break;
lixianyu 0:d8f4c441e032 261 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 262 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 263 return 1;
lixianyu 0:d8f4c441e032 264 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 265 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 266 return 1;
lixianyu 0:d8f4c441e032 267 }
lixianyu 0:d8f4c441e032 268 return u8g_dev_pb8h2_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 269 }
lixianyu 0:d8f4c441e032 270
lixianyu 0:d8f4c441e032 271
lixianyu 0:d8f4c441e032 272 uint8_t u8g_dev_ssd1322_nhd31oled_2x_gr_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 273 {
lixianyu 0:d8f4c441e032 274 switch(msg)
lixianyu 0:d8f4c441e032 275 {
lixianyu 0:d8f4c441e032 276 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 277 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_300NS);
lixianyu 0:d8f4c441e032 278 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd1322_2bit_nhd_312_init_seq);
lixianyu 0:d8f4c441e032 279 break;
lixianyu 0:d8f4c441e032 280 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 281 break;
lixianyu 0:d8f4c441e032 282 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 283 {
lixianyu 0:d8f4c441e032 284 uint8_t i;
lixianyu 0:d8f4c441e032 285 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 286 uint8_t *p = pb->buf;
lixianyu 0:d8f4c441e032 287 u8g_uint_t cnt;
lixianyu 0:d8f4c441e032 288 cnt = pb->width;
lixianyu 0:d8f4c441e032 289 cnt >>= 2; /* 23 Oct 2013, changed to 2 */
lixianyu 0:d8f4c441e032 290
lixianyu 0:d8f4c441e032 291 for( i = 0; i < pb->p.page_height; i++ )
lixianyu 0:d8f4c441e032 292 {
lixianyu 0:d8f4c441e032 293 u8g_dev_ssd1322_2bit_prepare_row(u8g, dev, i); /* this will also enable chip select */
lixianyu 0:d8f4c441e032 294 #if !defined(U8G_16BIT)
lixianyu 0:d8f4c441e032 295 u8g_WriteByte(u8g, dev, 0x00);
lixianyu 0:d8f4c441e032 296 u8g_WriteByte(u8g, dev, 0x00);
lixianyu 0:d8f4c441e032 297 #endif
lixianyu 0:d8f4c441e032 298 u8g_WriteSequence4LTo16GrDevice(u8g, dev, cnt, p);
lixianyu 0:d8f4c441e032 299 #if !defined(U8G_16BIT)
lixianyu 0:d8f4c441e032 300 u8g_WriteByte(u8g, dev, 0x00);
lixianyu 0:d8f4c441e032 301 u8g_WriteByte(u8g, dev, 0x00);
lixianyu 0:d8f4c441e032 302 #endif
lixianyu 0:d8f4c441e032 303 u8g_MicroDelay(); // for DUE?
lixianyu 0:d8f4c441e032 304 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 305 p+=cnt;
lixianyu 0:d8f4c441e032 306 }
lixianyu 0:d8f4c441e032 307 }
lixianyu 0:d8f4c441e032 308 break;
lixianyu 0:d8f4c441e032 309 case U8G_DEV_MSG_CONTRAST:
lixianyu 0:d8f4c441e032 310 u8g_SetChipSelect(u8g, dev, 1);
lixianyu 0:d8f4c441e032 311 u8g_SetAddress(u8g, dev, 0); /* instruction mode */
lixianyu 0:d8f4c441e032 312 u8g_WriteByte(u8g, dev, 0x081);
lixianyu 0:d8f4c441e032 313 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 314 u8g_WriteByte(u8g, dev, (*(uint8_t *)arg) >> 1);
lixianyu 0:d8f4c441e032 315 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 316 break;
lixianyu 0:d8f4c441e032 317 case U8G_DEV_MSG_SLEEP_ON:
lixianyu 0:d8f4c441e032 318 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_on);
lixianyu 0:d8f4c441e032 319 return 1;
lixianyu 0:d8f4c441e032 320 case U8G_DEV_MSG_SLEEP_OFF:
lixianyu 0:d8f4c441e032 321 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ssd13xx_sleep_off);
lixianyu 0:d8f4c441e032 322 return 1;
lixianyu 0:d8f4c441e032 323 }
lixianyu 0:d8f4c441e032 324 return u8g_dev_pb16h2_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 325 }
lixianyu 0:d8f4c441e032 326
lixianyu 0:d8f4c441e032 327
lixianyu 0:d8f4c441e032 328 U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_sw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_SW_SPI);
lixianyu 0:d8f4c441e032 329 U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_hw_spi , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_HW_SPI);
lixianyu 0:d8f4c441e032 330 U8G_PB_DEV(u8g_dev_ssd1322_nhd31oled_gr_parallel , WIDTH, HEIGHT, 4, u8g_dev_ssd1322_nhd31oled_gr_fn, U8G_COM_FAST_PARALLEL);
lixianyu 0:d8f4c441e032 331
lixianyu 0:d8f4c441e032 332
lixianyu 0:d8f4c441e032 333 #define DWIDTH (WIDTH*2)
lixianyu 0:d8f4c441e032 334 uint8_t u8g_dev_ssd1322_nhd31oled_2x_gr_buf[DWIDTH] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 335 u8g_pb_t u8g_dev_ssd1322_nhd31oled_2x_gr_pb = { {8, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_ssd1322_nhd31oled_2x_gr_buf};
lixianyu 0:d8f4c441e032 336 u8g_dev_t u8g_dev_ssd1322_nhd31oled_2x_gr_sw_spi = { u8g_dev_ssd1322_nhd31oled_2x_gr_fn, &u8g_dev_ssd1322_nhd31oled_2x_gr_pb, U8G_COM_SW_SPI };
lixianyu 0:d8f4c441e032 337 u8g_dev_t u8g_dev_ssd1322_nhd31oled_2x_gr_hw_spi = { u8g_dev_ssd1322_nhd31oled_2x_gr_fn, &u8g_dev_ssd1322_nhd31oled_2x_gr_pb, U8G_COM_HW_SPI };
lixianyu 0:d8f4c441e032 338
lixianyu 0:d8f4c441e032 339