hadif azli / Mbed 2 deprecated TEST123

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Dependencies:   mbed Blynk

u8glibARM/u8g_dev_ili9325d_320x240.c@1:0e75de2a5d21, 2016-06-13 (annotated)

Committer:
lixianyu
Date:
Mon Jun 13 02:21:11 2016 +0000
Revision:
1:0e75de2a5d21
Parent:
0:d8f4c441e032 
u8glib???????????????????????????Adafruit_GFX????OLED????????bitmap??????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lixianyu 0:d8f4c441e032 1 /*
lixianyu 0:d8f4c441e032 2
lixianyu 0:d8f4c441e032 3 u8g_dev_ili9325d_320x240.c
lixianyu 0:d8f4c441e032 4
lixianyu 0:d8f4c441e032 5 Universal 8bit Graphics Library
lixianyu 0:d8f4c441e032 6
lixianyu 0:d8f4c441e032 7 Copyright (c) 2011, olikraus@gmail.com
lixianyu 0:d8f4c441e032 8 All rights reserved.
lixianyu 0:d8f4c441e032 9
lixianyu 0:d8f4c441e032 10 Redistribution and use in source and binary forms, with or without modification,
lixianyu 0:d8f4c441e032 11 are permitted provided that the following conditions are met:
lixianyu 0:d8f4c441e032 12
lixianyu 0:d8f4c441e032 13 * Redistributions of source code must retain the above copyright notice, this list
lixianyu 0:d8f4c441e032 14 of conditions and the following disclaimer.
lixianyu 0:d8f4c441e032 15
lixianyu 0:d8f4c441e032 16 * Redistributions in binary form must reproduce the above copyright notice, this
lixianyu 0:d8f4c441e032 17 list of conditions and the following disclaimer in the documentation and/or other
lixianyu 0:d8f4c441e032 18 materials provided with the distribution.
lixianyu 0:d8f4c441e032 19
lixianyu 0:d8f4c441e032 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
lixianyu 0:d8f4c441e032 21 CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
lixianyu 0:d8f4c441e032 22 INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
lixianyu 0:d8f4c441e032 23 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
lixianyu 0:d8f4c441e032 24 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
lixianyu 0:d8f4c441e032 25 CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
lixianyu 0:d8f4c441e032 26 SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
lixianyu 0:d8f4c441e032 27 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
lixianyu 0:d8f4c441e032 28 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
lixianyu 0:d8f4c441e032 29 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
lixianyu 0:d8f4c441e032 30 STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
lixianyu 0:d8f4c441e032 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
lixianyu 0:d8f4c441e032 32 ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
lixianyu 0:d8f4c441e032 33
lixianyu 0:d8f4c441e032 34 Color format
lixianyu 0:d8f4c441e032 35 Red: 5 Bit
lixianyu 0:d8f4c441e032 36 Green: 6 Bit
lixianyu 0:d8f4c441e032 37 Blue: 5 Bit
lixianyu 0:d8f4c441e032 38
lixianyu 0:d8f4c441e032 39
lixianyu 0:d8f4c441e032 40 */
lixianyu 0:d8f4c441e032 41
lixianyu 0:d8f4c441e032 42 #include "u8g.h"
lixianyu 0:d8f4c441e032 43 #if defined(ARDUINO) && defined(PORTD)
lixianyu 0:d8f4c441e032 44 #define WIDTH 240
lixianyu 0:d8f4c441e032 45
lixianyu 0:d8f4c441e032 46 #if defined(U8G_16BIT)
lixianyu 0:d8f4c441e032 47 #define HEIGHT 320
lixianyu 0:d8f4c441e032 48 #else
lixianyu 0:d8f4c441e032 49 /* if the user tries to compile the 8Bit version of the lib, then restrict the height to something which fits to 8Bit */
lixianyu 0:d8f4c441e032 50 #define HEIGHT 240
lixianyu 0:d8f4c441e032 51 #endif
lixianyu 0:d8f4c441e032 52 #define PAGE_HEIGHT 4
lixianyu 0:d8f4c441e032 53
lixianyu 0:d8f4c441e032 54
lixianyu 0:d8f4c441e032 55 /*
lixianyu 0:d8f4c441e032 56 reference board for this device:
lixianyu 0:d8f4c441e032 57 http://iteadstudio.com/store/index.php?main_page=product_info&cPath=57_58&products_id=55
lixianyu 0:d8f4c441e032 58 documentation:
lixianyu 0:d8f4c441e032 59 http://iteadstudio.com/Downloadfile/ITDB02_material.rar
lixianyu 0:d8f4c441e032 60 datasheet
lixianyu 0:d8f4c441e032 61 http://www.newhavendisplay.com/app_notes/ILI9325D.pdf
lixianyu 0:d8f4c441e032 62 other libs
lixianyu 0:d8f4c441e032 63 http://henningkarlsen.com/electronics/library.php
lixianyu 0:d8f4c441e032 64 init sequence
lixianyu 0:d8f4c441e032 65 http://code.google.com/p/itdb02/, ITDB02.cpp, iteadstudio.com
lixianyu 0:d8f4c441e032 66 */
lixianyu 0:d8f4c441e032 67
lixianyu 0:d8f4c441e032 68 static const uint8_t u8g_dev_ili9325d_320x240_init_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 69 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 70 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 71 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
lixianyu 0:d8f4c441e032 72 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 73 U8G_ESC_RST(15), /* do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
lixianyu 0:d8f4c441e032 74 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 75 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 76 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 77
lixianyu 0:d8f4c441e032 78
lixianyu 0:d8f4c441e032 79 //U8G_ESC_ADR(0), 0x000, 0x0E5, /* only used for none D version: set SRAM internal timing */
lixianyu 0:d8f4c441e032 80 //U8G_ESC_ADR(1), 0x078, 0x0f0,
lixianyu 0:d8f4c441e032 81 U8G_ESC_ADR(0), 0x000, 0x001, /* Driver Output Control, bits 8 & 10 */
lixianyu 0:d8f4c441e032 82 U8G_ESC_ADR(1), 0x001, 0x000,
lixianyu 0:d8f4c441e032 83 U8G_ESC_ADR(0), 0x000, 0x002, /* LCD Driving Wave Control, bit 9: Set line inversion */
lixianyu 0:d8f4c441e032 84 U8G_ESC_ADR(1), 0x002, 0x000, /* ITDB02 none D verion: 0x007, 0x000 */
lixianyu 0:d8f4c441e032 85 U8G_ESC_ADR(0), 0x000, 0x003, /* Entry Mode, GRAM write direction and BGR=1 */
lixianyu 0:d8f4c441e032 86 U8G_ESC_ADR(1), 0x010, 0x030,
lixianyu 0:d8f4c441e032 87 U8G_ESC_ADR(0), 0x000, 0x004, /* Resize register */
lixianyu 0:d8f4c441e032 88 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 89 U8G_ESC_ADR(0), 0x000, 0x008, /* Display Control 2: set the back porch and front porch */
lixianyu 0:d8f4c441e032 90 U8G_ESC_ADR(1), 0x002, 0x007,
lixianyu 0:d8f4c441e032 91
lixianyu 0:d8f4c441e032 92 U8G_ESC_ADR(0), 0x000, 0x009, /* Display Control 3 */
lixianyu 0:d8f4c441e032 93 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 94
lixianyu 0:d8f4c441e032 95 U8G_ESC_ADR(0), 0x000, 0x00a, /* Display Control 4: FMARK */
lixianyu 0:d8f4c441e032 96 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 97 U8G_ESC_ADR(0), 0x000, 0x00c, /* RGB Display Interface Control 1 */
lixianyu 0:d8f4c441e032 98 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 99 U8G_ESC_ADR(0), 0x000, 0x00d, /* Frame Maker Position */
lixianyu 0:d8f4c441e032 100 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 101 U8G_ESC_ADR(0), 0x000, 0x00f, /* RGB Display Interface Control 2 */
lixianyu 0:d8f4c441e032 102 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 103 U8G_ESC_ADR(0), 0x000, 0x010, /* Power Control 1: SAP, BT[3:0], AP, DSTB, SLP, STB */
lixianyu 0:d8f4c441e032 104 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 105 U8G_ESC_ADR(0), 0x000, 0x011, /* Power Control 2: DC1[2:0], DC0[2:0], VC[2:0] */
lixianyu 0:d8f4c441e032 106 U8G_ESC_ADR(1), 0x000, 0x007,
lixianyu 0:d8f4c441e032 107 U8G_ESC_ADR(0), 0x000, 0x012, /* Power Control 3: VREG1OUT voltage */
lixianyu 0:d8f4c441e032 108 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 109 U8G_ESC_ADR(0), 0x000, 0x013, /* Power Control 4: VDV[4:0] for VCOM amplitude */
lixianyu 0:d8f4c441e032 110 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 111 U8G_ESC_ADR(0), 0x000, 0x007, /* Display Control 1: Operate, but do not display */
lixianyu 0:d8f4c441e032 112 U8G_ESC_ADR(1), 0x000, 0x001,
lixianyu 0:d8f4c441e032 113
lixianyu 0:d8f4c441e032 114 U8G_ESC_DLY(100), /* delay 100 ms */ /* ITDB02 none D verion: 50ms */
lixianyu 0:d8f4c441e032 115 U8G_ESC_DLY(100), /* delay 100 ms */
lixianyu 0:d8f4c441e032 116
lixianyu 0:d8f4c441e032 117 U8G_ESC_ADR(0), 0x000, 0x010, /* Power Control 1: SAP, BT[3:0], AP, DSTB, SLP, STB */
lixianyu 0:d8f4c441e032 118 U8G_ESC_ADR(1), 0x016, 0x090, /* ITDB02 none D verion: 0x010, 0x090 */
lixianyu 0:d8f4c441e032 119 U8G_ESC_ADR(0), 0x000, 0x011, /* Power Control 2: SAP, BT[3:0], AP, DSTB, SLP, STB */
lixianyu 0:d8f4c441e032 120 U8G_ESC_ADR(1), 0x002, 0x027,
lixianyu 0:d8f4c441e032 121
lixianyu 0:d8f4c441e032 122 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 123
lixianyu 0:d8f4c441e032 124 U8G_ESC_ADR(0), 0x000, 0x012, /* Power Control 3: VCI: External, VCI*1.80 */
lixianyu 0:d8f4c441e032 125 U8G_ESC_ADR(1), 0x000, 0x00d, /* ITDB02 none D verion: 0x000, 0x01f */
lixianyu 0:d8f4c441e032 126
lixianyu 0:d8f4c441e032 127 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 128
lixianyu 0:d8f4c441e032 129 U8G_ESC_ADR(0), 0x000, 0x013, /* Power Control 4: VDV[4:0] for VCOM amplitude */
lixianyu 0:d8f4c441e032 130 U8G_ESC_ADR(1), 0x012, 0x000, /* ITDB02 none D verion: 0x015, 0x000 */
lixianyu 0:d8f4c441e032 131 U8G_ESC_ADR(0), 0x000, 0x029, /* Power Control 7 */
lixianyu 0:d8f4c441e032 132 U8G_ESC_ADR(1), 0x000, 0x00a, /* ITDB02 none D verion: 0x000, 0x027 */
lixianyu 0:d8f4c441e032 133 U8G_ESC_ADR(0), 0x000, 0x02b, /* Frame Rate: 83 */
lixianyu 0:d8f4c441e032 134 U8G_ESC_ADR(1), 0x000, 0x00d,
lixianyu 0:d8f4c441e032 135
lixianyu 0:d8f4c441e032 136 U8G_ESC_DLY(50), /* delay 50 ms */
lixianyu 0:d8f4c441e032 137
lixianyu 0:d8f4c441e032 138 U8G_ESC_ADR(0), 0x000, 0x020, /* Horizontal GRAM Address Set */
lixianyu 0:d8f4c441e032 139 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 140 U8G_ESC_ADR(0), 0x000, 0x021, /* Vertical GRAM Address Set */
lixianyu 0:d8f4c441e032 141 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 142
lixianyu 0:d8f4c441e032 143 /* gamma control */
lixianyu 0:d8f4c441e032 144 U8G_ESC_ADR(0), 0x000, 0x030,
lixianyu 0:d8f4c441e032 145 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 146 U8G_ESC_ADR(0), 0x000, 0x031,
lixianyu 0:d8f4c441e032 147 U8G_ESC_ADR(1), 0x004, 0x004,
lixianyu 0:d8f4c441e032 148 U8G_ESC_ADR(0), 0x000, 0x032,
lixianyu 0:d8f4c441e032 149 U8G_ESC_ADR(1), 0x000, 0x003,
lixianyu 0:d8f4c441e032 150 U8G_ESC_ADR(0), 0x000, 0x035,
lixianyu 0:d8f4c441e032 151 U8G_ESC_ADR(1), 0x004, 0x005,
lixianyu 0:d8f4c441e032 152 U8G_ESC_ADR(0), 0x000, 0x036,
lixianyu 0:d8f4c441e032 153 U8G_ESC_ADR(1), 0x008, 0x008,
lixianyu 0:d8f4c441e032 154 U8G_ESC_ADR(0), 0x000, 0x037,
lixianyu 0:d8f4c441e032 155 U8G_ESC_ADR(1), 0x004, 0x007,
lixianyu 0:d8f4c441e032 156 U8G_ESC_ADR(0), 0x000, 0x038,
lixianyu 0:d8f4c441e032 157 U8G_ESC_ADR(1), 0x003, 0x003,
lixianyu 0:d8f4c441e032 158 U8G_ESC_ADR(0), 0x000, 0x039,
lixianyu 0:d8f4c441e032 159 U8G_ESC_ADR(1), 0x007, 0x007,
lixianyu 0:d8f4c441e032 160 U8G_ESC_ADR(0), 0x000, 0x03c,
lixianyu 0:d8f4c441e032 161 U8G_ESC_ADR(1), 0x005, 0x004,
lixianyu 0:d8f4c441e032 162 U8G_ESC_ADR(0), 0x000, 0x03d,
lixianyu 0:d8f4c441e032 163 U8G_ESC_ADR(1), 0x008, 0x008,
lixianyu 0:d8f4c441e032 164
lixianyu 0:d8f4c441e032 165 U8G_ESC_ADR(0), 0x000, 0x050, /* Horizontal GRAM Start Address */
lixianyu 0:d8f4c441e032 166 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 167 U8G_ESC_ADR(0), 0x000, 0x051, /* Horizontal GRAM End Address: 239 */
lixianyu 0:d8f4c441e032 168 U8G_ESC_ADR(1), 0x000, 0x0EF,
lixianyu 0:d8f4c441e032 169 U8G_ESC_ADR(0), 0x000, 0x052, /* Vertical GRAM Start Address */
lixianyu 0:d8f4c441e032 170 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 171 U8G_ESC_ADR(0), 0x000, 0x053, /* Vertical GRAM End Address: 319 */
lixianyu 0:d8f4c441e032 172 U8G_ESC_ADR(1), 0x001, 0x03F,
lixianyu 0:d8f4c441e032 173
lixianyu 0:d8f4c441e032 174 U8G_ESC_ADR(0), 0x000, 0x060, /* Driver Output Control 2 */
lixianyu 0:d8f4c441e032 175 U8G_ESC_ADR(1), 0x0a7, 0x000,
lixianyu 0:d8f4c441e032 176 U8G_ESC_ADR(0), 0x000, 0x061, /* Base Image Display Control: NDL,VLE, REV */
lixianyu 0:d8f4c441e032 177 U8G_ESC_ADR(1), 0x000, 0x001,
lixianyu 0:d8f4c441e032 178 U8G_ESC_ADR(0), 0x000, 0x06a, /* Vertical Scroll Control */
lixianyu 0:d8f4c441e032 179 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 180
lixianyu 0:d8f4c441e032 181 U8G_ESC_ADR(0), 0x000, 0x080, /* Partial Image 1 Display Position */
lixianyu 0:d8f4c441e032 182 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 183 U8G_ESC_ADR(0), 0x000, 0x081, /* Partial Image 1 RAM Start Address */
lixianyu 0:d8f4c441e032 184 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 185 U8G_ESC_ADR(0), 0x000, 0x082, /* Partial Image 1 RAM End Address */
lixianyu 0:d8f4c441e032 186 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 187 U8G_ESC_ADR(0), 0x000, 0x083, /* Partial Image 2 Display Position */
lixianyu 0:d8f4c441e032 188 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 189 U8G_ESC_ADR(0), 0x000, 0x084, /* Partial Image 2 RAM Start Address */
lixianyu 0:d8f4c441e032 190 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 191 U8G_ESC_ADR(0), 0x000, 0x085, /* Partial Image 2 RAM End Address */
lixianyu 0:d8f4c441e032 192 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 193
lixianyu 0:d8f4c441e032 194 U8G_ESC_ADR(0), 0x000, 0x090, /* Panel Interface Control 1 */
lixianyu 0:d8f4c441e032 195 U8G_ESC_ADR(1), 0x000, 0x010,
lixianyu 0:d8f4c441e032 196 U8G_ESC_ADR(0), 0x000, 0x092, /* Panel Interface Control 2 */
lixianyu 0:d8f4c441e032 197 U8G_ESC_ADR(1), 0x000, 0x000, /* 0x006, 0x000 */
lixianyu 0:d8f4c441e032 198
lixianyu 0:d8f4c441e032 199 U8G_ESC_ADR(0), 0x000, 0x007, /* Display Control 1: Operate, display ON */
lixianyu 0:d8f4c441e032 200 U8G_ESC_ADR(1), 0x001, 0x033,
lixianyu 0:d8f4c441e032 201
lixianyu 0:d8f4c441e032 202 U8G_ESC_DLY(10), /* delay 10 ms */
lixianyu 0:d8f4c441e032 203
lixianyu 0:d8f4c441e032 204 /* write test pattern */
lixianyu 0:d8f4c441e032 205 U8G_ESC_ADR(0), 0x000, 0x020, /* Horizontal GRAM Address Set */
lixianyu 0:d8f4c441e032 206 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 207 U8G_ESC_ADR(0), 0x000, 0x021, /* Vertical GRAM Address Set */
lixianyu 0:d8f4c441e032 208 U8G_ESC_ADR(1), 0x000, 0x010,
lixianyu 0:d8f4c441e032 209 U8G_ESC_ADR(0), 0x000, 0x022, /* Write Data to GRAM */
lixianyu 0:d8f4c441e032 210 U8G_ESC_ADR(1), 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 211 0x000, 0x000,
lixianyu 0:d8f4c441e032 212 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 213 0x000, 0x000,
lixianyu 0:d8f4c441e032 214 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 215 0x000, 0x000,
lixianyu 0:d8f4c441e032 216 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 217 0x000, 0x000,
lixianyu 0:d8f4c441e032 218 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 219 0x000, 0x000,
lixianyu 0:d8f4c441e032 220 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 221 0x000, 0x000,
lixianyu 0:d8f4c441e032 222 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 223 0x000, 0x000,
lixianyu 0:d8f4c441e032 224 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 225 0x000, 0x000,
lixianyu 0:d8f4c441e032 226 0x0fe, 0x0fe,
lixianyu 0:d8f4c441e032 227
lixianyu 0:d8f4c441e032 228 U8G_ESC_CS(0), /* disable chip */
lixianyu 0:d8f4c441e032 229 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 230 };
lixianyu 0:d8f4c441e032 231
lixianyu 0:d8f4c441e032 232
lixianyu 0:d8f4c441e032 233 static const uint8_t u8g_dev_ili9325d_320x240_page_seq[] PROGMEM = {
lixianyu 0:d8f4c441e032 234 U8G_ESC_CS(1), /* enable chip */
lixianyu 0:d8f4c441e032 235 U8G_ESC_ADR(0), 0x000, 0x020, /* Horizontal GRAM Address Set */
lixianyu 0:d8f4c441e032 236 U8G_ESC_ADR(1), 0x000, 0x000,
lixianyu 0:d8f4c441e032 237 U8G_ESC_ADR(0), 0x000, 0x021, /* Vertical GRAM Address Set */
lixianyu 0:d8f4c441e032 238 U8G_ESC_ADR(1),
lixianyu 0:d8f4c441e032 239 U8G_ESC_END /* end of sequence */
lixianyu 0:d8f4c441e032 240 };
lixianyu 0:d8f4c441e032 241
lixianyu 0:d8f4c441e032 242 /* convert the internal RGB 332 to 65K high byte */
lixianyu 0:d8f4c441e032 243 static uint8_t u8g_dev_ili9325d_get_65K_high_byte(uint8_t color)
lixianyu 0:d8f4c441e032 244 {
lixianyu 0:d8f4c441e032 245 uint8_t h;
lixianyu 0:d8f4c441e032 246 h = color;
lixianyu 0:d8f4c441e032 247 h &= 0x0e0;
lixianyu 0:d8f4c441e032 248 h |= h>>3;
lixianyu 0:d8f4c441e032 249 h &= 0x0f8;
lixianyu 0:d8f4c441e032 250 color>>=2;
lixianyu 0:d8f4c441e032 251 color &= 7;
lixianyu 0:d8f4c441e032 252 h |= color;
lixianyu 0:d8f4c441e032 253 return h;
lixianyu 0:d8f4c441e032 254 }
lixianyu 0:d8f4c441e032 255
lixianyu 0:d8f4c441e032 256 /* convert the internal RGB 332 to 65K high byte */
lixianyu 0:d8f4c441e032 257 static uint8_t u8g_dev_ili9325d_get_65K_low_byte(uint8_t color)
lixianyu 0:d8f4c441e032 258 {
lixianyu 0:d8f4c441e032 259 uint8_t l;
lixianyu 0:d8f4c441e032 260 l = color;
lixianyu 0:d8f4c441e032 261 l <<= 3;
lixianyu 0:d8f4c441e032 262 color &= 3;
lixianyu 0:d8f4c441e032 263 color <<= 1;
lixianyu 0:d8f4c441e032 264 l |= color;
lixianyu 0:d8f4c441e032 265 return l;
lixianyu 0:d8f4c441e032 266 }
lixianyu 0:d8f4c441e032 267
lixianyu 0:d8f4c441e032 268
lixianyu 0:d8f4c441e032 269 uint8_t u8g_dev_ili9325d_320x240_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg)
lixianyu 0:d8f4c441e032 270 {
lixianyu 0:d8f4c441e032 271
lixianyu 0:d8f4c441e032 272 switch(msg)
lixianyu 0:d8f4c441e032 273 {
lixianyu 0:d8f4c441e032 274 case U8G_DEV_MSG_INIT:
lixianyu 0:d8f4c441e032 275 u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_50NS);
lixianyu 0:d8f4c441e032 276 //for(;;)
lixianyu 0:d8f4c441e032 277 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ili9325d_320x240_init_seq);
lixianyu 0:d8f4c441e032 278
lixianyu 0:d8f4c441e032 279 break;
lixianyu 0:d8f4c441e032 280 case U8G_DEV_MSG_STOP:
lixianyu 0:d8f4c441e032 281 break;
lixianyu 0:d8f4c441e032 282 case U8G_DEV_MSG_PAGE_NEXT:
lixianyu 0:d8f4c441e032 283 {
lixianyu 0:d8f4c441e032 284 uint8_t i;
lixianyu 0:d8f4c441e032 285 uint16_t y, j;
lixianyu 0:d8f4c441e032 286 uint8_t *ptr;
lixianyu 0:d8f4c441e032 287 u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
lixianyu 0:d8f4c441e032 288
lixianyu 0:d8f4c441e032 289 y = pb->p.page_y0;
lixianyu 0:d8f4c441e032 290 ptr = pb->buf;
lixianyu 0:d8f4c441e032 291 for( i = 0; i < pb->p.page_height; i ++ )
lixianyu 0:d8f4c441e032 292 {
lixianyu 0:d8f4c441e032 293 u8g_WriteEscSeqP(u8g, dev, u8g_dev_ili9325d_320x240_page_seq);
lixianyu 0:d8f4c441e032 294 u8g_WriteByte(u8g, dev, y >> 8 ); /* display ram (cursor) address high byte */
lixianyu 0:d8f4c441e032 295 u8g_WriteByte(u8g, dev, y & 255 ); /* display ram (cursor) address low byte */
lixianyu 0:d8f4c441e032 296
lixianyu 0:d8f4c441e032 297 u8g_SetAddress(u8g, dev, 0); /* cmd mode */
lixianyu 0:d8f4c441e032 298 u8g_WriteByte(u8g, dev, 0 );
lixianyu 0:d8f4c441e032 299 u8g_WriteByte(u8g, dev, 0x022 ); /* start gram data */
lixianyu 0:d8f4c441e032 300
lixianyu 0:d8f4c441e032 301 u8g_SetAddress(u8g, dev, 1); /* data mode */
lixianyu 0:d8f4c441e032 302
lixianyu 0:d8f4c441e032 303 for( j = 0; j < pb->width; j++ )
lixianyu 0:d8f4c441e032 304 {
lixianyu 0:d8f4c441e032 305 u8g_WriteByte(u8g, dev, u8g_dev_ili9325d_get_65K_high_byte(*ptr) );
lixianyu 0:d8f4c441e032 306 u8g_WriteByte(u8g, dev, u8g_dev_ili9325d_get_65K_low_byte(*ptr) );
lixianyu 0:d8f4c441e032 307
lixianyu 0:d8f4c441e032 308 ptr++;
lixianyu 0:d8f4c441e032 309 }
lixianyu 0:d8f4c441e032 310 y++;
lixianyu 0:d8f4c441e032 311 }
lixianyu 0:d8f4c441e032 312 u8g_SetChipSelect(u8g, dev, 0);
lixianyu 0:d8f4c441e032 313 }
lixianyu 0:d8f4c441e032 314 break;
lixianyu 0:d8f4c441e032 315 }
lixianyu 0:d8f4c441e032 316 return u8g_dev_pb8h8_base_fn(u8g, dev, msg, arg);
lixianyu 0:d8f4c441e032 317 }
lixianyu 0:d8f4c441e032 318
lixianyu 0:d8f4c441e032 319 uint8_t u8g_ili9325d_320x240_8h8_buf[WIDTH*PAGE_HEIGHT] U8G_NOCOMMON ;
lixianyu 0:d8f4c441e032 320 u8g_pb_t u8g_ili9325d_320x240_8h8_pb U8G_NOCOMMON = { {PAGE_HEIGHT, HEIGHT, 0, 0, 0}, WIDTH, u8g_ili9325d_320x240_8h8_buf};
lixianyu 0:d8f4c441e032 321 u8g_dev_t u8g_dev_ili9325d_320x240_8bit U8G_NOCOMMON = { u8g_dev_ili9325d_320x240_fn, &u8g_ili9325d_320x240_8h8_pb, u8g_com_arduino_port_d_wr_fn };
lixianyu 0:d8f4c441e032 322 //u8g_dev_t u8g_dev_ili9325d_320x240_8bit = { u8g_dev_ili9325d_320x240_fn, &u8g_ili9325d_320x240_8h8_pb, u8g_com_arduino_parallel_fn };
lixianyu 0:d8f4c441e032 323
lixianyu 0:d8f4c441e032 324 //U8G_PB_DEV(u8g_dev_ili9325d_320x240_8bit, WIDTH, HEIGHT, PAGE_HEIGHT, u8g_dev_ili9325d_320x240_fn, U8G_COM_PARALLEL);
lixianyu 0:d8f4c441e032 325
lixianyu 0:d8f4c441e032 326 #endif /* ARDUINO && PORTD */