Kenji Arai / Mbed 2 deprecated mbed_clock_ckeck

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Dependencies:   mbed

main.cpp@1:67ac582483f9, 2015-05-19 (annotated)

Committer:
kenjiArai
Date:
Tue May 19 12:05:25 2015 +0000
Revision:
1:67ac582483f9
Parent:
0:325fcc4dca89
Child:
2:8b82f7b0639a
Added detail information.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 0:325fcc4dca89 1 /*
kenjiArai 0:325fcc4dca89 2 * mbed Application program
kenjiArai 0:325fcc4dca89 3 * Check "System clock" frequency
kenjiArai 0:325fcc4dca89 4 *
kenjiArai 0:325fcc4dca89 5 * Copyright (c) 2015 Kenji Arai / JH1PJL
kenjiArai 0:325fcc4dca89 6 * http://www.page.sannet.ne.jp/kenjia/index.html
kenjiArai 0:325fcc4dca89 7 * http://mbed.org/users/kenjiArai/
kenjiArai 0:325fcc4dca89 8 * Created: may 18th, 2015
kenjiArai 0:325fcc4dca89 9 * Revised: may 18th, 2015
kenjiArai 0:325fcc4dca89 10 *
kenjiArai 0:325fcc4dca89 11 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
kenjiArai 0:325fcc4dca89 12 * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
kenjiArai 0:325fcc4dca89 13 * AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
kenjiArai 0:325fcc4dca89 14 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
kenjiArai 0:325fcc4dca89 15 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
kenjiArai 0:325fcc4dca89 16 */
kenjiArai 0:325fcc4dca89 17
kenjiArai 0:325fcc4dca89 18 #include "mbed.h"
kenjiArai 0:325fcc4dca89 19
kenjiArai 0:325fcc4dca89 20 DigitalOut myled(LED1);
kenjiArai 0:325fcc4dca89 21
kenjiArai 1:67ac582483f9 22 void put_rn(void);
kenjiArai 1:67ac582483f9 23 void detail_info_if_available(void);
kenjiArai 1:67ac582483f9 24
kenjiArai 1:67ac582483f9 25 int main()
kenjiArai 1:67ac582483f9 26 {
kenjiArai 1:67ac582483f9 27 put_rn();
kenjiArai 1:67ac582483f9 28 printf("Your mbed SysClock is %u Hz.", SystemCoreClock);
kenjiArai 1:67ac582483f9 29 put_rn();
kenjiArai 1:67ac582483f9 30 put_rn();
kenjiArai 1:67ac582483f9 31 detail_info_if_available();
kenjiArai 0:325fcc4dca89 32 while(true) {
kenjiArai 0:325fcc4dca89 33 myled = !myled;
kenjiArai 0:325fcc4dca89 34 wait(1.0);
kenjiArai 0:325fcc4dca89 35 }
kenjiArai 0:325fcc4dca89 36 }
kenjiArai 0:325fcc4dca89 37
kenjiArai 1:67ac582483f9 38 /* measured by JH1PJL on May 18th & 19th, 2015
kenjiArai 0:325fcc4dca89 39
kenjiArai 0:325fcc4dca89 40 Check old revision
kenjiArai 1:67ac582483f9 41 Case L152 (C-01 old ver with internal RC clock)
kenjiArai 1:67ac582483f9 42 before and rev.81 20140319 -> 16000000Hz
kenjiArai 1:67ac582483f9 43 rev.82 and after 20140407 -> 32000000Hz
kenjiArai 1:67ac582483f9 44 Case L152 (C-02 new ver)
kenjiArai 0:325fcc4dca89 45 before and rev.81 20140319 -> 16000000Hz
kenjiArai 0:325fcc4dca89 46 rev.82 and after 20140407 -> 24000000Hz
kenjiArai 0:325fcc4dca89 47 Case F401
kenjiArai 0:325fcc4dca89 48 all rev.(?) -> 84000000Hz
kenjiArai 0:325fcc4dca89 49 Case F411
kenjiArai 0:325fcc4dca89 50 befoe and rev.97 20150414 -> 100000000Hz
kenjiArai 0:325fcc4dca89 51 rev.98& 99 (as of 20150518) -> 96000000Hz
kenjiArai 0:325fcc4dca89 52 Case LPC1768
kenjiArai 0:325fcc4dca89 53 rev.99 -> 96000000Hz
kenjiArai 0:325fcc4dca89 54 Case GR-PEACH
kenjiArai 0:325fcc4dca89 55 error "SystemCoreClock" is undefined
kenjiArai 0:325fcc4dca89 56 Case LPC1114FN28
kenjiArai 0:325fcc4dca89 57 rev.99 -> 48000000Hz
kenjiArai 1:67ac582483f9 58 Case FRDM-K64F
kenjiArai 1:67ac582483f9 59 rev.99 -> 120000000Hz
kenjiArai 1:67ac582483f9 60 */
kenjiArai 0:325fcc4dca89 61
kenjiArai 1:67ac582483f9 62 /* ------ History L152RE Clock value ----------------
kenjiArai 1:67ac582483f9 63 -------------------------------------------------
kenjiArai 1:67ac582483f9 64 Ver C-02 (NEW) mbed (Rev.99)
kenjiArai 1:67ac582483f9 65 -------------------------------------------------
kenjiArai 1:67ac582483f9 66 Your mbed SysClock is 24000000 Hz.
kenjiArai 1:67ac582483f9 67 Use PLL with Mul=6, Div=2
kenjiArai 1:67ac582483f9 68 Use HSE(not Xtal but External Clock)=8000000Hz
kenjiArai 1:67ac582483f9 69 PLL freq=24000000Hz
kenjiArai 1:67ac582483f9 70 SYSCLK clock freq. =24000000Hz
kenjiArai 1:67ac582483f9 71 HCLK clock freq. =24000000Hz
kenjiArai 1:67ac582483f9 72 PCLK1 clock freq. =24000000Hz
kenjiArai 1:67ac582483f9 73 PCLK2 clock freq. =24000000Hz
kenjiArai 1:67ac582483f9 74 RTC/LCD Clock
kenjiArai 1:67ac582483f9 75 No clock
kenjiArai 1:67ac582483f9 76 -------------------------------------------------
kenjiArai 1:67ac582483f9 77 Ver C-01 (OLD) mbed (Rev.99)
kenjiArai 1:67ac582483f9 78 -------------------------------------------------
kenjiArai 1:67ac582483f9 79 Your mbed SysClock is 32000000 Hz.
kenjiArai 1:67ac582483f9 80 Use PLL with Mul=4, Div=2
kenjiArai 1:67ac582483f9 81 Use HSI(internal RC/High speed), RC=16000000Hz
kenjiArai 1:67ac582483f9 82 PLL freq=32000000Hz
kenjiArai 1:67ac582483f9 83 SYSCLK clock freq. =32000000Hz
kenjiArai 1:67ac582483f9 84 HCLK clock freq. =32000000Hz
kenjiArai 1:67ac582483f9 85 PCLK1 clock freq. =32000000Hz
kenjiArai 1:67ac582483f9 86 PCLK2 clock freq. =32000000Hz
kenjiArai 1:67ac582483f9 87 RTC/LCD Clock
kenjiArai 1:67ac582483f9 88 No clock
kenjiArai 1:67ac582483f9 89 -------------------------------------------------
kenjiArai 1:67ac582483f9 90 Ver C-02 (NEW) mbed (Rev.81)
kenjiArai 1:67ac582483f9 91 -------------------------------------------------
kenjiArai 1:67ac582483f9 92 Your mbed SysClock is 16000000 Hz.
kenjiArai 1:67ac582483f9 93 Use HSI(internal RC/High speed), freq=16000000Hz
kenjiArai 1:67ac582483f9 94 -------------------------------------------------
kenjiArai 1:67ac582483f9 95 Ver C-01 (OLD) mbed (Rev.81)
kenjiArai 1:67ac582483f9 96 -------------------------------------------------
kenjiArai 1:67ac582483f9 97 Your mbed SysClock is 16000000 Hz.
kenjiArai 1:67ac582483f9 98 Use HSI(internal RC/High speed), freq=16000000Hz
kenjiArai 0:325fcc4dca89 99 */
kenjiArai 1:67ac582483f9 100
kenjiArai 1:67ac582483f9 101 ///////////////////////////////////////////////////////////////////////////////////////////////////
kenjiArai 1:67ac582483f9 102 #if \
kenjiArai 1:67ac582483f9 103 defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE) || defined(TARGET_NUCLEO_L152RE)
kenjiArai 1:67ac582483f9 104
kenjiArai 1:67ac582483f9 105 // USB Frequency
kenjiArai 1:67ac582483f9 106 #define USB_FREQ_H 48100000
kenjiArai 1:67ac582483f9 107 #define USB_FREQ_L 47900000
kenjiArai 1:67ac582483f9 108
kenjiArai 1:67ac582483f9 109 char *const cmsg0 = "Use MSI(internal RC)";
kenjiArai 1:67ac582483f9 110 char *const cmsg1 = "freq=";
kenjiArai 1:67ac582483f9 111 char *const cmsg2 = "Use HSI(internal RC/High speed)";
kenjiArai 1:67ac582483f9 112 char *const cmsg3 = "Use HSE(External Xtal)";
kenjiArai 1:67ac582483f9 113 char *const cmsg4 = "Use PLL with";
kenjiArai 1:67ac582483f9 114 char *const cmsg5 = "??? following infromation is not valid !";
kenjiArai 1:67ac582483f9 115 char *const cmsg6 = "clock freq. =";
kenjiArai 1:67ac582483f9 116 char *const cmsg7 = "No clock";
kenjiArai 1:67ac582483f9 117 char *const cmsg8 = "Use LSE(external Xtal)=32768Hz";
kenjiArai 1:67ac582483f9 118 char *const cmsg9 = "Use LSI(internal RC/Low speed), RC=";
kenjiArai 1:67ac582483f9 119 char *const cmsg10= "Use HSE(external Xtal & prescaler)";
kenjiArai 1:67ac582483f9 120 //char *const cmsg11= "Power Control";
kenjiArai 1:67ac582483f9 121
kenjiArai 1:67ac582483f9 122 #endif
kenjiArai 1:67ac582483f9 123
kenjiArai 1:67ac582483f9 124 #if defined(TARGET_NUCLEO_F401RE) || defined(TARGET_NUCLEO_F411RE)
kenjiArai 1:67ac582483f9 125
kenjiArai 1:67ac582483f9 126
kenjiArai 1:67ac582483f9 127 void detail_info_if_available(void)
kenjiArai 1:67ac582483f9 128 {
kenjiArai 1:67ac582483f9 129 uint32_t m1 = 0, m2 = 0, m3 = 0, m4 = 0, m5 = 0;
kenjiArai 1:67ac582483f9 130
kenjiArai 1:67ac582483f9 131 m1 = RCC->CFGR & RCC_CFGR_SWS; /* Get SYSCLK source */
kenjiArai 1:67ac582483f9 132 switch (m1) {
kenjiArai 1:67ac582483f9 133 case 0x00: // HSI used as system clock
kenjiArai 1:67ac582483f9 134 printf( "%s, %s%dHz", cmsg2, cmsg1,HSI_VALUE );
kenjiArai 1:67ac582483f9 135 m2 = HSI_VALUE;
kenjiArai 1:67ac582483f9 136 break;
kenjiArai 1:67ac582483f9 137 case 0x04: // HSE used as system clock
kenjiArai 1:67ac582483f9 138 printf( "%s, %s%dHz", cmsg3, cmsg1, HSE_VALUE );
kenjiArai 1:67ac582483f9 139 m2 = HSE_VALUE;
kenjiArai 1:67ac582483f9 140 break;
kenjiArai 1:67ac582483f9 141 case 0x08: // PLL used as system clock
kenjiArai 1:67ac582483f9 142 printf("fVCO = fPLL-in x (PLLN/PLLM), fPLL-out = fVCO/PLLP, fUSB-out = fVCO/PLLQ");
kenjiArai 1:67ac582483f9 143 put_rn();
kenjiArai 1:67ac582483f9 144 m5 = (RCC->PLLCFGR >> 6) & 0x1ff; // PLLN
kenjiArai 1:67ac582483f9 145 m1 = RCC->PLLCFGR & 0x3f; // PLLM
kenjiArai 1:67ac582483f9 146 printf( "%s PLLN=%d, PLLM=%d", cmsg4, m5, m1 );
kenjiArai 1:67ac582483f9 147 put_rn();
kenjiArai 1:67ac582483f9 148 m3 = (RCC->PLLCFGR >> 22) & 0x1; // Clock source
kenjiArai 1:67ac582483f9 149 if (m3 == 0) {
kenjiArai 1:67ac582483f9 150 // HSI oscillator clock selected as PLL clock source
kenjiArai 1:67ac582483f9 151 m2 = (HSI_VALUE * (m5 / m1));
kenjiArai 1:67ac582483f9 152 printf( "%s, RC=%dHz", cmsg2, HSI_VALUE );
kenjiArai 1:67ac582483f9 153 } else {
kenjiArai 1:67ac582483f9 154 // HSE selected
kenjiArai 1:67ac582483f9 155 m2 = (((HSE_VALUE) * m5) / m1);
kenjiArai 1:67ac582483f9 156 if ((RCC->CR >> 18) & 0x01) { // check HSEBYP bit
kenjiArai 1:67ac582483f9 157 // HSE(not Xtal) selected as PLL clock source
kenjiArai 1:67ac582483f9 158 printf( "Use HSE(not Xtal but External Clock)=%dHz", HSE_VALUE );
kenjiArai 1:67ac582483f9 159 } else {
kenjiArai 1:67ac582483f9 160 // HSE(Xtal) selected as PLL clock source
kenjiArai 1:67ac582483f9 161 printf( "%s, Xtal=%dHz", cmsg3, HSE_VALUE );
kenjiArai 1:67ac582483f9 162 }
kenjiArai 1:67ac582483f9 163 }
kenjiArai 1:67ac582483f9 164 put_rn();
kenjiArai 1:67ac582483f9 165 printf("PLL/Base %s%dHz", cmsg1, m2);
kenjiArai 1:67ac582483f9 166 put_rn();
kenjiArai 1:67ac582483f9 167 m3 = (RCC->PLLCFGR >> 16) & 0x03; // PLLP
kenjiArai 1:67ac582483f9 168 switch (m3) {
kenjiArai 1:67ac582483f9 169 case 0:
kenjiArai 1:67ac582483f9 170 m3 = 2;
kenjiArai 1:67ac582483f9 171 break;
kenjiArai 1:67ac582483f9 172 case 1:
kenjiArai 1:67ac582483f9 173 m3 = 4;
kenjiArai 1:67ac582483f9 174 break;
kenjiArai 1:67ac582483f9 175 case 2:
kenjiArai 1:67ac582483f9 176 m3 = 6;
kenjiArai 1:67ac582483f9 177 break;
kenjiArai 1:67ac582483f9 178 case 3:
kenjiArai 1:67ac582483f9 179 m3 = 8;
kenjiArai 1:67ac582483f9 180 break;
kenjiArai 1:67ac582483f9 181 }
kenjiArai 1:67ac582483f9 182 m4 = (RCC->PLLCFGR >> 24) & 0x0f; // PLLQ
kenjiArai 1:67ac582483f9 183 printf("%s PLLP=%d, PLLQ=%d", cmsg4, m3, m4);
kenjiArai 1:67ac582483f9 184 put_rn();
kenjiArai 1:67ac582483f9 185 printf("PLL/System %s%dHz", cmsg1, m2/m3);
kenjiArai 1:67ac582483f9 186 put_rn();
kenjiArai 1:67ac582483f9 187 printf("PLL/USB %s%dHz", cmsg1, m2/m4);
kenjiArai 1:67ac582483f9 188 m2 = m2/m4;
kenjiArai 1:67ac582483f9 189 if ((m2 > USB_FREQ_H) || (m2 <USB_FREQ_L)) {
kenjiArai 1:67ac582483f9 190 printf(" -> USB Freq. is out of range!");
kenjiArai 1:67ac582483f9 191 }
kenjiArai 1:67ac582483f9 192 put_rn();
kenjiArai 1:67ac582483f9 193 break;
kenjiArai 1:67ac582483f9 194 default: // Not come here
kenjiArai 1:67ac582483f9 195 printf( cmsg5 );
kenjiArai 1:67ac582483f9 196 break;
kenjiArai 1:67ac582483f9 197 }
kenjiArai 1:67ac582483f9 198 put_rn();
kenjiArai 1:67ac582483f9 199 printf( "SYSCLK %s%dHz", cmsg6, HAL_RCC_GetSysClockFreq());
kenjiArai 1:67ac582483f9 200 put_rn();
kenjiArai 1:67ac582483f9 201 printf( "HCLK %s%dHz", cmsg6, HAL_RCC_GetHCLKFreq());
kenjiArai 1:67ac582483f9 202 put_rn();
kenjiArai 1:67ac582483f9 203 printf( "PCLK1 %s%dHz", cmsg6, HAL_RCC_GetPCLK1Freq());
kenjiArai 1:67ac582483f9 204 put_rn();
kenjiArai 1:67ac582483f9 205 printf( "PCLK2 %s%dHz", cmsg6, HAL_RCC_GetPCLK2Freq());
kenjiArai 1:67ac582483f9 206 put_rn();
kenjiArai 1:67ac582483f9 207 put_rn();
kenjiArai 1:67ac582483f9 208 // Check RTC Clock
kenjiArai 1:67ac582483f9 209 printf("RTC Clock");
kenjiArai 1:67ac582483f9 210 put_rn();
kenjiArai 1:67ac582483f9 211 m1 = (RCC->BDCR >> 8) & 0x03;
kenjiArai 1:67ac582483f9 212 switch (m1) {
kenjiArai 1:67ac582483f9 213 case 0: // no clock
kenjiArai 1:67ac582483f9 214 printf(cmsg7);
kenjiArai 1:67ac582483f9 215 break;
kenjiArai 1:67ac582483f9 216 case 1: // LSE
kenjiArai 1:67ac582483f9 217 printf(cmsg8);
kenjiArai 1:67ac582483f9 218 break;
kenjiArai 1:67ac582483f9 219 case 2: // LSI
kenjiArai 1:67ac582483f9 220 printf("%s 17 to 47, typ.32KHz", cmsg9);
kenjiArai 1:67ac582483f9 221 break;
kenjiArai 1:67ac582483f9 222 case 3: // HSE
kenjiArai 1:67ac582483f9 223 printf( cmsg10 );
kenjiArai 1:67ac582483f9 224 m2 = (RCC->PLLCFGR >> 16) & 0x1f; // RTCPRE
kenjiArai 1:67ac582483f9 225 m3 = HSE_VALUE / m2;
kenjiArai 1:67ac582483f9 226 printf("%s%dHz", cmsg6, m3);
kenjiArai 1:67ac582483f9 227 put_rn();
kenjiArai 1:67ac582483f9 228 break;
kenjiArai 1:67ac582483f9 229 default: // Not come here
kenjiArai 1:67ac582483f9 230 printf(cmsg5);
kenjiArai 1:67ac582483f9 231 break;
kenjiArai 1:67ac582483f9 232 }
kenjiArai 1:67ac582483f9 233 put_rn();
kenjiArai 1:67ac582483f9 234 put_rn();
kenjiArai 1:67ac582483f9 235 }
kenjiArai 1:67ac582483f9 236 #elif defined(TARGET_NUCLEO_L152RE)
kenjiArai 1:67ac582483f9 237
kenjiArai 1:67ac582483f9 238 static __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
kenjiArai 1:67ac582483f9 239
kenjiArai 1:67ac582483f9 240 void detail_info_if_available(void)
kenjiArai 1:67ac582483f9 241 {
kenjiArai 1:67ac582483f9 242 uint32_t m1, m2, m3, m4, m5;
kenjiArai 1:67ac582483f9 243
kenjiArai 1:67ac582483f9 244 m1 = RCC->CFGR & RCC_CFGR_SWS; /* Get SYSCLK source */
kenjiArai 1:67ac582483f9 245 switch (m1) {
kenjiArai 1:67ac582483f9 246 case 0x00: // MSI used as system clock
kenjiArai 1:67ac582483f9 247 m4 = ( RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> 13;
kenjiArai 1:67ac582483f9 248 m2 = (32768 * (1 << (m4 + 1)));
kenjiArai 1:67ac582483f9 249 printf( "%s, %s%dHz", cmsg0, cmsg1, m2);
kenjiArai 1:67ac582483f9 250 break;
kenjiArai 1:67ac582483f9 251 case 0x04: // HSI used as system clock
kenjiArai 1:67ac582483f9 252 printf( "%s, %s%dHz", cmsg2, cmsg1,HSI_VALUE );
kenjiArai 1:67ac582483f9 253 m2 = HSI_VALUE;
kenjiArai 1:67ac582483f9 254 break;
kenjiArai 1:67ac582483f9 255 case 0x08: // HSE used as system clock
kenjiArai 1:67ac582483f9 256 printf( "%s, %s%dHz", cmsg3, cmsg1, HSE_VALUE );
kenjiArai 1:67ac582483f9 257 m2 = HSE_VALUE;
kenjiArai 1:67ac582483f9 258 break;
kenjiArai 1:67ac582483f9 259 case 0x0C: // PLL used as system clock
kenjiArai 1:67ac582483f9 260 // Get PLL clock source and multiplication factor
kenjiArai 1:67ac582483f9 261 m5 = RCC->CFGR & RCC_CFGR_PLLMUL;
kenjiArai 1:67ac582483f9 262 m1 = RCC->CFGR & RCC_CFGR_PLLDIV;
kenjiArai 1:67ac582483f9 263 m5 = PLLMulTable[(m5 >> 18)];
kenjiArai 1:67ac582483f9 264 m1 = (m1 >> 22) + 1;
kenjiArai 1:67ac582483f9 265 printf( "%s Mul=%d, Div=%d", cmsg4, m5, m1 );
kenjiArai 1:67ac582483f9 266 put_rn();
kenjiArai 1:67ac582483f9 267 m3 = RCC->CFGR & RCC_CFGR_PLLSRC;
kenjiArai 1:67ac582483f9 268 if ( m3 == 0x00 ) {
kenjiArai 1:67ac582483f9 269 // HSI oscillator clock selected as PLL clock source
kenjiArai 1:67ac582483f9 270 m2 = (((HSI_VALUE) * m5) / m1);
kenjiArai 1:67ac582483f9 271 printf( "%s, RC=%dHz", cmsg2, HSI_VALUE );
kenjiArai 1:67ac582483f9 272 } else {
kenjiArai 1:67ac582483f9 273 // HSE selected
kenjiArai 1:67ac582483f9 274 m2 = (((HSE_VALUE) * m5) / m1);
kenjiArai 1:67ac582483f9 275 if ((RCC->CR >> 18) & 0x01) { // check HSEBYP bit
kenjiArai 1:67ac582483f9 276 // HSE(not Xtal) selected as PLL clock source
kenjiArai 1:67ac582483f9 277 printf( "Use HSE(not Xtal but External Clock)=%dHz", HSE_VALUE );
kenjiArai 1:67ac582483f9 278 } else {
kenjiArai 1:67ac582483f9 279 // HSE(Xtal) selected as PLL clock source
kenjiArai 1:67ac582483f9 280 printf( "%s, Xtal=%dHz", cmsg3, HSE_VALUE );
kenjiArai 1:67ac582483f9 281 }
kenjiArai 1:67ac582483f9 282 }
kenjiArai 1:67ac582483f9 283 put_rn();
kenjiArai 1:67ac582483f9 284 printf( "PLL %s%dHz", cmsg1, m2 );
kenjiArai 1:67ac582483f9 285 put_rn();
kenjiArai 1:67ac582483f9 286 break;
kenjiArai 1:67ac582483f9 287 default: // Not come here
kenjiArai 1:67ac582483f9 288 printf( cmsg5 );
kenjiArai 1:67ac582483f9 289 break;
kenjiArai 1:67ac582483f9 290 }
kenjiArai 1:67ac582483f9 291 put_rn();
kenjiArai 1:67ac582483f9 292 #if 1 // Nucleo L152RE does NOT support folloing function call (Please set #if 0)
kenjiArai 1:67ac582483f9 293 printf( "SYSCLK %s%dHz", cmsg6, HAL_RCC_GetSysClockFreq() );
kenjiArai 1:67ac582483f9 294 put_rn();
kenjiArai 1:67ac582483f9 295 printf( "HCLK %s%dHz", cmsg6, HAL_RCC_GetHCLKFreq() );
kenjiArai 1:67ac582483f9 296 put_rn();
kenjiArai 1:67ac582483f9 297 printf( "PCLK1 %s%dHz", cmsg6, HAL_RCC_GetPCLK1Freq() );
kenjiArai 1:67ac582483f9 298 put_rn();
kenjiArai 1:67ac582483f9 299 printf( "PCLK2 %s%dHz", cmsg6, HAL_RCC_GetPCLK2Freq() );
kenjiArai 1:67ac582483f9 300 #endif
kenjiArai 1:67ac582483f9 301 put_rn();
kenjiArai 1:67ac582483f9 302 put_rn();
kenjiArai 1:67ac582483f9 303 m1 = RCC->CSR & RCC_CSR_RTCSEL;
kenjiArai 1:67ac582483f9 304 // Check RTC & LCD Clock
kenjiArai 1:67ac582483f9 305 printf("RTC/LCD Clock");
kenjiArai 1:67ac582483f9 306 put_rn();
kenjiArai 1:67ac582483f9 307 switch (m1) {
kenjiArai 1:67ac582483f9 308 case RCC_CSR_RTCSEL_NOCLOCK:
kenjiArai 1:67ac582483f9 309 printf( cmsg7 );
kenjiArai 1:67ac582483f9 310 break;
kenjiArai 1:67ac582483f9 311 case RCC_CSR_RTCSEL_LSE:
kenjiArai 1:67ac582483f9 312 printf( cmsg8 );
kenjiArai 1:67ac582483f9 313 break;
kenjiArai 1:67ac582483f9 314 case RCC_CSR_RTCSEL_LSI:
kenjiArai 1:67ac582483f9 315 printf("%s 26 to 56, typ.38KHz", cmsg9);
kenjiArai 1:67ac582483f9 316 break;
kenjiArai 1:67ac582483f9 317 case RCC_CSR_RTCSEL_HSE:
kenjiArai 1:67ac582483f9 318 printf( cmsg10 );
kenjiArai 1:67ac582483f9 319 break;
kenjiArai 1:67ac582483f9 320 default: // Not come here
kenjiArai 1:67ac582483f9 321 printf( cmsg5 );
kenjiArai 1:67ac582483f9 322 break;
kenjiArai 1:67ac582483f9 323 }
kenjiArai 1:67ac582483f9 324 put_rn();
kenjiArai 1:67ac582483f9 325 put_rn();
kenjiArai 1:67ac582483f9 326 }
kenjiArai 1:67ac582483f9 327
kenjiArai 1:67ac582483f9 328 #elif defined(TARGET_LPC1768)
kenjiArai 1:67ac582483f9 329
kenjiArai 1:67ac582483f9 330 #define XTAL (12000000UL) // Oscillator frequency
kenjiArai 1:67ac582483f9 331 #define OSC_CLK ( XTAL) // Main oscillator frequency
kenjiArai 1:67ac582483f9 332 #define RTC_CLK ( 32000UL) // RTC oscillator frequency
kenjiArai 1:67ac582483f9 333 #define IRC_OSC ( 4000000UL) // Internal RC oscillator frequency
kenjiArai 1:67ac582483f9 334
kenjiArai 1:67ac582483f9 335 void detail_info_if_available(void)
kenjiArai 1:67ac582483f9 336 {
kenjiArai 1:67ac582483f9 337 uint32_t sys_freq = 0;
kenjiArai 1:67ac582483f9 338
kenjiArai 1:67ac582483f9 339 if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) {/* If PLL0 enabled and connected */
kenjiArai 1:67ac582483f9 340 printf("PLL0 enabled");
kenjiArai 1:67ac582483f9 341 put_rn();
kenjiArai 1:67ac582483f9 342 switch (LPC_SC->CLKSRCSEL & 0x03) {
kenjiArai 1:67ac582483f9 343 case 0: /* Internal RC oscillator => PLL0 */
kenjiArai 1:67ac582483f9 344 case 3: /* Reserved, default to Internal RC */
kenjiArai 1:67ac582483f9 345 printf("Internal RC Oscillator");
kenjiArai 1:67ac582483f9 346 put_rn();
kenjiArai 1:67ac582483f9 347 sys_freq = (IRC_OSC *
kenjiArai 1:67ac582483f9 348 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
kenjiArai 1:67ac582483f9 349 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
kenjiArai 1:67ac582483f9 350 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
kenjiArai 1:67ac582483f9 351 break;
kenjiArai 1:67ac582483f9 352 case 1: /* Main oscillator => PLL0 */
kenjiArai 1:67ac582483f9 353 printf("Xtal Osc Clock = %dHz",XTAL );
kenjiArai 1:67ac582483f9 354 put_rn();
kenjiArai 1:67ac582483f9 355 sys_freq = (OSC_CLK *
kenjiArai 1:67ac582483f9 356 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
kenjiArai 1:67ac582483f9 357 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
kenjiArai 1:67ac582483f9 358 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
kenjiArai 1:67ac582483f9 359 break;
kenjiArai 1:67ac582483f9 360 case 2: /* RTC oscillator => PLL0 */
kenjiArai 1:67ac582483f9 361 printf("RTC Xtal Oscillator f = %dHz", RTC_CLK );
kenjiArai 1:67ac582483f9 362 put_rn();
kenjiArai 1:67ac582483f9 363 sys_freq = (RTC_CLK *
kenjiArai 1:67ac582483f9 364 (((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
kenjiArai 1:67ac582483f9 365 (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1)) /
kenjiArai 1:67ac582483f9 366 ((LPC_SC->CCLKCFG & 0xFF)+ 1));
kenjiArai 1:67ac582483f9 367 break;
kenjiArai 1:67ac582483f9 368 }
kenjiArai 1:67ac582483f9 369 } else {
kenjiArai 1:67ac582483f9 370 printf("PLL0 disabled");
kenjiArai 1:67ac582483f9 371 switch (LPC_SC->CLKSRCSEL & 0x03) {
kenjiArai 1:67ac582483f9 372 case 0: /* Internal RC oscillator => PLL0 */
kenjiArai 1:67ac582483f9 373 case 3: /* Reserved, default to Internal RC */
kenjiArai 1:67ac582483f9 374 printf("Internal RC Oscillator");
kenjiArai 1:67ac582483f9 375 put_rn();
kenjiArai 1:67ac582483f9 376 sys_freq = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
kenjiArai 1:67ac582483f9 377 break;
kenjiArai 1:67ac582483f9 378 case 1: /* Main oscillator => PLL0 */
kenjiArai 1:67ac582483f9 379 printf("Xtal Osc Clock = %dHz",XTAL );
kenjiArai 1:67ac582483f9 380 put_rn();
kenjiArai 1:67ac582483f9 381 sys_freq = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
kenjiArai 1:67ac582483f9 382 break;
kenjiArai 1:67ac582483f9 383 case 2: /* RTC oscillator => PLL0 */
kenjiArai 1:67ac582483f9 384 printf("RTC Xtal Oscillator f = %dHz", RTC_CLK );
kenjiArai 1:67ac582483f9 385 put_rn();
kenjiArai 1:67ac582483f9 386 sys_freq = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
kenjiArai 1:67ac582483f9 387 break;
kenjiArai 1:67ac582483f9 388 }
kenjiArai 1:67ac582483f9 389 }
kenjiArai 1:67ac582483f9 390 printf("System Clock = %dHz", sys_freq);
kenjiArai 1:67ac582483f9 391 }
kenjiArai 1:67ac582483f9 392
kenjiArai 1:67ac582483f9 393 #else
kenjiArai 1:67ac582483f9 394
kenjiArai 1:67ac582483f9 395 void detail_info_if_available(void)
kenjiArai 1:67ac582483f9 396 {
kenjiArai 1:67ac582483f9 397 printf("Detail information -> No support");
kenjiArai 1:67ac582483f9 398 put_rn();
kenjiArai 1:67ac582483f9 399 put_rn();
kenjiArai 1:67ac582483f9 400 }
kenjiArai 1:67ac582483f9 401
kenjiArai 1:67ac582483f9 402 #endif
kenjiArai 1:67ac582483f9 403
kenjiArai 1:67ac582483f9 404 void put_rn(void)
kenjiArai 1:67ac582483f9 405 {
kenjiArai 1:67ac582483f9 406 printf("\r\n");
kenjiArai 1:67ac582483f9 407 }