s2lpReg.h

00001 /*
00002  * Copyright (c) 2018 ARM Limited. All rights reserved.
00003  * SPDX-License-Identifier: Apache-2.0
00004  * Licensed under the Apache License, Version 2.0 (the License); you may
00005  * not use this file except in compliance with the License.
00006  * You may obtain a copy of the License at
00007  *
00008  * http://www.apache.org/licenses/LICENSE-2.0
00009  *
00010  * Unless required by applicable law or agreed to in writing, software
00011  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
00012  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00013  * See the License for the specific language governing permissions and
00014  * limitations under the License.
00015  */
00016 
00017 #ifndef S2LPREG_H_
00018 #define S2LPREG_H_
00019 #ifdef __cplusplus
00020 extern "C" {
00021 #endif
00022 
00023 #define RF_MTU              2047
00024 #define PARTNUM             0x03
00025 #define VERSION             0xC1
00026 #define FIFO_SIZE           128
00027 #define SPI_HEADER_LENGTH   2
00028 #define RSSI_SETTLING_TIME  250
00029 
00030 #define S2LP_GPIO0   0
00031 #define S2LP_GPIO1   1
00032 #define S2LP_GPIO2   2
00033 #define S2LP_GPIO3   3
00034 
00035 // GPIO modes
00036 #define DIG_IN          1
00037 #define DIG_OUT_LOW     2
00038 #define DIG_OUT_HIGH    3
00039 
00040 // Interrupt events
00041 #define RX_DATA_READY           0
00042 #define RX_DATA_DISCARDED       1
00043 #define TX_DATA_SENT            2
00044 #define MAX_RE_TX               3
00045 #define CRC_ERROR               4
00046 #define TX_FIFO_UNF_OVF         5
00047 #define RX_FIFO_UNF_OVF         6
00048 #define TX_FIFO_ALMOST_FULL     7
00049 #define TX_FIFO_ALMOST_EMPTY    8
00050 #define RX_FIFO_ALMOST_FULL     9
00051 #define RX_FIFO_ALMOST_EMPTY    10
00052 #define MAX_CCA_BACKOFFS        11
00053 #define VALID_PREAMBLE          12
00054 #define SYNC_WORD               13
00055 #define RSSI_ABOVE_THR          14
00056 #define WAKE_UP_TIMEOUT         15
00057 #define READY                   16
00058 #define STANDBY_SWITCHING       17
00059 #define LOW_BATTERY_LVL         18
00060 #define POWER_ON_RESET          19
00061 #define RX_TIMER_TIMEOUT        28
00062 #define SNIFF_TIMER_TIMEOUT     29
00063 
00064 // GPIO signals
00065 #define NIRQ                                0
00066 #define POR                                 1
00067 #define WUT_EXPIRE                          2
00068 #define LOW_BATTERY                         3
00069 #define TX_DATA_OUTPUT                      4
00070 #define TX_STATE                            5
00071 #define TXRX_FIFO_ALMOST_EMPTY              6
00072 #define TXRX_FIFO_ALMOST_FULL               7
00073 #define RX_DATA_OUTPUT                      8
00074 #define RX_CLOCK_OUTPUT                     9
00075 #define RX_STATE                            10
00076 #define STATE_OTHER_THAN_SLEEP_OR_STANDBY   11
00077 #define STANDBY_STATE                       12
00078 #define ANTENNA_SWITCH                      13
00079 #define VALID_PREAMBLE_DETECTED             14
00080 #define SYNC_WORD_DETECTED                  15
00081 #define RSSI_ABOVE_THRESHOLD                16
00082 #define TXRX_MODE_INDICATOR                 18
00083 #define VDD                                 19
00084 #define GND                                 20
00085 #define SMPS_ENABLE                         21
00086 #define SLEEP_STATE                         22
00087 #define READY_STATE                         23
00088 #define LOCK_STATE                          24
00089 #define WAIT_LOCK_DETECTOR                  25
00090 #define TX_DATA_OOK                         26
00091 #define WAIT_READY                          27
00092 #define WAIT_TIMER_EXPIRATION               28
00093 #define END_OF_CALIBRATION                  29
00094 #define ENABLE_SYNTH_BLOCK                  30
00095 
00096 // RF registers
00097 #define GPIO0_CONF          0x00
00098 #define GPIO1_CONF          0x01
00099 #define GPIO2_CONF          0x02
00100 #define GPIO3_CONF          0x03
00101 #define SYNT3               0x05
00102 #define SYNT2               0x06
00103 #define SYNT1               0x07
00104 #define SYNT0               0x08
00105 #define IF_OFFSET_ANA       0x09
00106 #define IF_OFFSET_DIG       0x0A
00107 #define CHSPACE             0x0C
00108 #define CHNUM               0x0D
00109 #define MOD4                0x0E
00110 #define MOD3                0x0F
00111 #define MOD2                0x10
00112 #define MOD1                0x11
00113 #define MOD0                0x12
00114 #define CHFLT               0x13
00115 #define AFC2                0x14
00116 #define AFC1                0x15
00117 #define AFC0                0x16
00118 #define RSSI_FLT            0x17
00119 #define RSSI_TH             0x18
00120 #define AGCCTRL4            0x1A
00121 #define AGCCTRL3            0x1B
00122 #define AGCCTRL2            0x1C
00123 #define AGCCTRL1            0x1D
00124 #define AGCCTRL0            0x1E
00125 #define ANT_SELECT_CONF     0x1F
00126 #define CLOCKREC2           0x20
00127 #define CLOCKREC1           0x21
00128 #define PCKTCTRL6           0x2B
00129 #define PCKTCTRL5           0x2C
00130 #define PCKTCTRL4           0x2D
00131 #define PCKTCTRL3           0x2E
00132 #define PCKTCTRL2           0x2F
00133 #define PCKTCTRL1           0x30
00134 #define PCKTLEN1            0x31
00135 #define PCKTLEN0            0x32
00136 #define SYNC3               0x33
00137 #define SYNC2               0x34
00138 #define SYNC1               0x35
00139 #define SYNC0               0x36
00140 #define QI                  0x37
00141 #define PCKT_PSTMBL         0x38
00142 #define PROTOCOL2           0x39
00143 #define PROTOCOL1           0x3A
00144 #define PROTOCOL0           0x3B
00145 #define FIFO_CONFIG3        0x3C
00146 #define FIFO_CONFIG2        0x3D
00147 #define FIFO_CONFIG1        0x3E
00148 #define FIFO_CONFIG0        0x3F
00149 #define PCKT_FLT_OPTIONS    0x40
00150 #define PCKT_FLT_GOALS4     0x41
00151 #define PCKT_FLT_GOALS3     0x42
00152 #define PCKT_FLT_GOALS2     0x43
00153 #define PCKT_FLT_GOALS1     0x44
00154 #define PCKT_FLT_GOALS0     0x45
00155 #define TIMERS5             0x46
00156 #define TIMERS4             0x47
00157 #define TIMERS3             0x48
00158 #define TIMERS2             0x49
00159 #define TIMERS1             0x4A
00160 #define TIMERS0             0x4B
00161 #define CSMA_CONF3          0x4C
00162 #define CSMA_CONF2          0x4D
00163 #define CSMA_CONF1          0x4E
00164 #define CSMA_CONF0          0x4F
00165 #define IRQ_MASK3           0x50
00166 #define IRQ_MASK2           0x51
00167 #define IRQ_MASK1           0x52
00168 #define IRQ_MASK0           0x53
00169 #define FAST_RX_TIMER       0x54
00170 #define PA_POWER8           0x5A
00171 #define PA_POWER7           0x5B
00172 #define PA_POWER6           0x5C
00173 #define PA_POWER5           0x5D
00174 #define PA_POWER4           0x5E
00175 #define PA_POWER3           0x5F
00176 #define PA_POWER2           0x60
00177 #define PA_POWER1           0x61
00178 #define PA_POWER0           0x62
00179 #define PA_CONFIG1          0x63
00180 #define PA_CONFIG0          0x64
00181 #define SYNTH_CONFIG2       0x65
00182 #define VCO_CONFIG          0x68
00183 #define VCO_CALIBR_IN2      0x69
00184 #define VCO_CALIBR_IN1      0x6A
00185 #define VCO_CALIBR_IN0      0x6B
00186 #define XO_RCO_CONF1        0x6C
00187 #define XO_RCO_CONF0        0x6D
00188 #define RCO_CALIBR_CONF3    0x6E
00189 #define RCO_CALIBR_CONF2    0x6F
00190 #define PM_CONF4            0x75
00191 #define PM_CONF3            0x76
00192 #define PM_CONF2            0x77
00193 #define PM_CONF1            0x78
00194 #define PM_CONF0            0x79
00195 #define MC_STATE1           0x8D
00196 #define MC_STATE0           0x8E
00197 #define TX_FIFO_STATUS      0x8F
00198 #define RX_FIFO_STATUS      0x90
00199 #define RCO_CALIBR_OUT4     0x94
00200 #define RCO_CALIBR_OUT3     0x95
00201 #define VCO_CALIBR_OUT1     0x99
00202 #define VCO_CALIBR_OUT0     0x9A
00203 #define TX_PCKT_INFO        0x9C
00204 #define RX_PCKT_INFO        0x9D
00205 #define AFC_CORR            0x9E
00206 #define LINK_QUALIF2        0x9F
00207 #define LINK_QUALIF1        0xA0
00208 #define RSSI_LEVEL          0xA2
00209 #define RX_PCKT_LEN1        0xA4
00210 #define RX_PCKT_LEN0        0xA5
00211 #define CRC_FIELD3          0xA6
00212 #define CRC_FIELD2          0xA7
00213 #define CRC_FIELD1          0xA8
00214 #define CRC_FIELD0          0xA9
00215 #define RX_ADDRE_FIELD1     0xAA
00216 #define RX_ADDRE_FIELD0     0xAB
00217 #define RSSI_LEVEL_RUN      0xEF
00218 #define DEVICE_INFO1        0xF0
00219 #define DEVICE_INFO0        0xF1
00220 #define IRQ_STATUS3         0xFA
00221 #define IRQ_STATUS2         0xFB
00222 #define IRQ_STATUS1         0xFC
00223 #define IRQ_STATUS0         0xFD
00224 #define TX_FIFO             0xFF
00225 #define RX_FIFO             0xFF
00226 
00227 #define SFD0 0x90
00228 #define SFD1 0x4e
00229 
00230 #define DEFAULT_DEVIATION       125000
00231 #define RX_FILTER_BANDWIDTH     540000
00232 #define RSSI_THRESHOLD          -85
00233 
00234 // PCKTCTRL6
00235 #define PCKT_SYNCLEN_FIELD      0xFC
00236 #define PCKT_SYNCLEN            (16 << 2)
00237 
00238 // PCKTCTRL5
00239 #define PCKT_PREAMBLE_LEN       32
00240 
00241 // PCKTCTRL3
00242 #define PCKT_FORMAT_FIELD       0xC0
00243 #define PCKT_FORMAT_802_15_4    (1 << 6)
00244 #define PCKT_RXMODE_FIELD       0x30
00245 #define PCKT_RXMODE_NORMAL      (0 << 4)
00246 #define PCKT_BYTE_SWAP_FIELD    0x04
00247 #define PCKT_BYTE_SWAP_LSB      (1 << 2)
00248 
00249 // PCKTCTRL2
00250 #define PCKT_FIXVARLEN_FIELD    0x01
00251 #define PCKT_VARIABLE_LEN       (1 << 0)
00252 #define PCKT_FCS_TYPE_FIELD     0x20
00253 #define PCKT_FCS_TYPE_4_OCTET   (0 << 5)
00254 #define PCKT_FCS_TYPE_2_OCTET   (1 << 5)
00255 
00256 // PCKTCTRL1
00257 #define PCKT_CRCMODE_FIELD      0xE0
00258 #define PCKT_CRCMODE_0X1021     (3 << 5)
00259 #define PCKT_CRCMODE_0x04C11DB7 (5 << 5)
00260 #define PCKT_TXSOURCE_FIELD     0x0C
00261 #define PCKT_TXSOURCE_NORMAL    (0 << 2)
00262 #define PCKT_WHITENING_FIELD    0x10
00263 #define PCKT_WHITENING_ENABLED  (1 << 4)
00264 
00265 // MOD4
00266 #define DATARATE_M_MSB          0x47
00267 // MOD3
00268 #define DATARATE_M_LSB          0xAE
00269 
00270 // MOD2
00271 #define MOD_TYPE_FIELD          0xF0
00272 #define MOD_2FSK                (0 << 4)
00273 #define MOD_2GFSK               (10 << 4)
00274 #define DATARATE_E_FIELD        0x0F
00275 #define DATARATE_E              (10 << 0)
00276 
00277 // MOD1
00278 #define FDEV_E_FIELD            0x0F
00279 
00280 // QI
00281 #define PQI_TH_FIELD            0x1E
00282 #define PQI_TH                  (8 << 1)
00283 #define SQI_EN_FIELD            0x01
00284 #define SQI_EN                  (1 << 0)
00285 
00286 // SYNT3
00287 #define SYNT_FIELD              0x0F
00288 
00289 // CHFLT
00290 #define CHFLT_M_FIELD           0xF0
00291 #define CHFLT_E_FIELD           0x0F
00292 
00293 // LINK_QUALIF1
00294 #define CARRIER_SENSE           (1 << 7)
00295 
00296 #define SPI_WR_REG  0x00
00297 #define SPI_RD_REG  0x01
00298 #define SPI_CMD     0x80
00299 
00300 typedef enum {
00301     S2LP_STATE_STANDBY      = 0x02,
00302     S2LP_STATE_SLEEPA       = 0x01,
00303     S2LP_STATE_SLEEPB       = 0x03,
00304     S2LP_STATE_READY        = 0x00,
00305     S2LP_STATE_LOCK         = 0x0C,
00306     S2LP_STATE_RX           = 0x30,
00307     S2LP_STATE_TX           = 0x5C,
00308     S2LP_STATE_SYNTH_SETUP  = 0x50
00309 } s2lp_states_e;
00310 
00311 #if defined __cplusplus && __cplusplus >= 201103
00312 typedef enum : uint8_t {
00313 #else
00314 typedef enum {
00315 #endif
00316     S2LP_CMD_TX = 0x60,
00317     S2LP_CMD_RX,
00318     S2LP_CMD_READY,
00319     S2LP_CMD_STANDBY,
00320     S2LP_CMD_SLEEP,
00321     S2LP_CMD_LOCKRX,
00322     S2LP_CMD_LOCKTX,
00323     S2LP_CMD_SABORT,
00324     S2LP_CMD_LDC_RELOAD,
00325     S2LP_CMD_SRES = 0x70,
00326     S2LP_CMD_FLUSHRXFIFO,
00327     S2LP_CMD_FLUSHTXFIFO,
00328     S2LP_CMD_SEQUPDATE
00329 } s2lp_commands_e;
00330 
00331 typedef enum {
00332     RF_IDLE,
00333     RF_CSMA_STARTED,
00334     RF_TX_STARTED,
00335     RF_RX_STARTED,
00336     RF_TX_ACK
00337 } rf_states_e;
00338 
00339 #ifdef __cplusplus
00340 }
00341 #endif
00342 
00343 #endif /* S2LPREG_H_ */