pn512_irq.h

00001 /*
00002  * Copyright (c) 2013-2018, ARM Limited, All Rights Reserved
00003  * SPDX-License-Identifier: Apache-2.0
00004  *
00005  * Licensed under the Apache License, Version 2.0 (the "License"); you may
00006  * not use this file except in compliance with the License.
00007  * You may obtain a copy of the License at
00008  *
00009  * http://www.apache.org/licenses/LICENSE-2.0
00010  *
00011  * Unless required by applicable law or agreed to in writing, software
00012  * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
00013  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00014  * See the License for the specific language governing permissions and
00015  * limitations under the License.
00016  */
00017 /**
00018  * \file pn512_irq.h
00019  * \copyright Copyright (c) ARM Ltd 2013
00020  * \author Donatien Garnier
00021  */
00022 
00023 #ifndef PN512_IRQ_H_
00024 #define PN512_IRQ_H_
00025 
00026 #ifdef __cplusplus
00027 extern "C" {
00028 #endif
00029 
00030 #include "stack/nfc_common.h"
00031 #include "pn512.h"
00032 #include "pn512_registers.h"
00033 
00034 #define PN512_IRQ_TX          (1<<6)
00035 #define PN512_IRQ_RX          (1<<5)
00036 #define PN512_IRQ_IDLE        (1<<4)
00037 #define PN512_IRQ_HIGH_ALERT  (1<<3)
00038 #define PN512_IRQ_LOW_ALERT   (1<<2)
00039 #define PN512_IRQ_ERR         (1<<1)
00040 #define PN512_IRQ_TIMER       (1<<0)
00041 
00042 #define PN512_IRQ_SIGIN       (1<<(4+8))
00043 #define PN512_IRQ_MODE        (1<<(3+8))
00044 #define PN512_IRQ_CRC         (1<<(2+8))
00045 #define PN512_IRQ_RF_ON       (1<<(1+8))
00046 #define PN512_IRQ_RF_OFF      (1<<(0+8))
00047 
00048 #define PN512_IRQ_NONE        0x00
00049 #define PN512_IRQ_ALL         0x1F7F
00050 
00051 #define PN512_REG_COMIEN_MASK 0x7F
00052 #define PN512_REG_COMIEN_VAL  0x00
00053 
00054 #define PN512_REG_DIVIEN_MASK 0x1F
00055 #define PN512_REG_DIVIEN_VAL  0x80
00056 
00057 #define PN512_REG_COMIRQ_MASK 0x7F
00058 #define PN512_REG_COMIRQ_CLEAR  0x00
00059 
00060 #define PN512_REG_DIVIRQ_MASK 0x1F
00061 #define PN512_REG_DIVIRQ_CLEAR  0x00
00062 
00063 /** \internal Set IRQ enable registers
00064  * \param pPN512 pointer to pn512_t structure
00065  * \param irqs MSB is DIVIEN value, LSB is COMIEN value
00066  */
00067 static inline void pn512_irq_set(pn512_t *pPN512, uint16_t irqs) //ORed
00068 {
00069     pn512_register_write(pPN512, PN512_REG_COMIEN, PN512_REG_COMIEN_VAL | (PN512_REG_COMIEN_MASK & (irqs & 0xFF)));
00070     pn512_register_write(pPN512, PN512_REG_DIVIEN, PN512_REG_DIVIEN_VAL | (PN512_REG_DIVIEN_MASK & (irqs >> 8)));
00071     pPN512->irqsEn = irqs;
00072 }
00073 
00074 /** \internal Get IRQ enable registers
00075  * \param pPN512 pointer to pn512_t structure
00076  * \return MSB is DIVIEN value, LSB is COMIEN value
00077  */
00078 static inline uint16_t pn512_irq_enabled(pn512_t *pPN512) //ORed
00079 {
00080     return pPN512->irqsEn /*(pn512_register_read(pPN512, PN512_REG_COMIEN_VAL) & PN512_REG_COMIEN_MASK)
00081       | ((pn512_register_read(pPN512, PN512_REG_DIVIEN_VAL) & PN512_REG_DIVIEN_MASK) << 8)*/;
00082 }
00083 
00084 /** \internal Get IRQ status registers (masked with enabled IRQ register)
00085  * \param pPN512 pointer to pn512_t structure
00086  * \return MSB is DIVIRQ value, LSB is COMIRQ value
00087  */
00088 static inline uint16_t pn512_irq_get(pn512_t *pPN512) //ORed
00089 {
00090     return ((pn512_register_read(pPN512, PN512_REG_COMIRQ) & PN512_REG_COMIEN_MASK)
00091             | ((pn512_register_read(pPN512, PN512_REG_DIVIRQ) & PN512_REG_DIVIEN_MASK) << 8)) & pPN512->irqsEn;
00092 }
00093 
00094 /** \internal Clear some interrupts
00095  * \param pPN512 pointer to pn512_t structure
00096  * \param irqs MSB is DIVIEN value, LSB is COMIEN value
00097  */
00098 static inline void pn512_irq_clear(pn512_t *pPN512, uint16_t irqs)
00099 {
00100     pn512_register_write(pPN512, PN512_REG_COMIRQ, PN512_REG_COMIRQ_CLEAR | (PN512_REG_COMIRQ_MASK & (irqs & 0xFF)));
00101     pn512_register_write(pPN512, PN512_REG_DIVIRQ, PN512_REG_DIVIRQ_CLEAR | (PN512_REG_DIVIRQ_MASK & (irqs >> 8)));
00102 }
00103 
00104 #ifdef __cplusplus
00105 }
00106 #endif
00107 
00108 #endif /* PN512_IRQ_H_ */