driver_defs.h

00001 /**************************************************************************************
00002 * Copyright (c) 2016-2017, ARM Limited or its affiliates. All rights reserved         *
00003 *                                                                                     *
00004 * This file and the related binary are licensed under the following license:          *
00005 *                                                                                     *
00006 * ARM Object Code and Header Files License, v1.0 Redistribution.                      *
00007 *                                                                                     *
00008 * Redistribution and use of object code, header files, and documentation, without     *
00009 * modification, are permitted provided that the following conditions are met:         *
00010 *                                                                                     *
00011 * 1) Redistributions must reproduce the above copyright notice and the                *
00012 *    following disclaimer in the documentation and/or other materials                 *
00013 *    provided with the distribution.                                                  *
00014 *                                                                                     *
00015 * 2) Unless to the extent explicitly permitted by law, no reverse                     *
00016 *    engineering, decompilation, or disassembly of is permitted.                      *
00017 *                                                                                     *
00018 * 3) Redistribution and use is permitted solely for the purpose of                    *
00019 *    developing or executing applications that are targeted for use                   *
00020 *    on an ARM-based product.                                                         *
00021 *                                                                                     *
00022 * DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND                  *
00023 * CONTRIBUTORS "AS IS." ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT             *
00024 * NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,        *
00025 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE          *
00026 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,   *
00027 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED            *
00028 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR              *
00029 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF              *
00030 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING                *
00031 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS                  *
00032 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.                        *
00033 **************************************************************************************/
00034 
00035 
00036 
00037 #ifndef _DRIVER_DEFS_H_
00038 #define _DRIVER_DEFS_H_
00039 
00040 #ifdef __KERNEL__
00041 #include <linux/types.h>
00042 #define INT32_MAX 0x7FFFFFFFL
00043 #else
00044 #include <stdint.h>
00045 #endif
00046 
00047 #ifndef min
00048 #define min(a, b) ((a) < (b) ? (a) : (b))
00049 #endif
00050 
00051 /******************************************************************************
00052 *               TYPE DEFINITIONS
00053 ******************************************************************************/
00054 typedef uint32_t drvError_t;
00055 
00056 typedef enum aesMode {
00057     CIPHER_NULL_MODE = -1,
00058     CIPHER_ECB = 0,
00059     CIPHER_CBC = 1,
00060     CIPHER_CTR = 2,
00061     CIPHER_CBC_MAC = 3,
00062     CIPHER_CMAC = 7,
00063     CIPHER_RESERVE32B = INT32_MAX
00064 }aesMode_t;
00065 
00066 typedef enum hashMode {
00067     HASH_NULL_MODE = -1,
00068     HASH_SHA1 = 0,
00069     HASH_SHA256 = 1,
00070     HASH_SHA224 = 2,
00071     HASH_SHA512 = 3,
00072     HASH_SHA384 = 4,
00073     HASH_RESERVE32B = INT32_MAX
00074 }hashMode_t;
00075 
00076 typedef enum DataBlockType {
00077     FIRST_BLOCK,
00078     MIDDLE_BLOCK,
00079     LAST_BLOCK,
00080     RESERVE32B_BLOCK = INT32_MAX
00081 }DataBlockType_t;
00082 
00083 typedef enum dataAddrType {
00084     SRAM_ADDR = 0,
00085     DLLI_ADDR = 1,
00086     ADDR_RESERVE32B = INT32_MAX
00087 }dataAddrType_t;
00088 
00089 typedef enum cryptoDirection {
00090     CRYPTO_DIRECTION_ENCRYPT = 0,
00091     CRYPTO_DIRECTION_DECRYPT = 1,
00092 
00093     CRYPTO_DIRECTION_NUM_OF_ENC_MODES,
00094     CRYPTO_DIRECTION_RESERVE32B = INT32_MAX
00095 }cryptoDirection_t;
00096 
00097 typedef enum cryptoKeyType {
00098     RKEK_KEY = 0,
00099     USER_KEY = 1,
00100     PROVISIONING_KEY = 2,
00101     SESSION_KEY = 3,
00102     END_OF_KEYS = INT32_MAX,
00103 }cryptoKeyType_t;
00104 
00105 typedef enum cryptoPaddingType {
00106     CRYPTO_PADDING_NONE = 0,
00107     CRYPTO_PADDING_PKCS7 = 1,
00108     CRYPTO_PADDING_RESERVE32B = INT32_MAX
00109 }cryptoPaddingType_t;
00110 
00111 typedef enum chachaNonceSize {
00112         NONCE_SIZE_64 = 0,
00113         NONCE_SIZE_96 = 1,
00114         NONCE_SIZE_RESERVE32B = INT32_MAX
00115 }chachaNonceSize_t;
00116 
00117 /* The IOT drviers base address */
00118 #define DRV_MODULE_ERROR_BASE               0x00F00000
00119 #define AES_DRV_MODULE_ERROR_BASE           (DRV_MODULE_ERROR_BASE + 0x10000UL)
00120 #define HASH_DRV_MODULE_ERROR_BASE          (DRV_MODULE_ERROR_BASE + 0x20000UL)
00121 #define HMAC_DRV_MODULE_ERROR_BASE          (DRV_MODULE_ERROR_BASE + 0x30000UL)
00122 #define BYPASS_DRV_MODULE_ERROR_BASE            (DRV_MODULE_ERROR_BASE + 0x40000UL)
00123 #define CHACHA_DRV_MODULE_ERROR_BASE            (DRV_MODULE_ERROR_BASE + 0x50000UL)
00124 
00125 
00126 /******************************************************************************
00127 *               AES DEFINITIONS
00128 ******************************************************************************/
00129 
00130 #define AES_BLOCK_SIZE                  16
00131 #define AES_BLOCK_SIZE_WORDS            (AES_BLOCK_SIZE >> 2)
00132 #define AES_IV_SIZE                     16
00133 #define AES_IV_SIZE_WORDS               (AES_IV_SIZE >> 2)
00134 #define AES_128_BIT_KEY_SIZE            16
00135 #define AES_128_BIT_KEY_SIZE_WORDS  (AES_128_BIT_KEY_SIZE >> 2)
00136 
00137 
00138 #define ENABLE_AES_CLOCK        0x1UL
00139 #define DISABLE_AES_CLOCK       0x0UL
00140 
00141 #define CONFIG_DIN_AES_DOUT_VAL         0x1UL
00142 
00143 /* The CRYS AES module errors */
00144 #define AES_DRV_OK                      0
00145 #define AES_DRV_INVALID_USER_CONTEXT_POINTER_ERROR          (AES_DRV_MODULE_ERROR_BASE + 0x00UL)
00146 #define AES_DRV_ILLEGAL_OPERATION_MODE_ERROR                (AES_DRV_MODULE_ERROR_BASE + 0x01UL)
00147 #define AES_DRV_ILLEGAL_OPERATION_DIRECTION_ERROR           (AES_DRV_MODULE_ERROR_BASE + 0x02UL)
00148 #define AES_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR            (AES_DRV_MODULE_ERROR_BASE + 0x03UL)
00149 #define AES_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR           (AES_DRV_MODULE_ERROR_BASE + 0x04UL)
00150 #define AES_DRV_ILLEGAL_MEM_SIZE_ERROR              (AES_DRV_MODULE_ERROR_BASE + 0x05UL)
00151 
00152 
00153 /******************************************************************************
00154 *               HASH & HMAC DEFINITIONS
00155 ******************************************************************************/
00156 
00157 /************************ Typedefs  ****************************/
00158 typedef drvError_t (*llf_hash_init_operation_func)(void *);
00159 typedef drvError_t (*llf_hash_update_operation_func)(void *, uint32_t inputDataAddr, uint32_t dataInSize);
00160 typedef drvError_t (*llf_hash_finish_operation_func)(void *);
00161 
00162 
00163 /* The SHA-1 digest result size */
00164 #define SHA1_DIGEST_SIZE_IN_WORDS 5
00165 #define SHA1_DIGEST_SIZE_IN_BYTES (SHA1_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
00166 
00167 /* The SHA-256 digest result size*/
00168 #define SHA224_DIGEST_SIZE_IN_WORDS 7
00169 #define SHA224_DIGEST_SIZE_IN_BYTES (SHA224_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
00170 
00171 /* The SHA-256 digest result size */
00172 #define SHA256_DIGEST_SIZE_IN_WORDS 8
00173 #define SHA256_DIGEST_SIZE_IN_BYTES (SHA256_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
00174 
00175 /* The SHA-384 digest result size*/
00176 #define SHA384_DIGEST_SIZE_IN_WORDS 12
00177 #define SHA384_DIGEST_SIZE_IN_BYTES (SHA384_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
00178 
00179 /* The SHA-512 digest result size in bytes */
00180 #define SHA512_DIGEST_SIZE_IN_WORDS 16
00181 #define SHA512_DIGEST_SIZE_IN_BYTES (SHA512_DIGEST_SIZE_IN_WORDS * sizeof(uint32_t))
00182 
00183 
00184 #define MAX_DIGEST_SIZE_WORDS       SHA512_DIGEST_SIZE_IN_WORDS
00185 
00186 /* Hash driver registers configurations */
00187 #define ENABLE_HASH_CLOCK       0x1UL
00188 #define DISABLE_HASH_CLOCK      0x0UL
00189 
00190 #define HW_HASH_CTL_SHA1_VAL            0x0001UL
00191 #define HW_HASH_CTL_SHA256_VAL          0x0002UL
00192 #define HW_HASH_LE_MODE_VAL         0x0001UL
00193 #define HW_HASH_PAD_EN_VAL          0x1UL
00194 
00195 /* The SHA1 hash block size in words */
00196 #define HASH_BLOCK_SIZE_IN_WORDS 16
00197 #define HASH_BLOCK_SIZE_IN_BYTES (HASH_BLOCK_SIZE_IN_WORDS * sizeof(uint32_t))
00198 
00199 /* The SHA2 hash block size in words */
00200 #define HASH_SHA512_BLOCK_SIZE_IN_WORDS 32
00201 #define HASH_SHA512_BLOCK_SIZE_IN_BYTES (HASH_SHA512_BLOCK_SIZE_IN_WORDS * sizeof(uint32_t))
00202 
00203 #define CONFIG_HASH_MODE_VAL            0x7UL
00204 
00205 /* the MAC key IPAD and OPAD bytes */
00206 #define MAC_KEY_IPAD_BYTE 0x36
00207 #define MAC_KEY_OPAD_BYTE 0x5C
00208 
00209 #define HMAC_CONTEXT_VALIDATION_TAG 0x23456789
00210 
00211 /* The CRYS HASH module errors */
00212 #define HASH_DRV_OK                     0
00213 #define HASH_DRV_INVALID_USER_CONTEXT_POINTER_ERROR         (HASH_DRV_MODULE_ERROR_BASE + 0x00UL)
00214 #define HASH_DRV_ILLEGAL_OPERATION_MODE_ERROR           (HASH_DRV_MODULE_ERROR_BASE + 0x01UL)
00215 #define HASH_DRV_USER_CONTEXT_CORRUPTED_ERROR           (HASH_DRV_MODULE_ERROR_BASE + 0x02UL)
00216 
00217 /* The CRYS HMAC module errors */
00218 #define HMAC_DRV_OK                     0
00219 #define HMAC_DRV_INVALID_USER_CONTEXT_POINTER_ERROR         (HMAC_DRV_MODULE_ERROR_BASE + 0x00UL)
00220 
00221 
00222 /* SHA512 soft driver */
00223 
00224 /* The first padding byte */
00225 #define LLF_HASH_FIRST_PADDING_BYTE 0x80
00226 /* The size at the end of the padding for SHA384 and SHA512 */
00227 #define LLF_HASH_SHA2_COUNTER_SIZE_ON_END_OF_PADDING_IN_BYTES (4 * sizeof(uint32_t))
00228 #define LLF_HASH_SHA2_COUNTER_SIZE_ON_END_OF_PADDING_IN_WORDS 4
00229 
00230 /* the HASH user context validity TAG */
00231 #define HASH_CONTEXT_VALIDATION_TAG 0x12345678
00232 
00233 /******************************************************************************
00234 *               BYPASS DEFINITIONS
00235 ******************************************************************************/
00236 
00237 #define CONFIG_DIN_BYPASS_DOUT_VAL                      0
00238 
00239 /* The CRYS BYPASS module errors */
00240 #define BYPASS_DRV_OK                       0
00241 #define BYPASS_DRV_ILLEGAL_BLOCK_SIZE_ERROR         (BYPASS_DRV_MODULE_ERROR_BASE + 0x01UL)
00242 #define BYPASS_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR         (BYPASS_DRV_MODULE_ERROR_BASE + 0x02UL)
00243 #define BYPASS_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR        (BYPASS_DRV_MODULE_ERROR_BASE + 0x03UL)
00244 
00245 /******************************************************************************
00246 *               CHACHA DEFINITIONS
00247 ******************************************************************************/
00248 
00249 #define CHACHA_BLOCK_SIZE_BYTES             64
00250 #define CHACHA_BLOCK_SIZE_WORDS             (CHACHA_BLOCK_SIZE_BYTES >> 2)
00251 #define CHACHA_NONCE_64_SIZE_BYTES              8
00252 #define CHACHA_NONCE_64_SIZE_WORDS              (CHACHA_NONCE_64_SIZE_BYTES >> 2)
00253 #define CHACHA_NONCE_96_SIZE_BYTES              12
00254 #define CHACHA_NONCE_96_SIZE_WORDS              (CHACHA_NONCE_96_SIZE_BYTES >> 2)
00255 #define CHACHA_256_BIT_KEY_SIZE                 32
00256 #define CHACHA_256_BIT_KEY_SIZE_WORDS       (CHACHA_256_BIT_KEY_SIZE >> 2)
00257 
00258 #define ENABLE_CHACHA_CLOCK     0x1UL
00259 #define DISABLE_CHACHA_CLOCK        0x0UL
00260 
00261 #define CONFIG_DIN_CHACHA_DOUT_VAL          0x10UL
00262 
00263 /* The CRYS CHACHA module errors */
00264 #define CHACHA_DRV_OK                       0
00265 #define CHACHA_DRV_INVALID_USER_CONTEXT_POINTER_ERROR       (CHACHA_DRV_MODULE_ERROR_BASE + 0x00UL)
00266 #define CHACHA_DRV_ILLEGAL_OPERATION_DIRECTION_ERROR            (CHACHA_DRV_MODULE_ERROR_BASE + 0x01UL)
00267 #define CHACHA_DRV_ILLEGAL_INPUT_ADDR_MEM_ERROR         (CHACHA_DRV_MODULE_ERROR_BASE + 0x02UL)
00268 #define CHACHA_DRV_ILLEGAL_OUTPUT_ADDR_MEM_ERROR        (CHACHA_DRV_MODULE_ERROR_BASE + 0x03UL)
00269 #define CHACHA_DRV_ILLEGAL_MEM_SIZE_ERROR               (CHACHA_DRV_MODULE_ERROR_BASE + 0x04UL)
00270 #define CHACHA_DRV_ILLEGAL_NONCE_SIZE_ERROR             (CHACHA_DRV_MODULE_ERROR_BASE + 0x05UL)
00271 
00272 
00273 /******************************************************************************
00274 *               MACROS
00275 ******************************************************************************/
00276 /* This MACRO purpose is to switch from CryptoCell definitions to crypto driver definitions, the MACRO assumes that the value is legal (encrypt or decrypt only) */
00277 #define SASI_2_DRIVER_DIRECTION(ssiDirection) ((ssiDirection == SASI_AES_ENCRYPT) ? (CRYPTO_DIRECTION_ENCRYPT) : (CRYPTO_DIRECTION_DECRYPT))
00278 
00279 /* Poll on the DOUT MEM DMA (DLLI) busy till it is = 0 */
00280 #define SASI_HAL_WAIT_ON_DOUT_MEM_DMA_BUSY()\
00281         do {\
00282            uint32_t regVal=1;\
00283            do {\
00284                     regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, DOUT_MEM_DMA_BUSY));\
00285                }while( regVal ); \
00286         }while(0)
00287 
00288 /* Poll on the DIN MEM DMA (DLLI) busy till it is = 0 */
00289 #define SASI_HAL_WAIT_ON_DIN_MEM_DMA_BUSY()\
00290     do {\
00291             uint32_t regVal=1;\
00292             do {\
00293             regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, DIN_MEM_DMA_BUSY));\
00294                 }while( regVal );\
00295         }while(0)
00296 
00297 /* Poll on the DOUT SRAM DMA busy till it is = 0 */
00298 #define SASI_HAL_WAIT_ON_DOUT_SRAM_DMA_BUSY()\
00299     do {\
00300             uint32_t regVal=1; \
00301             do {\
00302             regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, DOUT_SRAM_DMA_BUSY));\
00303                 }while( regVal );\
00304         }while(0)
00305 
00306 /* Poll on the DIN SRAM busy till it is = 0 */
00307 #define SASI_HAL_WAIT_ON_DIN_SRAM_DMA_BUSY()\
00308     do {\
00309             uint32_t regVal=1;\
00310             do {\
00311             regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, DIN_SRAM_DMA_BUSY));\
00312                 }while( regVal );\
00313         }while(0)
00314 
00315 
00316 /* Poll on the AES busy till it is = 0 */
00317 #define SASI_HAL_WAIT_ON_AES_BUSY()\
00318     do {\
00319         uint32_t regVal=1;\
00320             do {\
00321             regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, AES_BUSY));\
00322                 }while( regVal );\
00323         }while(0)
00324 
00325 /* Poll on the HASH busy till it is = 0 */
00326 #define SASI_HAL_WAIT_ON_HASH_BUSY()\
00327     do {\
00328         uint32_t regVal=1;\
00329             do {\
00330             regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, HASH_BUSY));\
00331                 }while( regVal );\
00332         }while(0)
00333 
00334 /* Poll on the CHACHA busy till it is = 0 */
00335 #define SASI_HAL_WAIT_ON_CHACHA_BUSY()                                                                  \
00336         do {                                                                                            \
00337                 uint32_t regVal=1;                                                                      \
00338                 do {                                                                                    \
00339                         regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, CHACHA_BUSY));       \
00340                 }while( regVal );                                                                       \
00341         }while(0)
00342 
00343 /* Poll on the crypto busy till it is = 0 */
00344 #define SASI_HAL_WAIT_ON_CRYPTO_BUSY()\
00345     do {\
00346         uint32_t regVal=1;\
00347         do {\
00348             regVal = SASI_HAL_READ_REGISTER( SASI_REG_OFFSET(HOST_RGF, CRYPTO_BUSY));\
00349                 }while( regVal );\
00350         }while(0)
00351 
00352 
00353 #endif /* _DRIVER_DEFS_H_ */
00354