check_TYBLE16.cpp

00001 /*
00002  * Mbed Application program for TYBLE-16
00003  *
00004  * Copyright (c) 2018,'19 Kenji Arai / JH1PJL
00005  *  http://www.page.sannet.ne.jp/kenjia/index.html
00006  *  https://os.mbed.com/users/kenjiArai/
00007  *      Created:    Feburary  16th, 2018
00008  *      Revised:    December  15th, 2019
00009  */
00010 
00011 #include "mbed.h"
00012 
00013 static uint32_t mem_range[][2] = {     // Memory access range
00014     { 0x00000000, 0x0003ffff }, // On-chip non-volatile memory //128 or 256KB
00015     { 0x20000000, 0x20007fff }, // On-chip SRAM                //16 or 32KB
00016     { 0x10000000, 0x1000007f }, // FICR
00017     { 0x10001000, 0x100010ff }, // UICR
00018     { 0x40000000, 0x400245ff }, // Peripheral
00019     { 0x50000500, 0x500007ff }  // GPIO
00020 };
00021 
00022 static void mem_cnfg_init( uint8_t print )
00023 {
00024     uint32_t a, b, c;
00025 
00026     a = NRF_FICR->CODEPAGESIZE;
00027     b = NRF_FICR->CODESIZE;
00028     c = a * b;
00029     mem_range[0][1] = mem_range[0][0] + c -1;
00030     if (print) {
00031         printf("CODEPAGESIZE:%d, CODESIZE:%d\r\nFLASH:0x%08x-0x%08x\r\n",
00032                   a, b, mem_range[0][0], mem_range[0][1]);
00033     }
00034     a = NRF_FICR->NUMRAMBLOCK;
00035     b = NRF_FICR->SIZERAMBLOCKS;
00036     c = a * b;
00037     mem_range[1][1] = mem_range[1][0] + c -1;
00038     if (print) {
00039         printf("NUMRAMBLOCK:%d, SIZERAMBLOCKS:%d\r\nRAM:  0x%08x-0x%08x\r\n",
00040                   a, b, mem_range[1][0], mem_range[1][1]);
00041     }
00042 }
00043 
00044 void cpu_sys(void)
00045 {
00046     uint32_t m1 = 0, m2 = 0;
00047 
00048     //printf("line:%d\r\n", __LINE__);
00049     wait(0.1f);
00050     m1 = SCB->CPUID;
00051     m2 = ( m1 >> 24 );
00052     if ( m2 == 0x41 ) {
00053         printf( "CPU = ARM " );
00054         wait(0.1f);
00055     } else {
00056         printf( "CPU = NOT ARM " );
00057     }
00058     m2 = ( m1 >> 4 ) & 0xfff;
00059     if ( m2 == 0xc20 ) {
00060         printf( "Cortex-M0" );
00061         wait(0.1f);
00062     } else {
00063         printf( "NOT Cortex-M0" );
00064     }
00065     m2 = ( m1 >> 20 ) & 0x0f;
00066     printf( "  Variant:%x  ", m2 );
00067     m2 = m1 & 0x7;
00068     printf( "Revision:%x\r\n", m2 );
00069     printf( "CPU ID: 0x%08x\r\n", m1 );
00070     // nRF Chip revision
00071     m1 = (((*((uint32_t volatile *)0xF0000FE8)) & 0x000000F0) >> 4);
00072     switch (m1) {
00073         case 1:     // revision 1
00074             m2 = 1;
00075             break;
00076         case 4:     // revision 2
00077             m2 = 2;
00078             break;
00079         case 7:
00080         case 8:
00081         case 9:     // revision 3
00082             m2 = 3;
00083             break;
00084         default:
00085             m2 = 0;
00086             break;
00087     }
00088     if (m2) {
00089         printf( "nRF Revision: %d\r\n", m2 );
00090     } else {
00091         printf( "nRF Revision: Unknown\r\n" );
00092     }
00093     // Firmware
00094     m1 = NRF_UICR->FWID & 0xffff;
00095     printf( "Firmware ID: 0x%04x\r\n", m1 );
00096     // System Clock
00097     m1 = NRF_UICR->XTALFREQ & 0xff;
00098     printf( "System clock by " );
00099     if (m1) {
00100         printf( "XTAL:16MHz\r\n" );
00101     } else {
00102         printf( "XTAL:32MHz\r\n" );
00103     }
00104     m1 = NRF_CLOCK->LFCLKSRCCOPY & 0x3;
00105     printf( "LFCLK Source=32.768 kHz " );
00106     switch (m1) {
00107         case 0:     // revision 1
00108             printf( "RC oscillator" );
00109             break;
00110         case 1:     // revision 1
00111             printf( "crystal oscillator" );
00112             break;
00113         case 2:      // revision 1
00114             printf( "synthesized from HFCLK" );
00115             break;
00116         default:
00117             printf( "unknown" );
00118             break;
00119     }
00120     printf("\r\n");
00121     // FLASH & RAM
00122     mem_cnfg_init(1);
00123 }
00124 
00125 bool compile_condition(void)
00126 {
00127     uint32_t m1 = 0, m2 = 0;
00128 
00129     // ARM
00130     m1 = SCB->CPUID;
00131     m2 = ( m1 >> 24 );
00132     if ( m2 != 0x41 ) {
00133         return false;
00134     }
00135     // M0
00136     m2 = ( m1 >> 4 ) & 0xfff;
00137     if ( m2 != 0xc20 ) {
00138         return false;
00139     }
00140     // FLASH
00141     m1 = NRF_FICR->CODEPAGESIZE;
00142     if (m1 != 1024) {
00143         return false;
00144     }
00145     m1 = NRF_FICR->CODESIZE;
00146     if (m1 != 256) {
00147         return false;
00148     }
00149     // RAM
00150     m1 = NRF_FICR->NUMRAMBLOCK;
00151     if (m1 != 4) {
00152         return false;
00153     }
00154     m1 = NRF_FICR->SIZERAMBLOCKS;
00155     if (m1 != 8192) {
00156         return false;
00157     }
00158     // 32MHz Xtal
00159     m1 = NRF_UICR->XTALFREQ & 0xff;
00160     if (m1) {
00161         return false;   // Not 32MHz XTAL
00162     }
00163     // LF = internal RC
00164     m1 = NRF_CLOCK->LFCLKSRCCOPY & 0x3;
00165     if (m1 != 0) {
00166         printf("Looks TY51822r3 board\r\n");
00167         return false;   // Not RC
00168     }
00169     printf("Looks TYBLE16 board\r\n");
00170     return true;
00171 }