SPITester.h

00001 /*
00002  * Copyright (c) 2019, Arm Limited and affiliates.
00003  * SPDX-License-Identifier: Apache-2.0
00004  *
00005  * Licensed under the Apache License, Version 2.0 (the "License");
00006  * you may not use this file except in compliance with the License.
00007  * You may obtain a copy of the License at
00008  *
00009  * http://www.apache.org/licenses/LICENSE-2.0
00010  *
00011  * Unless required by applicable law or agreed to in writing, software
00012  * distributed under the License is distributed on an "AS IS" BASIS,
00013  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00014  * See the License for the specific language governing permissions and
00015  * limitations under the License.
00016  */
00017 
00018 #ifndef SPI_TESTER_H
00019 #define SPI_TESTER_H
00020 
00021 #include "MbedTester.h"
00022 
00023 class SPITester: public MbedTester {
00024 public:
00025 
00026     enum SpiMode {
00027         Mode0 = 0,
00028         Mode1 = 1,
00029         Mode2 = 2,
00030         Mode3 = 3
00031     };
00032 
00033     enum SpiBitOrder {
00034         MSBFirst = 0,
00035         LSBFirst = 1
00036     };
00037 
00038     enum SpiDuplex {
00039         FullDuplex = 0,
00040         HalfDuplex = 1
00041     };
00042 
00043     SPITester(const PinList *form_factor, const PinList *exclude_pins)
00044         : MbedTester(form_factor, exclude_pins)
00045     {
00046 
00047     }
00048 
00049 protected:
00050     /*
00051      * Read the number of transfers which have occurred
00052      *
00053      * return The number of SPI transfers that have completed since
00054      *         spi was reset.
00055      */
00056     uint16_t get_transfer_count(uint32_t addr_transfers, uint32_t size_transfers);
00057 
00058     /*
00059      * Read a checksum of data send to the tester
00060      *
00061      * param addr_checksum Address of the FPGA checksum reg.
00062      * param size_checksum Size of the FPGA checksum reg.
00063      *
00064      * return The sum of all bytes sent to the tester since reset.
00065      */
00066     uint32_t get_receive_checksum(uint32_t addr_checksum, uint32_t size_checksum);
00067 
00068     /*
00069      * Set the clock mode of the spi_slave module.
00070      *
00071      * param mode Spi clock mode
00072      * param addr_spi_ctrl Address of the FPGA spi control reg.
00073      * param size_spi_ctrl Size of the FPGA FPGA spi control reg.
00074      * param offset_clk_mode Clock mode offset.
00075      * param size_clk_mode Clock mode size.
00076      */
00077     void set_mode(SpiMode mode, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_clk_mode, uint32_t size_clk_mode);
00078 
00079     /*
00080      * Set bit order durring transmission of the spi_slave module.
00081      *
00082      * param bit_order Spi clock mode
00083      * param addr_spi_ctrl Address of the FPGA spi control reg.
00084      * param size_spi_ctrl Size of the FPGA FPGA spi control reg.
00085      * param offset_bit_order Bit order offset.
00086      * param size_bit_order Bit order size.
00087      */
00088     void set_bit_order(SpiBitOrder bit_order, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_bit_order, uint32_t size_bit_order);
00089 
00090     /*
00091      * Set symbol size used durring transmission of the spi_slave module.
00092      *
00093      * param sym_size Spi symbol size
00094      * param addr_spi_ctrl Address of the FPGA spi control reg.
00095      * param size_spi_ctrl Size of the FPGA FPGA spi control reg.
00096      * param offset_sym_size Symbol size offset.
00097      * param size_sym_size Symbol size size.
00098      */
00099     void set_sym_size(uint32_t sym_size, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_sym_size, uint32_t size_sym_size);
00100 
00101     /*
00102      * Set full-duplex/half-duplex transmission mode of the spi_slave module.
00103      *
00104      * param duplex Duplex mode used for the transmission
00105      * param addr_spi_ctrl Address of the FPGA spi control reg.
00106      * param size_spi_ctrl Size of the FPGA FPGA spi control reg.
00107      * param offset_duplex Duplex mode offset.
00108      * param size_duplex Duplex mode size.
00109      */
00110     void set_duplex_mode(SpiDuplex duplex, uint32_t addr_spi_ctrl, uint32_t size_spi_ctrl, uint32_t offset_duplex, uint32_t size_duplex);
00111 
00112     /*
00113      * Set tx/rx symbol count.
00114      *
00115      * tx_cnt TX symbol count
00116      * rx_cnt RX symbol count
00117      * param addr_hd_rx_cnt Address of the FPGA half duplex RX count reg.
00118      * param size_hd_rx_cnt Size of the FPGA half duplex RX count reg.
00119      * param addr_hd_tx_cnt Address of the FPGA half duplex TX count reg.
00120      * param size_hd_tx_cnt Size of the FPGA half duplex TX count reg.
00121      *
00122      *  note Required only in Half-Duplex mode.
00123      */
00124     void set_hd_tx_rx_cnt(uint16_t tx_cnt, uint16_t rx_cnt, uint32_t addr_hd_rx_cnt, uint32_t size_hd_rx_cnt, uint32_t addr_hd_tx_cnt, uint32_t size_hd_tx_cnt);
00125 };
00126 
00127 #endif