QSPI.h

00001 /* mbed Microcontroller Library
00002  * Copyright (c) 2006-2018 ARM Limited
00003  * SPDX-License-Identifier: Apache-2.0
00004  *
00005  * Licensed under the Apache License, Version 2.0 (the "License");
00006  * you may not use this file except in compliance with the License.
00007  * You may obtain a copy of the License at
00008  *
00009  *     http://www.apache.org/licenses/LICENSE-2.0
00010  *
00011  * Unless required by applicable law or agreed to in writing, software
00012  * distributed under the License is distributed on an "AS IS" BASIS,
00013  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00014  * See the License for the specific language governing permissions and
00015  * limitations under the License.
00016  */
00017 #ifndef MBED_QSPI_H
00018 #define MBED_QSPI_H
00019 
00020 #include "platform/platform.h"
00021 
00022 #if DEVICE_QSPI || defined(DOXYGEN_ONLY)
00023 
00024 #include "hal/qspi_api.h"
00025 #include "platform/PlatformMutex.h"
00026 #include "platform/SingletonPtr.h"
00027 #include "platform/NonCopyable.h"
00028 
00029 #define ONE_MHZ     1000000
00030 
00031 #define QSPI_NO_INST (-1)
00032 
00033 namespace mbed {
00034 /** \defgroup drivers-public-api-spi SPI
00035  * \ingroup drivers-public-api
00036  */
00037 
00038 /**
00039  * \defgroup drivers_QSPI QSPI class
00040  * \ingroup drivers-public-api-spi
00041  * @{
00042  */
00043 
00044 /** Type representing a QSPI instruction
00045  */
00046 typedef int qspi_inst_t;
00047 
00048 /** A QSPI Driver, used for communicating with QSPI slave devices
00049  *
00050  * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
00051  * Most QSPI devices will also require Chip Select which is indicated by ssel.
00052  *
00053  * @note Synchronization level: Thread safe
00054  *
00055  * Example:
00056  * @code
00057  * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
00058  *
00059  * #include "mbed.h"
00060  *
00061  * #define CMD_WRITE 0x02
00062  * #define CMD_READ  0x03
00063  * #define ADDRESS   0x1000
00064  *
00065  * // hardware ssel (where applicable)
00066  * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel
00067  *
00068  *
00069  * int main() {
00070  *     char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
00071  *     char rx_buf[4];
00072  *     int buf_len = sizeof(tx_buf);
00073  *
00074  *     qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
00075  *     if (result != QSPI_STATUS_OK) {
00076  *        printf("Write failed");
00077  *     }
00078  *     result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
00079  *     if (result != QSPI_STATUS_OK) {
00080  *        printf("Read failed");
00081  *     }
00082  *
00083  * }
00084  * @endcode
00085  */
00086 class QSPI : private NonCopyable<QSPI> {
00087 
00088 public:
00089 
00090     /** Create a QSPI master connected to the specified pins
00091      *
00092      *  io0-io3 is used to specify the Pins used for Quad SPI mode
00093      *
00094      *  @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
00095      *  @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
00096      *  @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
00097      *  @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
00098      *  @param sclk QSPI Clock pin
00099      *  @param ssel QSPI chip select pin
00100      *  @param mode Clock polarity and phase mode (0 - 3) of SPI
00101      *         (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
00102      *
00103      */
00104     QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
00105 
00106     /** Create a QSPI master connected to the specified pins
00107      *
00108      *  io0-io3 is used to specify the Pins used for Quad SPI mode
00109      *
00110      *  @param pinmap reference to structure which holds static pinmap
00111      *  @param mode Clock polarity and phase mode (0 - 3) of SPI
00112      *         (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
00113      *
00114      */
00115     QSPI(const qspi_pinmap_t &pinmap, int mode = 0);
00116     QSPI(const qspi_pinmap_t &&, int = 0) = delete; // prevent passing of temporary objects
00117 
00118     virtual ~QSPI()
00119     {
00120     }
00121 
00122     /** Configure the data transmission format
00123      *
00124      *  @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
00125      *  @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
00126      *  @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
00127      *  @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
00128      *  @param alt_size Size in bits used by alt phase (must be a multiple of the number of bus lines indicated in alt_width)
00129      *  @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
00130      *  @param dummy_cycles Number of dummy clock cycles to be used after alt phase
00131      *
00132      */
00133     qspi_status_t configure_format(qspi_bus_width_t inst_width,
00134                                    qspi_bus_width_t address_width,
00135                                    qspi_address_size_t address_size,
00136                                    qspi_bus_width_t alt_width,
00137                                    qspi_alt_size_t alt_size,
00138                                    qspi_bus_width_t data_width,
00139                                    int dummy_cycles);
00140 
00141     /** Set the qspi bus clock frequency
00142      *
00143      *  @param hz SCLK frequency in hz (default = 1MHz)
00144      *  @returns
00145      *    Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
00146      */
00147     qspi_status_t set_frequency(int hz = ONE_MHZ);
00148 
00149     /** Read from QSPI peripheral with the preset read_instruction and alt_value
00150      *
00151      *  @param address Address to be accessed in QSPI peripheral
00152      *  @param rx_buffer Buffer for data to be read from the peripheral
00153      *  @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
00154      *
00155      *  @returns
00156      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00157      */
00158     qspi_status_t read(int address, char *rx_buffer, size_t *rx_length);
00159 
00160     /** Write to QSPI peripheral using custom write instruction
00161      *
00162      *  @param address Address to be accessed in QSPI peripheral
00163      *  @param tx_buffer Buffer containing data to be sent to peripheral
00164      *  @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
00165      *
00166      *  @returns
00167      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00168      */
00169     qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
00170 
00171     /** Read from QSPI peripheral using custom read instruction, alt values
00172      *
00173      *  @param instruction Instruction value to be used in instruction phase. Use QSPI_NO_INST to skip the instruction phase
00174      *  @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
00175      *  @param address Address to be accessed in QSPI peripheral
00176      *  @param rx_buffer Buffer for data to be read from the peripheral
00177      *  @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
00178      *
00179      *  @returns
00180      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00181      */
00182     qspi_status_t read(qspi_inst_t instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
00183 
00184     /** Write to QSPI peripheral using custom write instruction, alt values
00185      *
00186      *  @param instruction Instruction value to be used in instruction phase. Use QSPI_NO_INST to skip the instruction phase
00187      *  @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
00188      *  @param address Address to be accessed in QSPI peripheral
00189      *  @param tx_buffer Buffer containing data to be sent to peripheral
00190      *  @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
00191      *
00192      *  @returns
00193      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00194      */
00195     qspi_status_t write(qspi_inst_t instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
00196 
00197     /** Perform a transaction to write to an address(a control register) and get the status results
00198      *
00199      *  @param instruction Instruction value to be used in instruction phase. Use QSPI_NO_INST to skip the instruction phase
00200      *  @param address Some instruction might require address. Use -1 if no address
00201      *  @param tx_buffer Buffer containing data to be sent to peripheral
00202      *  @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
00203      *  @param rx_buffer Buffer for data to be read from the peripheral
00204      *  @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
00205      *
00206      *  @returns
00207      *    Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
00208      */
00209     qspi_status_t command_transfer(qspi_inst_t instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
00210 
00211 #if !defined(DOXYGEN_ONLY)
00212 protected:
00213     /** Acquire exclusive access to this SPI bus
00214      */
00215     virtual void lock(void);
00216 
00217     /** Release exclusive access to this SPI bus
00218      */
00219     virtual void unlock(void);
00220 
00221     qspi_t _qspi;
00222 
00223     bool acquire(void);
00224     static QSPI *_owner;
00225     static SingletonPtr<PlatformMutex>  _mutex;
00226     qspi_bus_width_t _inst_width; //Bus width for Instruction phase
00227     qspi_bus_width_t _address_width; //Bus width for Address phase
00228     qspi_address_size_t _address_size;
00229     qspi_bus_width_t _alt_width; //Bus width for Alt phase
00230     qspi_alt_size_t _alt_size;
00231     qspi_bus_width_t _data_width; //Bus width for Data phase
00232     qspi_command_t _qspi_command; //QSPI Hal command struct
00233     unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
00234     int _hz; //Bus Frequency
00235     int _mode; //SPI mode
00236     bool _initialized;
00237     PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
00238     const qspi_pinmap_t *_static_pinmap;
00239     bool (QSPI::* _init_func)(void);
00240 
00241 private:
00242     /* Private acquire function without locking/unlocking
00243      * Implemented in order to avoid duplicate locking and boost performance
00244      */
00245     bool _acquire(void);
00246     bool _initialize();
00247     bool _initialize_direct();
00248 
00249     /*
00250      * This function builds the qspi command struct to be send to Hal
00251      */
00252     inline void _build_qspi_command(qspi_inst_t instruction, int address, int alt);
00253 #endif
00254 };
00255 
00256 /** @}*/
00257 
00258 } // namespace mbed
00259 
00260 #endif
00261 
00262 #endif