QSPIFBlockDevice.cpp

00001 /* mbed Microcontroller Library
00002  * Copyright (c) 2018 ARM Limited
00003  *
00004  * Licensed under the Apache License, Version 2.0 (the "License");
00005  * you may not use this file except in compliance with the License.
00006  * You may obtain a copy of the License at
00007  *
00008  *     http://www.apache.org/licenses/LICENSE-2.0
00009  *
00010  * Unless required by applicable law or agreed to in writing, software
00011  * distributed under the License is distributed on an "AS IS" BASIS,
00012  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
00013  * See the License for the specific language governing permissions and
00014  * limitations under the License.
00015  */
00016 
00017 #include "QSPIFBlockDevice.h"
00018 #include <string.h>
00019 #include "rtos/ThisThread.h"
00020 
00021 #ifndef MBED_CONF_MBED_TRACE_ENABLE
00022 #define MBED_CONF_MBED_TRACE_ENABLE        0
00023 #endif
00024 
00025 #include "mbed_trace.h"
00026 #define TRACE_GROUP "QSPIF"
00027 
00028 using namespace mbed;
00029 
00030 /* Default QSPIF Parameters */
00031 /****************************/
00032 #define QSPIF_DEFAULT_PAGE_SIZE  256
00033 #define QSPIF_DEFAULT_SE_SIZE    4096
00034 // The SFDP spec only defines two status registers. But some devices,
00035 // have three "status-like" registers (one status, two config)
00036 #define QSPI_MAX_STATUS_REGISTERS 3
00037 #define QSPI_DEFAULT_STATUS_REGISTERS 2
00038 #ifndef UINT64_MAX
00039 #define UINT64_MAX -1
00040 #endif
00041 #define QSPI_NO_ADDRESS_COMMAND UINT64_MAX
00042 #define QSPI_ALT_DEFAULT_VALUE  0
00043 // Status Register Bits
00044 #define QSPIF_STATUS_BIT_WIP        0x1 // Write In Progress
00045 #define QSPIF_STATUS_BIT_WEL        0x2 // Write Enable Latch
00046 #define QSPIF_NO_QUAD_ENABLE        (-1)
00047 
00048 /* SFDP Header Parsing */
00049 /***********************/
00050 #define QSPIF_RSFDP_DUMMY_CYCLES 8
00051 #define QSPIF_SFDP_HEADER_SIZE 8
00052 #define QSPIF_PARAM_HEADER_SIZE 8
00053 
00054 /* Basic Parameters Table Parsing */
00055 /**********************************/
00056 #define SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES 64 /* 16 DWORDS */
00057 //READ Instruction support according to BUS Configuration
00058 #define QSPIF_BASIC_PARAM_TABLE_FAST_READ_SUPPORT_BYTE 2
00059 #define QSPIF_BASIC_PARAM_TABLE_QPI_READ_SUPPORT_BYTE 16
00060 #define QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE 27
00061 #define QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE 9
00062 #define QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE 11
00063 #define QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE 23
00064 #define QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE 15
00065 #define QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE 13
00066 #define QSPIF_BASIC_PARAM_TABLE_PAGE_SIZE_BYTE 40
00067 // Quad Enable Params
00068 #define QSPIF_BASIC_PARAM_TABLE_QER_BYTE 58
00069 #define QSPIF_BASIC_PARAM_TABLE_444_MODE_EN_SEQ_BYTE 56
00070 // Erase Types Params
00071 #define QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_1_BYTE 29
00072 #define QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_2_BYTE 31
00073 #define QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_3_BYTE 33
00074 #define QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_4_BYTE 35
00075 #define QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_1_SIZE_BYTE 28
00076 #define QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_2_SIZE_BYTE 30
00077 #define QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_3_SIZE_BYTE 32
00078 #define QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_4_SIZE_BYTE 34
00079 #define QSPIF_BASIC_PARAM_4K_ERASE_TYPE_BYTE 1
00080 
00081 #define QSPIF_BASIC_PARAM_TABLE_SOFT_RESET_BYTE 61
00082 #define QSPIF_BASIC_PARAM_TABLE_4BYTE_ADDR_BYTE 63
00083 
00084 #define SOFT_RESET_RESET_INST_BITMASK            0b001000
00085 #define SOFT_RESET_ENABLE_AND_RESET_INST_BITMASK 0b010000
00086 
00087 // Erase Types Per Region BitMask
00088 #define ERASE_BITMASK_TYPE4 0x08
00089 #define ERASE_BITMASK_TYPE1 0x01
00090 #define ERASE_BITMASK_NONE  0x00
00091 #define ERASE_BITMASK_ALL   0x0F
00092 
00093 // 4-Byte Addressing Support Bitmasks
00094 #define FOURBYTE_ADDR_B7_BITMASK           0b00000001
00095 #define FOURBYTE_ADDR_B7_WREN_BITMASK      0b00000010
00096 #define FOURBYTE_ADDR_EXT_ADDR_REG_BITMASK 0b00000100
00097 #define FOURBYTE_ADDR_BANK_REG_BITMASK     0b00001000
00098 #define FOURBYTE_ADDR_CONF_REG_BITMASK     0b00010000
00099 #define FOURBYTE_ADDR_INSTS_BITMASK        0b00100000
00100 #define FOURBYTE_ADDR_ALWAYS_BITMASK       0b01000000
00101 
00102 #define IS_MEM_READY_MAX_RETRIES 10000
00103 
00104 
00105 // General QSPI instructions
00106 #define QSPIF_INST_WSR1  0x01 // Write status register 1
00107 #define QSPIF_INST_PROG  0x02 // Page program
00108 #define QSPIF_INST_WRDI  0x04 // Write disable
00109 #define QSPIF_INST_RSR1  0x05 // Read status register 1
00110 #define QSPIF_INST_WREN  0x06 // Write enable
00111 #define QSPIF_INST_RSFDP 0x5A // Read SFDP
00112 #define QSPIF_INST_RDID  0x9F // Read Manufacturer and JDEC Device ID
00113 
00114 // Device-specific instructions
00115 #define QSPIF_INST_ULBPR 0x98 // Clear all write-protection bits in the Block-Protection register
00116 #define QSPIF_INST_RDCR  0x15 // Read the two control registers
00117 
00118 // Default read/legacy erase instructions
00119 #define QSPIF_INST_READ_DEFAULT          0x03
00120 #define QSPIF_INST_LEGACY_ERASE_DEFAULT  QSPI_NO_INST
00121 
00122 // Default status register 2 read/write instructions
00123 #define QSPIF_INST_WSR2_DEFAULT    QSPI_NO_INST
00124 #define QSPIF_INST_RSR2_DEFAULT    0x35
00125 
00126 // Default 4-byte extended addressing register write instruction
00127 #define QSPIF_INST_4BYTE_REG_WRITE_DEFAULT QSPI_NO_INST
00128 
00129 
00130 // Length of data returned from RDID instruction
00131 #define QSPI_RDID_DATA_LENGTH 3
00132 
00133 
00134 /* Init function to initialize Different Devices CS static list */
00135 static PinName *generate_initialized_active_qspif_csel_arr();
00136 // Static Members for different devices csel
00137 // _devices_mutex is used to lock csel list - only one QSPIFBlockDevice instance per csel is allowed
00138 SingletonPtr<PlatformMutex>  QSPIFBlockDevice::_devices_mutex;
00139 int QSPIFBlockDevice::_number_of_active_qspif_flash_csel = 0;
00140 PinName *QSPIFBlockDevice::_active_qspif_flash_csel_arr = generate_initialized_active_qspif_csel_arr();
00141 
00142 /********* Public API Functions *********/
00143 /****************************************/
00144 QSPIFBlockDevice::QSPIFBlockDevice(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName csel,
00145                                    int clock_mode, int freq)
00146     : _qspi(io0, io1, io2, io3, sclk, csel, clock_mode), _csel(csel), _freq(freq), _device_size_bytes(0),
00147       _init_ref_count(0),
00148       _is_initialized(false)
00149 {
00150     _unique_device_status = add_new_csel_instance(csel);
00151 
00152     if (_unique_device_status == 0) {
00153         tr_debug("Adding a new QSPIFBlockDevice csel: %d", (int)csel);
00154     } else if (_unique_device_status == -1) {
00155         tr_error("QSPIFBlockDevice with the same csel(%d) already exists", (int)csel);
00156     } else {
00157         tr_error("Too many different QSPIFBlockDevice devices - max allowed: %d", QSPIF_MAX_ACTIVE_FLASH_DEVICES);
00158     }
00159 
00160     // Initialize parameters
00161     _min_common_erase_size = 0;
00162     _regions_count = 1;
00163     _region_erase_types_bitfield[0] = ERASE_BITMASK_NONE;
00164 
00165     // Until proven otherwise, assume no quad enable
00166     _quad_enable_register_idx = QSPIF_NO_QUAD_ENABLE;
00167     _quad_enable_bit = QSPIF_NO_QUAD_ENABLE;
00168     _needs_fast_mode = false;
00169 
00170     // Default Bus Setup 1_1_1 with 0 dummy and mode cycles
00171     _inst_width = QSPI_CFG_BUS_SINGLE;
00172     _address_width = QSPI_CFG_BUS_SINGLE;
00173     _address_size = QSPI_CFG_ADDR_SIZE_24;
00174     _alt_size = 0;
00175     _dummy_cycles = 0;
00176     _data_width = QSPI_CFG_BUS_SINGLE;
00177 
00178     // Set default read/erase instructions
00179     _read_instruction = QSPIF_INST_READ_DEFAULT;
00180     _legacy_erase_instruction = QSPIF_INST_LEGACY_ERASE_DEFAULT;
00181 
00182     _num_status_registers = QSPI_DEFAULT_STATUS_REGISTERS;
00183     // Set default status register 2 write/read instructions
00184     _write_status_reg_2_inst = QSPIF_INST_WSR2_DEFAULT;
00185     _read_status_reg_2_inst = QSPIF_INST_RSR2_DEFAULT;
00186 
00187     _clear_protection_method = QSPIF_BP_CLEAR_SR;
00188 
00189     // Set default 4-byte addressing extension register write instruction
00190     _attempt_4_byte_addressing = true;
00191     _4byte_msb_reg_write_inst = QSPIF_INST_4BYTE_REG_WRITE_DEFAULT;
00192 }
00193 
00194 int QSPIFBlockDevice::init()
00195 {
00196     if (_unique_device_status == 0) {
00197         tr_debug("QSPIFBlockDevice csel: %d", (int)_csel);
00198     } else if (_unique_device_status == -1) {
00199         tr_error("QSPIFBlockDevice with the same csel(%d) already exists", (int)_csel);
00200         return QSPIF_BD_ERROR_DEVICE_NOT_UNIQUE;
00201     } else {
00202         tr_error("Too many different QSPIFBlockDevice devices - max allowed: %d", QSPIF_MAX_ACTIVE_FLASH_DEVICES);
00203         return QSPIF_BD_ERROR_DEVICE_MAX_EXCEED;
00204     }
00205 
00206     int status = QSPIF_BD_ERROR_OK;
00207     uint32_t basic_table_addr = 0;
00208     size_t basic_table_size = 0;
00209     uint32_t sector_map_table_addr = 0;
00210     size_t sector_map_table_size = 0;
00211 
00212     _mutex.lock();
00213 
00214     // All commands other than Read and RSFDP use default 1-1-1 bus mode (Program/Erase are constrained by flash memory performance more than bus performance)
00215     if (QSPI_STATUS_OK != _qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, _address_size, QSPI_CFG_BUS_SINGLE,
00216                                                  0, QSPI_CFG_BUS_SINGLE, 0)) {
00217         tr_error("_qspi_configure_format failed");
00218         status = QSPIF_BD_ERROR_DEVICE_ERROR;
00219         goto exit_point;
00220     }
00221 
00222     if (!_is_initialized) {
00223         _init_ref_count = 0;
00224     }
00225 
00226     _init_ref_count++;
00227 
00228     if (_init_ref_count != 1) {
00229         goto exit_point;
00230     }
00231 
00232     _alt_size = 0;
00233     _dummy_cycles = 0;
00234     if (QSPI_STATUS_OK != _qspi_set_frequency(_freq)) {
00235         tr_error("QSPI Set Frequency Failed");
00236         status = QSPIF_BD_ERROR_DEVICE_ERROR;
00237         goto exit_point;
00238     }
00239 
00240     // Synchronize Device
00241     if (false == _is_mem_ready()) {
00242         tr_error("Init - _is_mem_ready Failed");
00243         status = QSPIF_BD_ERROR_READY_FAILED;
00244         goto exit_point;
00245     }
00246 
00247     if (0 != _handle_vendor_quirks()) {
00248         tr_error("Init - Could not read vendor id");
00249         status = QSPIF_BD_ERROR_DEVICE_ERROR;
00250         goto exit_point;
00251     }
00252 
00253     /**************************** Parse SFDP Header ***********************************/
00254     if (0 != _sfdp_parse_sfdp_headers(basic_table_addr, basic_table_size, sector_map_table_addr, sector_map_table_size)) {
00255         tr_error("Init - Parse SFDP Headers Failed");
00256         status = QSPIF_BD_ERROR_PARSING_FAILED;
00257         goto exit_point;
00258     }
00259 
00260     /**************************** Parse Basic Parameters Table ***********************************/
00261     if (0 != _sfdp_parse_basic_param_table(basic_table_addr, basic_table_size)) {
00262         tr_error("Init - Parse Basic Param Table Failed");
00263         status = QSPIF_BD_ERROR_PARSING_FAILED;
00264         goto exit_point;
00265     }
00266 
00267     /**************************** Parse Sector Map Table ***********************************/
00268     _region_size_bytes[0] =
00269         _device_size_bytes; // If there's no region map, we have a single region sized the entire device size
00270     _region_high_boundary[0] = _device_size_bytes - 1;
00271 
00272     if ((sector_map_table_addr != 0) && (0 != sector_map_table_size)) {
00273         tr_debug("Init - Parsing Sector Map Table - addr: 0x%lxh, Size: %d", sector_map_table_addr,
00274                  sector_map_table_size);
00275         if (0 != _sfdp_parse_sector_map_table(sector_map_table_addr, sector_map_table_size)) {
00276             tr_error("Init - Parse Sector Map Table Failed");
00277             status = QSPIF_BD_ERROR_PARSING_FAILED;
00278             goto exit_point;
00279         }
00280     }
00281 
00282     if (0 != _clear_block_protection()) {
00283         tr_error("Init - clearing block protection failed");
00284         status = QSPIF_BD_ERROR_PARSING_FAILED;
00285         goto exit_point;
00286     }
00287 
00288     _is_initialized = true;
00289 
00290 exit_point:
00291     _mutex.unlock();
00292 
00293     return status;
00294 }
00295 
00296 int QSPIFBlockDevice::deinit()
00297 {
00298     int result = QSPIF_BD_ERROR_OK;
00299 
00300     _mutex.lock();
00301 
00302     if (!_is_initialized) {
00303         _init_ref_count = 0;
00304         _mutex.unlock();
00305         return result;
00306     }
00307 
00308     _init_ref_count--;
00309 
00310     if (_init_ref_count) {
00311         _mutex.unlock();
00312         return result;
00313     }
00314 
00315     // Disable Device for Writing
00316     qspi_status_t status = _qspi_send_general_command(QSPIF_INST_WRDI, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0);
00317     if (status != QSPI_STATUS_OK)  {
00318         tr_error("Write Disable failed");
00319         result = QSPIF_BD_ERROR_DEVICE_ERROR;
00320     }
00321 
00322     _is_initialized = false;
00323 
00324     _mutex.unlock();
00325 
00326     if (_unique_device_status == 0) {
00327         remove_csel_instance(_csel);
00328     }
00329 
00330     return result;
00331 }
00332 
00333 int QSPIFBlockDevice::read(void *buffer, bd_addr_t addr, bd_size_t size)
00334 {
00335     int status = QSPIF_BD_ERROR_OK;
00336     tr_debug("Read Inst: 0x%xh", _read_instruction);
00337 
00338     _mutex.lock();
00339 
00340     if (QSPI_STATUS_OK != _qspi_send_read_command(_read_instruction, buffer, addr, size)) {
00341         tr_error("Read Command failed");
00342         status = QSPIF_BD_ERROR_DEVICE_ERROR;
00343     }
00344 
00345     _mutex.unlock();
00346 
00347     return status;
00348 
00349 }
00350 
00351 int QSPIFBlockDevice::program(const void *buffer, bd_addr_t addr, bd_size_t size)
00352 {
00353     qspi_status_t result = QSPI_STATUS_OK;
00354     bool program_failed = false;
00355     int status = QSPIF_BD_ERROR_OK;
00356     uint32_t offset = 0;
00357     uint32_t chunk = 0;
00358     bd_size_t written_bytes = 0;
00359 
00360     tr_debug("Program - Buff: 0x%lxh, addr: %llu, size: %llu", (uint32_t)buffer, addr, size);
00361 
00362     while (size > 0) {
00363         // Write on _page_size_bytes boundaries (Default 256 bytes a page)
00364         offset = addr % _page_size_bytes;
00365         chunk = (offset + size < _page_size_bytes) ? size : (_page_size_bytes - offset);
00366         written_bytes = chunk;
00367 
00368         _mutex.lock();
00369 
00370         //Send WREN
00371         if (_set_write_enable() != 0) {
00372             tr_error("Write Enabe failed");
00373             program_failed = true;
00374             status = QSPIF_BD_ERROR_WREN_FAILED;
00375             goto exit_point;
00376         }
00377 
00378         result = _qspi_send_program_command(QSPIF_INST_PROG, buffer, addr, &written_bytes);
00379         if ((result != QSPI_STATUS_OK) || (chunk != written_bytes)) {
00380             tr_error("Write failed");
00381             program_failed = true;
00382             status = QSPIF_BD_ERROR_DEVICE_ERROR;
00383             goto exit_point;
00384         }
00385 
00386         buffer = static_cast<const uint8_t *>(buffer) + chunk;
00387         addr += chunk;
00388         size -= chunk;
00389 
00390         if (false == _is_mem_ready()) {
00391             tr_error("Device not ready after write, failed");
00392             program_failed = true;
00393             status = QSPIF_BD_ERROR_READY_FAILED;
00394             goto exit_point;
00395         }
00396         _mutex.unlock();
00397     }
00398 
00399 exit_point:
00400     if (program_failed) {
00401         _mutex.unlock();
00402     }
00403 
00404     return status;
00405 }
00406 
00407 int QSPIFBlockDevice::erase(bd_addr_t addr, bd_size_t in_size)
00408 {
00409     int type = 0;
00410     uint32_t offset = 0;
00411     uint32_t chunk = 4096;
00412     qspi_inst_t cur_erase_inst = QSPI_NO_INST;
00413     int size = (int)in_size;
00414     bool erase_failed = false;
00415     int status = QSPIF_BD_ERROR_OK;
00416     // Find region of erased address
00417     int region = _utils_find_addr_region(addr);
00418     // Erase Types of selected region
00419     uint8_t bitfield = _region_erase_types_bitfield[region];
00420 
00421     tr_debug("Erase - addr: %llu, in_size: %llu", addr, in_size);
00422 
00423     if ((addr + in_size) > _device_size_bytes) {
00424         tr_error("Erase exceeds flash device size");
00425         return QSPIF_BD_ERROR_INVALID_ERASE_PARAMS;
00426     }
00427 
00428     if (((addr % get_erase_size(addr)) != 0) || (((addr + in_size) % get_erase_size(addr + in_size - 1)) != 0)) {
00429         tr_error("Invalid erase - unaligned address and size");
00430         return QSPIF_BD_ERROR_INVALID_ERASE_PARAMS;
00431     }
00432 
00433     // For each iteration erase the largest section supported by current region
00434     while (size > 0) {
00435         unsigned int eu_size;
00436         if (_legacy_erase_instruction == QSPI_NO_INST) {
00437             // Iterate to find next largest erase type that is a) supported by region, and b) smaller than size.
00438             // Find the matching instruction and erase size chunk for that type.
00439             type = _utils_iterate_next_largest_erase_type(bitfield, size, (int)addr, _region_high_boundary[region]);
00440             cur_erase_inst = _erase_type_inst_arr[type];
00441             eu_size = _erase_type_size_arr[type];
00442         } else {
00443             // Must use legacy 4k erase instruction
00444             cur_erase_inst = _legacy_erase_instruction;
00445             eu_size = QSPIF_DEFAULT_SE_SIZE;
00446         }
00447         offset = addr % eu_size;
00448         chunk = ((offset + size) < eu_size) ? size : (eu_size - offset);
00449 
00450         tr_debug("Erase - addr: %llu, size:%d, Inst: 0x%xh, chunk: %lu ",
00451                  addr, size, cur_erase_inst, chunk);
00452         tr_debug("Erase - Region: %d, Type:%d ",
00453                  region, type);
00454 
00455         _mutex.lock();
00456 
00457         if (_set_write_enable() != 0) {
00458             tr_error("QSPI Erase Device not ready - failed");
00459             erase_failed = true;
00460             status = QSPIF_BD_ERROR_WREN_FAILED;
00461             goto exit_point;
00462         }
00463 
00464         if (QSPI_STATUS_OK != _qspi_send_erase_command(cur_erase_inst, addr, size)) {
00465             tr_error("QSPI Erase command failed!");
00466             erase_failed = true;
00467             status = QSPIF_BD_ERROR_DEVICE_ERROR;
00468             goto exit_point;
00469         }
00470 
00471         addr += chunk;
00472         size -= chunk;
00473 
00474         if ((size > 0) && (addr > _region_high_boundary[region])) {
00475             // erase crossed to next region
00476             region++;
00477             bitfield = _region_erase_types_bitfield[region];
00478         }
00479 
00480         if (false == _is_mem_ready()) {
00481             tr_error("QSPI After Erase Device not ready - failed");
00482             erase_failed = true;
00483             status = QSPIF_BD_ERROR_READY_FAILED;
00484             goto exit_point;
00485         }
00486 
00487         _mutex.unlock();
00488     }
00489 
00490 exit_point:
00491     if (erase_failed) {
00492         _mutex.unlock();
00493     }
00494 
00495     return status;
00496 }
00497 
00498 bd_size_t QSPIFBlockDevice::get_read_size() const
00499 {
00500     // Return minimum read size in bytes for the device
00501     return MBED_CONF_QSPIF_QSPI_MIN_READ_SIZE;
00502 }
00503 
00504 bd_size_t QSPIFBlockDevice::get_program_size() const
00505 {
00506     // Return minimum program/write size in bytes for the device
00507     return MBED_CONF_QSPIF_QSPI_MIN_PROG_SIZE;
00508 }
00509 
00510 bd_size_t QSPIFBlockDevice::get_erase_size() const
00511 {
00512     // return minimal erase size supported by all regions (0 if none exists)
00513     return _min_common_erase_size;
00514 }
00515 
00516 const char *QSPIFBlockDevice::get_type() const
00517 {
00518     return "QSPIF";
00519 }
00520 
00521 // Find minimal erase size supported by the region to which the address belongs to
00522 bd_size_t QSPIFBlockDevice::get_erase_size(bd_addr_t addr)
00523 {
00524     // If the legacy erase instruction is in use, the erase size is uniformly 4k
00525     if (_legacy_erase_instruction != QSPI_NO_INST) {
00526         return QSPIF_DEFAULT_SE_SIZE;
00527     }
00528 
00529     // Find region of current address
00530     int region = _utils_find_addr_region(addr);
00531 
00532     int min_region_erase_size = _min_common_erase_size;
00533     int8_t type_mask = ERASE_BITMASK_TYPE1;
00534     int i_ind = 0;
00535 
00536     if (region != -1) {
00537         type_mask = 0x01;
00538 
00539         for (i_ind = 0; i_ind < 4; i_ind++) {
00540             // loop through erase types bitfield supported by region
00541             if (_region_erase_types_bitfield[region] & type_mask) {
00542 
00543                 min_region_erase_size = _erase_type_size_arr[i_ind];
00544                 break;
00545             }
00546             type_mask = type_mask << 1;
00547         }
00548 
00549         if (i_ind == 4) {
00550             tr_error("No erase type was found for region addr");
00551         }
00552     }
00553 
00554     return (bd_size_t)min_region_erase_size;
00555 }
00556 
00557 bd_size_t QSPIFBlockDevice::size() const
00558 {
00559     return _device_size_bytes;
00560 }
00561 
00562 int QSPIFBlockDevice::get_erase_value() const
00563 {
00564     return 0xFF;
00565 }
00566 
00567 /********************************/
00568 /*   Different Device Csel Mgmt */
00569 /********************************/
00570 static PinName *generate_initialized_active_qspif_csel_arr()
00571 {
00572     PinName *init_arr = new PinName[QSPIF_MAX_ACTIVE_FLASH_DEVICES];
00573     for (int i_ind = 0; i_ind < QSPIF_MAX_ACTIVE_FLASH_DEVICES; i_ind++) {
00574         init_arr[i_ind] = NC;
00575     }
00576     return init_arr;
00577 }
00578 
00579 int QSPIFBlockDevice::add_new_csel_instance(PinName csel)
00580 {
00581     int status = 0;
00582     _devices_mutex->lock();
00583     if (_number_of_active_qspif_flash_csel >= QSPIF_MAX_ACTIVE_FLASH_DEVICES) {
00584         status = -2;
00585         goto exit_point;
00586     }
00587 
00588     // verify the device is unique(no identical csel already exists)
00589     for (int i_ind = 0; i_ind < QSPIF_MAX_ACTIVE_FLASH_DEVICES; i_ind++) {
00590         if (_active_qspif_flash_csel_arr[i_ind] == csel) {
00591             status = -1;
00592             goto exit_point;
00593         }
00594     }
00595 
00596     // Insert new csel into existing device list
00597     for (int i_ind = 0; i_ind < QSPIF_MAX_ACTIVE_FLASH_DEVICES; i_ind++) {
00598         if (_active_qspif_flash_csel_arr[i_ind] == NC) {
00599             _active_qspif_flash_csel_arr[i_ind] = csel;
00600             break;
00601         }
00602     }
00603     _number_of_active_qspif_flash_csel++;
00604 
00605 exit_point:
00606     _devices_mutex->unlock();
00607     return status;
00608 }
00609 
00610 int QSPIFBlockDevice::remove_csel_instance(PinName csel)
00611 {
00612     int status = -1;
00613     _devices_mutex->lock();
00614     // remove the csel from existing device list
00615     for (int i_ind = 0; i_ind < QSPIF_MAX_ACTIVE_FLASH_DEVICES; i_ind++) {
00616         if (_active_qspif_flash_csel_arr[i_ind] == csel) {
00617             _active_qspif_flash_csel_arr[i_ind] = NC;
00618             if (_number_of_active_qspif_flash_csel > 0) {
00619                 _number_of_active_qspif_flash_csel--;
00620             }
00621             status = 0;
00622             break;
00623         }
00624     }
00625     _devices_mutex->unlock();
00626     return status;
00627 }
00628 
00629 /*********************************************************/
00630 /********** SFDP Parsing and Detection Functions *********/
00631 /*********************************************************/
00632 int QSPIFBlockDevice::_sfdp_parse_sfdp_headers(uint32_t &basic_table_addr, size_t &basic_table_size,
00633                                                uint32_t &sector_map_table_addr, size_t &sector_map_table_size)
00634 {
00635     uint8_t sfdp_header[QSPIF_SFDP_HEADER_SIZE];
00636     uint8_t param_header[QSPIF_PARAM_HEADER_SIZE];
00637     size_t data_length = QSPIF_SFDP_HEADER_SIZE;
00638     bd_addr_t addr = 0x0;
00639 
00640     qspi_status_t status = _qspi_send_read_sfdp_command(addr, (char *) sfdp_header, data_length);
00641     if (status != QSPI_STATUS_OK) {
00642         tr_error("Init - Read SFDP Failed");
00643         return -1;
00644     }
00645 
00646     // Verify SFDP signature for sanity
00647     // Also check that major/minor version is acceptable
00648     if (!(memcmp(&sfdp_header[0], "SFDP", 4) == 0 && sfdp_header[5] == 1)) {
00649         tr_error("Init - Verification of SFDP signature and version failed");
00650         return -1;
00651     } else {
00652         tr_debug("Init - Verification of SFDP signature and version succeeded");
00653     }
00654 
00655     // Discover Number of Parameter Headers
00656     int number_of_param_headers = (int)(sfdp_header[6]) + 1;
00657     tr_debug("Number of Param Headers: %d", number_of_param_headers);
00658 
00659 
00660     addr += QSPIF_SFDP_HEADER_SIZE;
00661     data_length = QSPIF_PARAM_HEADER_SIZE;
00662 
00663     // Loop over Param Headers and parse them (currently supports Basic Param Table and Sector Region Map Table)
00664     for (int i_ind = 0; i_ind < number_of_param_headers; i_ind++) {
00665         status = _qspi_send_read_sfdp_command(addr, (char *) param_header, data_length);
00666         if (status != QSPI_STATUS_OK) {
00667             tr_error("Init - Read Param Table %d Failed", i_ind + 1);
00668             return -1;
00669         }
00670 
00671         // The SFDP spec indicates the standard table is always at offset 0
00672         // in the parameter headers, we check just to be safe
00673         if (param_header[2] != 1) {
00674             tr_error("Param Table %d - Major Version should be 1!", i_ind + 1);
00675             return -1;
00676         }
00677 
00678         if ((param_header[0] == 0) && (param_header[7] == 0xFF)) {
00679             // Found Basic Params Table: LSB=0x00, MSB=0xFF
00680             tr_debug("Found Basic Param Table at Table: %d", i_ind + 1);
00681             basic_table_addr = ((param_header[6] << 16) | (param_header[5] << 8) | (param_header[4]));
00682             // Supporting up to 64 Bytes Table (16 DWORDS)
00683             basic_table_size = ((param_header[3] * 4) < SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES) ? (param_header[3] * 4) : 64;
00684         } else if ((param_header[0] == 81) && (param_header[7] == 0xFF)) {
00685             // Found Sector Map Table: LSB=0x81, MSB=0xFF
00686             tr_debug("Found Sector Map Table at Table: %d", i_ind + 1);
00687             sector_map_table_addr = ((param_header[6] << 16) | (param_header[5] << 8) | (param_header[4]));
00688             sector_map_table_size = param_header[3] * 4;
00689         }
00690         addr += QSPIF_PARAM_HEADER_SIZE;
00691     }
00692 
00693     return 0;
00694 }
00695 
00696 int QSPIFBlockDevice::_sfdp_parse_basic_param_table(uint32_t basic_table_addr, size_t basic_table_size)
00697 {
00698     uint8_t param_table[SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES]; /* Up To 16 DWORDS = 64 Bytes */
00699 
00700     qspi_status_t status = _qspi_send_read_sfdp_command(basic_table_addr, (char *) param_table, basic_table_size);
00701     if (status != QSPI_STATUS_OK) {
00702         tr_error("Init - Read SFDP First Table Failed");
00703         return -1;
00704     }
00705 
00706     // Check that density is not greater than 4 gigabits (i.e. that addressing beyond 4 bytes is not required)
00707     if ((param_table[7] & 0x80) != 0) {
00708         tr_error("Init - verify flash density failed");
00709         return -1;
00710     }
00711 
00712     // Get device density (stored in bits - 1)
00713     uint32_t density_bits = ((param_table[7] << 24) |
00714                              (param_table[6] << 16) |
00715                              (param_table[5] << 8)  |
00716                              param_table[4]);
00717     _device_size_bytes = (density_bits + 1) / 8;
00718 
00719     // Set Page Size (QSPI write must be done on Page limits)
00720     _page_size_bytes = _sfdp_detect_page_size(param_table, basic_table_size);
00721 
00722     if (_sfdp_detect_reset_protocol_and_reset(param_table) != QSPIF_BD_ERROR_OK) {
00723         tr_error("Init - Detecting reset protocol/resetting failed");
00724         return -1;
00725     }
00726 
00727     // Detect and Set Erase Types
00728     bool shouldSetQuadEnable = false;
00729     bool is_qpi_mode = false;
00730 
00731     if (_sfdp_detect_erase_types_inst_and_size(param_table, basic_table_size) != 0) {
00732         tr_error("Init - Detecting erase types instructions/sizes failed");
00733         return -1;
00734     }
00735 
00736     // Detect and Set fastest Bus mode (default 1-1-1)
00737     _sfdp_detect_best_bus_read_mode(param_table, basic_table_size, shouldSetQuadEnable, is_qpi_mode);
00738     if (true == shouldSetQuadEnable) {
00739         if (_needs_fast_mode) {
00740             _enable_fast_mode();
00741         }
00742         // Set Quad Enable and QPI Bus modes if Supported
00743         tr_debug("Init - Setting Quad Enable");
00744         if (0 != _sfdp_set_quad_enabled(param_table)) {
00745             tr_error("Device supports Quad bus, but Quad Enable Failed");
00746             return -1;
00747         }
00748         if (true == is_qpi_mode) {
00749             tr_debug("Init - Setting QPI mode");
00750             _sfdp_set_qpi_enabled(param_table);
00751         }
00752     }
00753 
00754 #ifndef TARGET_NORDIC
00755     // 4 byte addressing is not currently supported with the Nordic QSPI controller
00756     if (_attempt_4_byte_addressing) {
00757         if (_sfdp_detect_and_enable_4byte_addressing(param_table, basic_table_size) != QSPIF_BD_ERROR_OK) {
00758             tr_error("Init - Detecting/enabling 4-byte addressing failed");
00759             return -1;
00760         }
00761     }
00762 #endif
00763 
00764     if (false == _is_mem_ready()) {
00765         tr_error("Init - _is_mem_ready Failed");
00766         return -1;
00767     }
00768 
00769     return 0;
00770 }
00771 
00772 int QSPIFBlockDevice::_sfdp_set_quad_enabled(uint8_t *basic_param_table_ptr)
00773 {
00774     uint8_t status_reg_setup[QSPI_MAX_STATUS_REGISTERS] = {0};
00775     uint8_t status_regs[QSPI_MAX_STATUS_REGISTERS] = {0};
00776 
00777     // QUAD Enable procedure is specified by 3 bits
00778     uint8_t qer_value = (basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_QER_BYTE] & 0x70) >> 4;
00779 
00780     switch (qer_value) {
00781         case 0:
00782             tr_debug("Device Does not Have a QE Bit, continue based on Read Inst");
00783             return 0;
00784         case 1:
00785         case 4:
00786             // Bit 1 of Status Reg 2
00787             _quad_enable_register_idx = 1;
00788             _quad_enable_bit = 1;
00789             tr_debug("Setting QE Bit, Bit 1 of Status Reg 2");
00790             break;
00791         case 2:
00792             // Bit 6 of Status Reg 1
00793             _quad_enable_register_idx = 0;
00794             _quad_enable_bit = 6;
00795             tr_debug("Setting QE Bit, Bit 6 of Status Reg 1");
00796             break;
00797         case 3:
00798             // Bit 7 of Status Reg 1
00799             _quad_enable_register_idx = 0;
00800             _quad_enable_bit = 7;
00801             _write_status_reg_2_inst = 0x3E;
00802             _read_status_reg_2_inst = 0x3F;
00803             tr_debug("Setting QE Bit, Bit 7 of Status Reg 1");
00804             break;
00805         case 5:
00806             // Bit 1 of status Reg 2
00807             _quad_enable_register_idx = 1;
00808             _quad_enable_bit = 1;
00809             tr_debug("Setting QE Bit, Bit 1 of Status Reg 2");
00810             break;
00811         default:
00812             tr_warning("Unsupported QER configuration");
00813             return 0;
00814     }
00815 
00816     if (_quad_enable_register_idx != QSPIF_NO_QUAD_ENABLE && _quad_enable_bit != QSPIF_NO_QUAD_ENABLE) {
00817         status_reg_setup[_quad_enable_register_idx] = 1 << _quad_enable_bit;
00818     }
00819 
00820     // Read existing status register values
00821     _qspi_read_status_registers(status_regs);
00822 
00823     // Set Bits for Quad Enable
00824     for (int i = 0; i < QSPI_MAX_STATUS_REGISTERS; i++) {
00825         status_regs[i] |= status_reg_setup[i];
00826     }
00827 
00828     // Write new Status Register Setup
00829     _qspi_write_status_registers(status_regs);
00830 
00831     if (false == _is_mem_ready()) {
00832         tr_error("Device not ready after write, failed");
00833         return -1;
00834     }
00835 
00836     // For Debug
00837     memset(status_regs, 0, QSPI_MAX_STATUS_REGISTERS);
00838     _qspi_read_status_registers(status_regs);
00839     if (((status_regs[0] & status_reg_setup[0]) | (status_regs[1] & status_reg_setup[1])) == 0) {
00840         tr_error("Status register not set correctly");
00841         return -1;
00842     }
00843 
00844     return 0;
00845 }
00846 
00847 int QSPIFBlockDevice::_sfdp_set_qpi_enabled(uint8_t *basic_param_table_ptr)
00848 {
00849     uint8_t config_reg[1];
00850 
00851     // QPI 4-4-4 Enable Procedure is specified in 5 Bits
00852     uint8_t en_seq_444_value = (((basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_MODE_EN_SEQ_BYTE] & 0xF0) >> 4) | ((
00853                                                                                                                            basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_MODE_EN_SEQ_BYTE + 1] & 0x01) << 4));
00854 
00855     switch (en_seq_444_value) {
00856         case 1:
00857         case 2:
00858             tr_debug("_sfdp_set_qpi_enabled - send command 38h");
00859             if (QSPI_STATUS_OK != _qspi_send_general_command(0x38, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) {
00860                 tr_error("_sfdp_set_qpi_enabled - send command 38h Failed");
00861             }
00862             break;
00863 
00864         case 4:
00865             tr_debug("_sfdp_set_qpi_enabled - send command 35h");
00866             if (QSPI_STATUS_OK != _qspi_send_general_command(0x35, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) {
00867                 tr_error("_sfdp_set_qpi_enabled - send command 35h Failed");
00868             }
00869             break;
00870 
00871         case 8:
00872             tr_debug("_sfdp_set_qpi_enabled - set config bit 6 and send command 71h");
00873             if (QSPI_STATUS_OK != _qspi_send_general_command(0x65, 0x800003, NULL, 0, (char *)config_reg, 1)) {
00874                 tr_error("_sfdp_set_qpi_enabled - set config bit 6 command 65h Failed");
00875             }
00876             config_reg[0] |= 0x40; //Set Bit 6
00877             if (QSPI_STATUS_OK != _qspi_send_general_command(0x71, 0x800003, NULL, 0, (char *)config_reg, 1)) {
00878                 tr_error("_sfdp_set_qpi_enabled - send command 71h Failed");
00879             }
00880             break;
00881 
00882         case 16:
00883             tr_debug("_sfdp_set_qpi_enabled - reset config bits 0-7 and send command 61h");
00884             if (QSPI_STATUS_OK != _qspi_send_general_command(0x65, QSPI_NO_ADDRESS_COMMAND, NULL, 0, (char *)config_reg, 1)) {
00885                 tr_error("_sfdp_set_qpi_enabled - send command 65h Failed");
00886             }
00887             config_reg[0] &= 0x7F; //Reset Bit 7 of CR
00888             if (QSPI_STATUS_OK != _qspi_send_general_command(0x61, QSPI_NO_ADDRESS_COMMAND, NULL, 0, (char *)config_reg, 1)) {
00889                 tr_error("_sfdp_set_qpi_enabled - send command 61 Failed");
00890             }
00891             break;
00892 
00893         default:
00894             tr_warning("_sfdp_set_qpi_enabled - Unsupported En Seq 444 configuration");
00895             break;
00896     }
00897     return 0;
00898 }
00899 
00900 int QSPIFBlockDevice::_sfdp_detect_page_size(uint8_t *basic_param_table_ptr, int basic_param_table_size)
00901 {
00902     unsigned int page_size = QSPIF_DEFAULT_PAGE_SIZE;
00903 
00904     if (basic_param_table_size > QSPIF_BASIC_PARAM_TABLE_PAGE_SIZE_BYTE) {
00905         // Page Size is specified by 4 Bits (N), calculated by 2^N
00906         int page_to_power_size = ((int)basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_PAGE_SIZE_BYTE]) >> 4;
00907         page_size = 1 << page_to_power_size;
00908         tr_debug("Detected Page Size: %d", page_size);
00909     } else {
00910         tr_debug("Using Default Page Size: %d", page_size);
00911     }
00912     return page_size;
00913 }
00914 
00915 int QSPIFBlockDevice::_sfdp_detect_erase_types_inst_and_size(uint8_t *basic_param_table_ptr, int basic_param_table_size)
00916 {
00917     uint8_t bitfield = 0x01;
00918 
00919     // Erase 4K Inst is taken either from param table legacy 4K erase or superseded by erase Instruction for type of size 4K
00920     if (basic_param_table_size > QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_1_SIZE_BYTE) {
00921         // Loop Erase Types 1-4
00922         for (int i_ind = 0; i_ind < 4; i_ind++) {
00923             _erase_type_inst_arr[i_ind] = QSPI_NO_INST; // Default for unsupported type
00924             _erase_type_size_arr[i_ind] = 1 << basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_1_SIZE_BYTE + 2 * i_ind]; // Size is 2^N where N is the table value
00925             tr_debug("Erase Type(A) %d - Inst: 0x%xh, Size: %d", (i_ind + 1), _erase_type_inst_arr[i_ind],
00926                      _erase_type_size_arr[i_ind]);
00927             if (_erase_type_size_arr[i_ind] > 1) {
00928                 // if size==1 type is not supported
00929                 _erase_type_inst_arr[i_ind] = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_ERASE_TYPE_1_BYTE + 2 * i_ind];
00930 
00931                 if ((_erase_type_size_arr[i_ind] < _min_common_erase_size) || (_min_common_erase_size == 0)) {
00932                     //Set default minimal common erase for signal region
00933                     _min_common_erase_size = _erase_type_size_arr[i_ind];
00934                 }
00935                 _region_erase_types_bitfield[0] |= bitfield; // If there's no region map, set region "0" types bitfield as default
00936             }
00937 
00938             tr_debug("Erase Type %d - Inst: 0x%xh, Size: %d", (i_ind + 1), _erase_type_inst_arr[i_ind],
00939                      _erase_type_size_arr[i_ind]);
00940             bitfield = bitfield << 1;
00941         }
00942     } else {
00943         tr_debug("SFDP erase types are not available - falling back to legacy 4k erase instruction");
00944 
00945         // 0xFF indicates that the legacy 4k erase instruction is not supported
00946         _legacy_erase_instruction = basic_param_table_ptr[QSPIF_BASIC_PARAM_4K_ERASE_TYPE_BYTE];
00947         if (_legacy_erase_instruction == 0xFF) {
00948             tr_error("_detectEraseTypesInstAndSize - Legacy 4k erase instruction not supported");
00949             return -1;
00950         }
00951     }
00952 
00953     return 0;
00954 }
00955 
00956 int QSPIFBlockDevice::_sfdp_detect_best_bus_read_mode(uint8_t *basic_param_table_ptr, int basic_param_table_size,
00957                                                       bool &set_quad_enable, bool &is_qpi_mode)
00958 {
00959     set_quad_enable = false;
00960     is_qpi_mode = false;
00961     uint8_t examined_byte;
00962 
00963     do { // compound statement is the loop body
00964 
00965         if (basic_param_table_size > QSPIF_BASIC_PARAM_TABLE_QPI_READ_SUPPORT_BYTE) {
00966             examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_QPI_READ_SUPPORT_BYTE];
00967 
00968             if (examined_byte & 0x10) {
00969                 // QPI 4-4-4 Supported
00970                 _read_instruction = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE];
00971                 set_quad_enable = true;
00972                 is_qpi_mode = true;
00973                 _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] & 0x1F;
00974                 uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_444_READ_INST_BYTE - 1] >> 5;
00975                 _alt_size = mode_cycles * 4;
00976                 tr_debug("Read Bus Mode set to 4-4-4, Instruction: 0x%xh", _read_instruction);
00977                 _address_width = QSPI_CFG_BUS_QUAD;
00978                 _data_width = QSPI_CFG_BUS_QUAD;
00979             }
00980         }
00981         is_qpi_mode = false;
00982         examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_FAST_READ_SUPPORT_BYTE];
00983         if (examined_byte & 0x20) {
00984             //  Fast Read 1-4-4 Supported
00985             _read_instruction = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE];
00986             set_quad_enable = true;
00987             _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] & 0x1F;
00988             uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_144_READ_INST_BYTE - 1] >> 5;
00989             _alt_size = mode_cycles * 4;
00990             _address_width = QSPI_CFG_BUS_QUAD;
00991             _data_width = QSPI_CFG_BUS_QUAD;
00992             tr_debug("Read Bus Mode set to 1-4-4, Instruction: 0x%xh", _read_instruction);
00993             break;
00994         }
00995 
00996         if (examined_byte & 0x40) {
00997             //  Fast Read 1-1-4 Supported
00998             _read_instruction = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE];
00999             set_quad_enable = true;
01000             _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] & 0x1F;
01001             uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_114_READ_INST_BYTE - 1] >> 5;
01002             _alt_size = mode_cycles;
01003             _data_width = QSPI_CFG_BUS_QUAD;
01004             tr_debug("Read Bus Mode set to 1-1-4, Instruction: 0x%xh", _read_instruction);
01005             break;
01006         }
01007         examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_QPI_READ_SUPPORT_BYTE];
01008         if (examined_byte & 0x01) {
01009             //  Fast Read 2-2-2 Supported
01010             _read_instruction = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE];
01011             _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] & 0x1F;
01012             uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_222_READ_INST_BYTE - 1] >> 5;
01013             _alt_size = mode_cycles * 2;
01014             _address_width = QSPI_CFG_BUS_DUAL;
01015             _data_width = QSPI_CFG_BUS_DUAL;
01016             tr_debug("Read Bus Mode set to 2-2-2, Instruction: 0x%xh", _read_instruction);
01017             break;
01018         }
01019 
01020         examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_FAST_READ_SUPPORT_BYTE];
01021         if (examined_byte & 0x10) {
01022             //  Fast Read 1-2-2 Supported
01023             _read_instruction = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE];
01024             _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] & 0x1F;
01025             uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_122_READ_INST_BYTE - 1] >> 5;
01026             _alt_size = mode_cycles * 2;
01027             _address_width = QSPI_CFG_BUS_DUAL;
01028             _data_width = QSPI_CFG_BUS_DUAL;
01029             tr_debug("Read Bus Mode set to 1-2-2, Instruction: 0x%xh", _read_instruction);
01030             break;
01031         }
01032         if (examined_byte & 0x01) {
01033             // Fast Read 1-1-2 Supported
01034             _read_instruction = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE];
01035             _dummy_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] & 0x1F;
01036             uint8_t mode_cycles = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_112_READ_INST_BYTE - 1] >> 5;
01037             _alt_size = mode_cycles;
01038             _data_width = QSPI_CFG_BUS_DUAL;
01039             tr_debug("Read Bus Mode set to 1-1-2, Instruction: 0x%xh", _read_instruction);
01040             break;
01041         }
01042         _read_instruction = QSPIF_INST_READ_DEFAULT;
01043         tr_debug("Read Bus Mode set to 1-1-1, Instruction: 0x%xh", _read_instruction);
01044     } while (false);
01045 
01046     return 0;
01047 }
01048 
01049 int QSPIFBlockDevice::_sfdp_detect_and_enable_4byte_addressing(uint8_t *basic_param_table_ptr, int basic_param_table_size)
01050 {
01051     int status = QSPIF_BD_ERROR_OK;
01052     qspi_status_t qspi_status = QSPI_STATUS_OK;
01053 
01054     // Always enable 4-byte addressing if possible
01055     if (basic_param_table_size > QSPIF_BASIC_PARAM_TABLE_4BYTE_ADDR_BYTE) {
01056         uint8_t examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_4BYTE_ADDR_BYTE];
01057 
01058         if (examined_byte & FOURBYTE_ADDR_ALWAYS_BITMASK) {
01059             // No need to do anything if 4-byte addressing is always enabled
01060             _address_size = QSPI_CFG_ADDR_SIZE_32;
01061         } else if (examined_byte & FOURBYTE_ADDR_B7_BITMASK) {
01062             // Issue instruction B7h to enable 4-byte addressing
01063             qspi_status = _qspi_send_general_command(0xB7, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0);
01064             status = (qspi_status == QSPI_STATUS_OK) ? QSPIF_BD_ERROR_OK : QSPIF_BD_ERROR_PARSING_FAILED;
01065             if (status == QSPIF_BD_ERROR_OK) {
01066                 _address_size = QSPI_CFG_ADDR_SIZE_32;
01067             }
01068         } else if (examined_byte & FOURBYTE_ADDR_B7_WREN_BITMASK) {
01069             // Issue WREN and then instruction B7h to enable 4-byte addressing
01070             if (_set_write_enable() == 0) {
01071                 qspi_status = _qspi_send_general_command(0xB7, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0);
01072                 status = (qspi_status == QSPI_STATUS_OK) ? QSPIF_BD_ERROR_OK : QSPIF_BD_ERROR_PARSING_FAILED;
01073 
01074                 if (status == QSPIF_BD_ERROR_OK) {
01075                     _address_size = QSPI_CFG_ADDR_SIZE_32;
01076                 }
01077             } else {
01078                 tr_error("Write enable failed");
01079                 status = QSPIF_BD_ERROR_WREN_FAILED;
01080             }
01081         } else if (examined_byte & FOURBYTE_ADDR_CONF_REG_BITMASK) {
01082             // Write 1 to bit 0 of a configuration register to enable 4-byte addressing
01083             // Write to register with instruction B1h, read from register with instruction B5h
01084             uint8_t conf_register = 0;
01085             qspi_status = _qspi_send_general_command(0xB5, QSPI_NO_ADDRESS_COMMAND, NULL, 0, (char *) &conf_register, 1);
01086             status = (qspi_status == QSPI_STATUS_OK) ? QSPIF_BD_ERROR_OK : QSPIF_BD_ERROR_PARSING_FAILED;
01087 
01088             if (status == QSPIF_BD_ERROR_OK) {
01089                 conf_register |= 0b00000001;
01090                 if (_set_write_enable() == 0) {
01091                     qspi_status_t qspi_status = _qspi_send_general_command(0xB1, QSPI_NO_ADDRESS_COMMAND, (char *) &conf_register, 1, NULL, 0);
01092                     status = (qspi_status == QSPI_STATUS_OK) ? QSPIF_BD_ERROR_OK : QSPIF_BD_ERROR_PARSING_FAILED;
01093 
01094                     if (status == QSPIF_BD_ERROR_OK) {
01095                         _address_size = QSPI_CFG_ADDR_SIZE_32;
01096                     }
01097                 } else {
01098                     tr_error("Write enable failed");
01099                     status = QSPIF_BD_ERROR_WREN_FAILED;
01100                 }
01101             }
01102         } else if (examined_byte & FOURBYTE_ADDR_BANK_REG_BITMASK) {
01103             // Write 1 to bit 7 of a bank register to enable 4-byte addressing
01104             // Write to register with instruction 17h, read from register with instruction 16h
01105             uint8_t to_write = 0b10000000;
01106             qspi_status = _qspi_send_general_command(0x17, QSPI_NO_ADDRESS_COMMAND, (char *) &to_write, 1, NULL, 0);
01107             status = (qspi_status == QSPI_STATUS_OK) ? QSPIF_BD_ERROR_OK : QSPIF_BD_ERROR_PARSING_FAILED;
01108             if (status == QSPIF_BD_ERROR_OK) {
01109                 _address_size = QSPI_CFG_ADDR_SIZE_32;
01110             }
01111         } else if (examined_byte & FOURBYTE_ADDR_EXT_ADDR_REG_BITMASK) {
01112             // Extended address register stores most significant byte of a 4-byte address
01113             // Instructions are sent with the lower 3 bytes of the address
01114             // Write to register with instruction C5h, read from register with instruction C8h
01115             _4byte_msb_reg_write_inst = 0xC5;
01116             _address_size = QSPI_CFG_ADDR_SIZE_24;
01117         } else {
01118             // Either part specific instructions are required to use 4-byte addressing or it isn't supported, so use 3-byte addressing instead
01119             tr_debug("_sfdp_detect_and_enable_4byte_addressing - 4-byte addressing not supported, falling back to 3-byte addressing");
01120             _address_size = QSPI_CFG_ADDR_SIZE_24;
01121         }
01122 
01123         if (_address_size == QSPI_CFG_ADDR_SIZE_32) {
01124             // Update 1-1-1 format to match new address size
01125             if (QSPI_STATUS_OK != _qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, _address_size, QSPI_CFG_BUS_SINGLE,
01126                                                          0, QSPI_CFG_BUS_SINGLE, 0)) {
01127                 tr_error("_qspi_configure_format failed");
01128                 status = QSPIF_BD_ERROR_DEVICE_ERROR;
01129             }
01130         }
01131     }
01132 
01133     return status;
01134 }
01135 
01136 int QSPIFBlockDevice::_sfdp_detect_reset_protocol_and_reset(uint8_t *basic_param_table_ptr)
01137 {
01138     int status = QSPIF_BD_ERROR_OK;
01139     uint8_t examined_byte = basic_param_table_ptr[QSPIF_BASIC_PARAM_TABLE_SOFT_RESET_BYTE];
01140 
01141     // Ignore bit indicating need to exit 0-4-4 mode - should not enter 0-4-4 mode from QSPIFBlockDevice
01142     if (examined_byte & SOFT_RESET_RESET_INST_BITMASK) {
01143         // Issue instruction 0xF0 to reset the device
01144         qspi_status_t qspi_status = _qspi_send_general_command(0xF0, QSPI_NO_ADDRESS_COMMAND, // Send reset instruction
01145                                                                NULL, 0, NULL, 0);
01146         status = (qspi_status == QSPI_STATUS_OK) ? QSPIF_BD_ERROR_OK : QSPIF_BD_ERROR_PARSING_FAILED;
01147     } else if (examined_byte & SOFT_RESET_ENABLE_AND_RESET_INST_BITMASK) {
01148         // Issue instruction 66h to enable resets on the device
01149         // Then issue instruction 99h to reset the device
01150         qspi_status_t qspi_status = _qspi_send_general_command(0x66, QSPI_NO_ADDRESS_COMMAND, // Send reset enable instruction
01151                                                                NULL, 0, NULL, 0);
01152         if (qspi_status == QSPI_STATUS_OK) {
01153             qspi_status = _qspi_send_general_command(0x99, QSPI_NO_ADDRESS_COMMAND, // Send reset instruction
01154                                                      NULL, 0, NULL, 0);
01155         }
01156         status = (qspi_status == QSPI_STATUS_OK) ? QSPIF_BD_ERROR_OK : QSPIF_BD_ERROR_PARSING_FAILED;
01157     } else {
01158         // Soft reset either is not supported or requires direct control over data lines
01159         status = QSPIF_BD_ERROR_PARSING_FAILED;
01160     }
01161 
01162     if (status == QSPIF_BD_ERROR_OK) {
01163         if (false == _is_mem_ready()) {
01164             tr_error("Device not ready, reset failed");
01165             status = QSPIF_BD_ERROR_READY_FAILED;
01166         }
01167     }
01168 
01169     return status;
01170 }
01171 
01172 int QSPIFBlockDevice::_sfdp_parse_sector_map_table(uint32_t sector_map_table_addr, size_t sector_map_table_size)
01173 {
01174     uint8_t sector_map_table[SFDP_DEFAULT_BASIC_PARAMS_TABLE_SIZE_BYTES]; /* Up To 16 DWORDS = 64 Bytes */
01175     uint32_t tmp_region_size = 0;
01176     int i_ind = 0;
01177     int prev_boundary = 0;
01178     // Default set to all type bits 1-4 are common
01179     int min_common_erase_type_bits = ERASE_BITMASK_ALL;
01180 
01181     qspi_status_t status = _qspi_send_read_sfdp_command(sector_map_table_addr, (char *) sector_map_table, sector_map_table_size);
01182     if (status != QSPI_STATUS_OK) {
01183         tr_error("Init - Read SFDP First Table Failed");
01184         return -1;
01185     }
01186 
01187     // Currently we support only Single Map Descriptor
01188     if (!((sector_map_table[0] & 0x3) == 0x03) && (sector_map_table[1]  == 0x0)) {
01189         tr_error("Sector Map - Supporting Only Single! Map Descriptor (not map commands)");
01190         return -1;
01191     }
01192 
01193     _regions_count = sector_map_table[2] + 1;
01194     if (_regions_count > QSPIF_MAX_REGIONS) {
01195         tr_error("Supporting up to %d regions, current setup to %d regions - fail",
01196                  QSPIF_MAX_REGIONS, _regions_count);
01197         return -1;
01198     }
01199 
01200     // Loop through Regions and set for each one: size, supported erase types, high boundary offset
01201     // Calculate minimum Common Erase Type for all Regions
01202     for (i_ind = 0; i_ind < _regions_count; i_ind++) {
01203         tmp_region_size = ((*((uint32_t *)&sector_map_table[(i_ind + 1) * 4])) >> 8) & 0x00FFFFFF; // bits 9-32
01204         _region_size_bytes[i_ind] = (tmp_region_size + 1) * 256; // Region size is 0 based multiple of 256 bytes;
01205         _region_erase_types_bitfield[i_ind] = sector_map_table[(i_ind + 1) * 4] & 0x0F; // bits 1-4
01206         min_common_erase_type_bits &= _region_erase_types_bitfield[i_ind];
01207         _region_high_boundary[i_ind] = (_region_size_bytes[i_ind] - 1) + prev_boundary;
01208         prev_boundary = _region_high_boundary[i_ind] + 1;
01209     }
01210 
01211     // Calc minimum Common Erase Size from min_common_erase_type_bits
01212     uint8_t type_mask = ERASE_BITMASK_TYPE1;
01213     for (i_ind = 0; i_ind < 4; i_ind++) {
01214         if (min_common_erase_type_bits & type_mask) {
01215             _min_common_erase_size = _erase_type_size_arr[i_ind];
01216             break;
01217         }
01218         type_mask = type_mask << 1;
01219     }
01220 
01221     if (i_ind == 4) {
01222         // No common erase type was found between regions
01223         _min_common_erase_size = 0;
01224     }
01225 
01226     return 0;
01227 }
01228 
01229 int QSPIFBlockDevice::_handle_vendor_quirks()
01230 {
01231     uint8_t vendor_device_ids[QSPI_RDID_DATA_LENGTH] = {0};
01232     /* Read Manufacturer ID (1byte), and Device ID (2bytes) */
01233     qspi_status_t status = _qspi_send_general_command(QSPIF_INST_RDID, QSPI_NO_ADDRESS_COMMAND,
01234                                                       NULL, 0,
01235                                                       (char *) vendor_device_ids, QSPI_RDID_DATA_LENGTH);
01236     if (QSPI_STATUS_OK != status) {
01237         tr_error("Read Vendor ID Failed");
01238         return -1;
01239     }
01240 
01241     tr_debug("Vendor device ID = 0x%x 0x%x 0x%x", vendor_device_ids[0], vendor_device_ids[1], vendor_device_ids[2]);
01242 
01243     switch (vendor_device_ids[0]) {
01244         case 0xbf:
01245             // SST devices come preset with block protection
01246             // enabled for some regions, issue global protection unlock to clear
01247             tr_debug("Applying quirks for SST");
01248             _clear_protection_method = QSPIF_BP_ULBPR;
01249             break;
01250         case 0xc2:
01251             // Macronix devices have several quirks:
01252             // 1. Have one status register and 2 config registers, with a nonstandard instruction for reading the config registers
01253             // 2. Require setting a "fast mode" bit in config register 2 to operate at higher clock rates
01254             // 3. Should never attempt to enable 4-byte addressing (it causes reads and writes to fail)
01255             tr_debug("Applying quirks for macronix");
01256             _needs_fast_mode = true;
01257             _num_status_registers = 3;
01258             _read_status_reg_2_inst = QSPIF_INST_RDCR;
01259             _attempt_4_byte_addressing = false;
01260             break;
01261     }
01262 
01263     return 0;
01264 }
01265 
01266 int QSPIFBlockDevice::_clear_block_protection()
01267 {
01268     uint8_t status_regs[QSPI_MAX_STATUS_REGISTERS] = {0};
01269 
01270     if (false == _is_mem_ready()) {
01271         tr_error("Device not ready, clearing block protection failed");
01272         return -1;
01273     }
01274     qspi_status_t status;
01275     switch (_clear_protection_method) {
01276         case QSPIF_BP_ULBPR:
01277             tr_debug("Clearing block protection via ULBPR");
01278             // SST devices come preset with block protection
01279             // enabled for some regions, issue global protection unlock to clear
01280             if (0 != _set_write_enable()) {
01281                 tr_error("Write enable failed");
01282                 return -1;
01283             }
01284             status = _qspi_send_general_command(QSPIF_INST_ULBPR, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0);
01285             if (QSPI_STATUS_OK != status) {
01286                 tr_error("Global block protection unlock failed");
01287                 return -1;
01288             }
01289             break;
01290         case QSPIF_BP_CLEAR_SR:
01291             // For all other devices, to clear the block protection bits clear all bits
01292             // in status register 1 that aren't the WIP or WEL bits, or the QE bit (if it is in SR 1)
01293             tr_debug("Clearing block protection via status register protection bits");
01294             status = _qspi_read_status_registers(status_regs);
01295             if (QSPI_STATUS_OK != status) {
01296                 tr_error("_clear_block_protection - Status register read failed");
01297                 return -1;
01298             }
01299             uint8_t status_mask = (QSPIF_STATUS_BIT_WIP | QSPIF_STATUS_BIT_WEL);
01300             if (_quad_enable_register_idx == 0) {
01301                 status_mask |= 1 << _quad_enable_bit;
01302             }
01303             status_regs[0] &= status_mask;
01304             status = _qspi_write_status_registers(status_regs);
01305             if (QSPI_STATUS_OK != status) {
01306                 tr_error("__clear_block_protection - Status register write failed");
01307                 return -1;
01308             }
01309             break;
01310     }
01311 
01312     if (false == _is_mem_ready()) {
01313         tr_error("Device not ready, clearing block protection failed");
01314         return -1;
01315     }
01316 
01317     return 0;
01318 }
01319 
01320 int QSPIFBlockDevice::_set_write_enable()
01321 {
01322     // Check Status Register Busy Bit to Verify the Device isn't Busy
01323     uint8_t status_value = 0;
01324     int status = -1;
01325 
01326     do {
01327         if (QSPI_STATUS_OK !=  _qspi_send_general_command(QSPIF_INST_WREN, QSPI_NO_ADDRESS_COMMAND, NULL, 0, NULL, 0)) {
01328             tr_error("Sending WREN command FAILED");
01329             break;
01330         }
01331 
01332         if (false == _is_mem_ready()) {
01333             tr_error("Device not ready, write failed");
01334             break;
01335         }
01336 
01337         if (QSPI_STATUS_OK != _qspi_send_general_command(QSPIF_INST_RSR1, QSPI_NO_ADDRESS_COMMAND,
01338                                                          NULL, 0,
01339                                                          (char *) &status_value, 1)) {
01340             tr_error("Reading Status Register 1 failed");
01341             break;
01342         }
01343 
01344         if ((status_value & QSPIF_STATUS_BIT_WEL) == 0) {
01345             tr_error("_set_write_enable failed - status register 1 value: %u", status_value);
01346             break;
01347         }
01348 
01349         status = 0;
01350     } while (false);
01351 
01352     return status;
01353 }
01354 
01355 int QSPIFBlockDevice::_enable_fast_mode()
01356 {
01357     tr_debug("enabling fast mode");
01358     MBED_ASSERT(_num_status_registers == 3); // Make sure the register for fast mode enable exists
01359     uint8_t status_reg[QSPI_MAX_STATUS_REGISTERS] = {0};
01360 
01361     // Bit 1 of config reg 2 (aka "status register 3" in our generic register representation)
01362     const int QER_REG_IDX = 2;
01363     const int QER_REG_VALUE = 0x2;
01364 
01365     // Configure  BUS Mode to 1_1_1 for all commands other than Read
01366     if (QSPI_STATUS_OK != _qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE,
01367                                                  0, QSPI_CFG_BUS_SINGLE, 0)) {
01368         tr_error("_qspi_configure_format failed");
01369         return -1;
01370 
01371     }
01372 
01373     if (QSPI_STATUS_OK == _qspi_read_status_registers(status_reg)) {
01374         tr_debug("Reading Config Register Success: value = 0x%x", status_reg[2]);
01375     } else {
01376         tr_error("Reading Config Register failed");
01377         return -1;
01378     }
01379 
01380     // Set Bits for Quad Enable
01381     status_reg[QER_REG_IDX] |= QER_REG_VALUE;
01382 
01383     // Write new Status Register Setup
01384     if (_set_write_enable() != 0) {
01385         tr_error("Write Enable failed");
01386         return -1;
01387     }
01388 
01389     if (QSPI_STATUS_OK == _qspi_write_status_registers(status_reg)) {
01390         tr_debug("fast mode enable - Writing Config Register Success: value = 0x%x",
01391                  (int)status_reg[2]);
01392     } else {
01393         tr_error("fast mode enable - Writing Config Register failed");
01394         return -1;
01395     }
01396 
01397     if (false == _is_mem_ready()) {
01398         tr_error("Device not ready after write, failed");
01399         return -1;
01400     }
01401 
01402     // For Debug
01403     memset(status_reg, 0, QSPI_MAX_STATUS_REGISTERS);
01404     if (QSPI_STATUS_OK == _qspi_read_status_registers(status_reg)) {
01405         tr_debug("Verifying Register Success: status = 0x%x config 1 = 0x%x config 2 = 0x%x", (int)status_reg[0], (int)status_reg[1], (int)status_reg[2]);
01406     } else {
01407         tr_error("Verifying Config Register failed");
01408         return -1;
01409     }
01410 
01411     return 0;
01412 }
01413 
01414 bool QSPIFBlockDevice::_is_mem_ready()
01415 {
01416     // Check Status Register Busy Bit to Verify the Device isn't Busy
01417     uint8_t status_value = 0;
01418     int retries = 0;
01419     bool mem_ready = true;
01420 
01421     do {
01422         rtos::ThisThread::sleep_for(1);
01423         retries++;
01424         //Read Status Register 1 from device
01425         if (QSPI_STATUS_OK != _qspi_send_general_command(QSPIF_INST_RSR1, QSPI_NO_ADDRESS_COMMAND,
01426                                                          NULL, 0,
01427                                                          (char *) &status_value, 1)) { // store received value in status_value
01428             tr_error("Reading Status Register failed");
01429         }
01430     } while ((status_value & QSPIF_STATUS_BIT_WIP) != 0 && retries < IS_MEM_READY_MAX_RETRIES);
01431 
01432     if ((status_value & QSPIF_STATUS_BIT_WIP) != 0) {
01433         tr_error("_is_mem_ready FALSE: status value = 0x%x ", status_value);
01434         mem_ready = false;
01435     }
01436     return mem_ready;
01437 }
01438 
01439 /*********************************************/
01440 /************* Utility Functions *************/
01441 /*********************************************/
01442 int QSPIFBlockDevice::_utils_find_addr_region(bd_size_t offset)
01443 {
01444     //Find the region to which the given offset belong to
01445     if ((offset > _device_size_bytes) || (_regions_count == 0)) {
01446         return -1;
01447     }
01448 
01449     if (_regions_count == 1) {
01450         return 0;
01451     }
01452 
01453     for (int i_ind = _regions_count - 2; i_ind >= 0; i_ind--) {
01454 
01455         if (offset > _region_high_boundary[i_ind]) {
01456             return (i_ind + 1);
01457         }
01458     }
01459     return -1;
01460 
01461 }
01462 
01463 int QSPIFBlockDevice::_utils_iterate_next_largest_erase_type(uint8_t &bitfield, int size, int offset, int boundry)
01464 {
01465     // Iterate on all supported Erase Types of the Region to which the offset belong to.
01466     // Iterates from highest type to lowest
01467     uint8_t type_mask = ERASE_BITMASK_TYPE4;
01468     int i_ind  = 0;
01469     int largest_erase_type = 0;
01470     for (i_ind = 3; i_ind >= 0; i_ind--) {
01471         if (bitfield & type_mask) {
01472             largest_erase_type = i_ind;
01473             if ((size > (int)(_erase_type_size_arr[largest_erase_type])) &&
01474                     ((boundry - offset) > (int)(_erase_type_size_arr[largest_erase_type]))) {
01475                 break;
01476             } else {
01477                 bitfield &= ~type_mask;
01478             }
01479         }
01480         type_mask = type_mask >> 1;
01481     }
01482 
01483     if (i_ind == 4) {
01484         tr_error("No erase type was found for current region addr");
01485     }
01486     return largest_erase_type;
01487 }
01488 
01489 /***************************************************/
01490 /*********** QSPI Driver API Functions *************/
01491 /***************************************************/
01492 qspi_status_t QSPIFBlockDevice::_qspi_set_frequency(int freq)
01493 {
01494     return _qspi.set_frequency(freq);
01495 }
01496 
01497 qspi_status_t QSPIFBlockDevice::_qspi_update_4byte_ext_addr_reg(bd_addr_t addr)
01498 {
01499     qspi_status_t status = QSPI_STATUS_OK;
01500     // Only update register if in the extended address register mode
01501     if (_4byte_msb_reg_write_inst != QSPI_NO_INST) {
01502         // Set register to the most significant byte of the address
01503         uint8_t most_significant_byte = addr >> 24;
01504         if (_set_write_enable() == 0) {
01505             status = _qspi.command_transfer(_4byte_msb_reg_write_inst, (int) QSPI_NO_ADDRESS_COMMAND,
01506                                             (char *) &most_significant_byte, 1,
01507                                             NULL, 0);
01508         } else {
01509             tr_error("Write enable failed");
01510             status = QSPI_STATUS_ERROR;
01511         }
01512     } else if ((_address_size != QSPI_CFG_ADDR_SIZE_32) && (addr != QSPI_NO_ADDRESS_COMMAND) && (addr >= (1 << 24))) {
01513         tr_error("Attempted to use 4-byte address but 4-byte addressing is not supported");
01514         status = QSPI_STATUS_ERROR;
01515     }
01516     return status;
01517 }
01518 
01519 qspi_status_t QSPIFBlockDevice::_qspi_send_read_command(qspi_inst_t read_inst, void *buffer,
01520                                                         bd_addr_t addr, bd_size_t size)
01521 {
01522     tr_debug("Inst: 0x%xh, addr: %llu, size: %llu", read_inst, addr, size);
01523 
01524     size_t buf_len = size;
01525 
01526     qspi_status_t status = _qspi_update_4byte_ext_addr_reg(addr);
01527     if (QSPI_STATUS_OK != status) {
01528         tr_error("QSPI Read - Updating 4-byte addressing extended address register failed");
01529         return status;
01530     }
01531 
01532     // Send read command to device driver
01533     // Read commands use the best bus mode supported by the part
01534     status = _qspi.configure_format(_inst_width, _address_width, _address_size, _address_width, // Alt width should be the same as address width
01535                                     _alt_size, _data_width, _dummy_cycles);
01536     if (QSPI_STATUS_OK != status) {
01537         tr_error("_qspi_configure_format failed");
01538         return status;
01539     }
01540 
01541     // Don't check the read status until after we've configured the format back to 1-1-1, to avoid leaving the interface in an
01542     // incorrect state if the read fails.
01543     status = _qspi.read(read_inst, (_alt_size == 0) ? -1 : QSPI_ALT_DEFAULT_VALUE, (unsigned int)addr, (char *)buffer, &buf_len);
01544 
01545     // All commands other than Read and RSFDP use default 1-1-1 bus mode (Program/Erase are constrained by flash memory performance more than bus performance)
01546     qspi_status_t format_status = _qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, _address_size, QSPI_CFG_BUS_SINGLE, 0, QSPI_CFG_BUS_SINGLE, 0);
01547     if (QSPI_STATUS_OK != format_status) {
01548         tr_error("_qspi_configure_format failed");
01549         return format_status;
01550     }
01551 
01552     if (QSPI_STATUS_OK != status) {
01553         tr_error("QSPI Read failed");
01554         return status;
01555     }
01556 
01557     return QSPI_STATUS_OK;
01558 }
01559 
01560 qspi_status_t QSPIFBlockDevice::_qspi_send_program_command(qspi_inst_t prog_inst, const void *buffer,
01561                                                            bd_addr_t addr, bd_size_t *size)
01562 {
01563     tr_debug("Inst: 0x%xh, addr: %llu, size: %llu", prog_inst, addr, *size);
01564 
01565     qspi_status_t status = _qspi_update_4byte_ext_addr_reg(addr);
01566     if (QSPI_STATUS_OK != status) {
01567         tr_error("QSPI Write - Updating 4-byte addressing extended address register failed");
01568         return status;
01569     }
01570 
01571     // Send program (write) command to device driver
01572     status = _qspi.write(prog_inst, -1, addr, (char *)buffer, (size_t *)size);
01573     if (QSPI_STATUS_OK != status) {
01574         tr_error("QSPI Write failed");
01575         return status;
01576     }
01577 
01578     return QSPI_STATUS_OK;
01579 }
01580 
01581 qspi_status_t QSPIFBlockDevice::_qspi_send_erase_command(qspi_inst_t erase_inst, bd_addr_t addr, bd_size_t size)
01582 {
01583     tr_debug("Inst: 0x%xh, addr: %llu, size: %llu", erase_inst, addr, size);
01584 
01585     qspi_status_t status = _qspi_update_4byte_ext_addr_reg(addr);
01586     if (QSPI_STATUS_OK != status) {
01587         tr_error("QSPI Erase - Updating 4-byte addressing extended address register failed");
01588         return status;
01589     }
01590 
01591     // Send erase command to driver
01592     status = _qspi.command_transfer(erase_inst, (int) addr, NULL, 0, NULL, 0);
01593 
01594     if (QSPI_STATUS_OK != status) {
01595         tr_error("QSPI Erase failed");
01596         return status;
01597     }
01598 
01599     return QSPI_STATUS_OK;
01600 }
01601 
01602 qspi_status_t QSPIFBlockDevice::_qspi_send_general_command(qspi_inst_t instruction, bd_addr_t addr,
01603                                                            const char *tx_buffer, bd_size_t tx_length,
01604                                                            const char *rx_buffer, bd_size_t rx_length)
01605 {
01606     tr_debug("Inst: 0x%xh, addr: %llu, tx length: %llu, rx length: %llu", instruction, addr, tx_length, rx_length);
01607 
01608     qspi_status_t status = _qspi_update_4byte_ext_addr_reg(addr);
01609     if (QSPI_STATUS_OK != status) {
01610         tr_error("QSPI Generic command - Updating 4-byte addressing extended address register failed");
01611         return status;
01612     }
01613 
01614     // Send a general command instruction to driver
01615     status = _qspi.command_transfer(instruction, (int)addr, tx_buffer, tx_length, rx_buffer, rx_length);
01616     if (QSPI_STATUS_OK != status) {
01617         tr_error("Sending Generic command: %x", instruction);
01618         return status;
01619     }
01620 
01621     return QSPI_STATUS_OK;
01622 }
01623 
01624 qspi_status_t QSPIFBlockDevice::_qspi_send_read_sfdp_command(bd_addr_t addr, void *rx_buffer, bd_size_t rx_length)
01625 {
01626     size_t rx_len = rx_length;
01627 
01628     // SFDP read instruction requires 1-1-1 bus mode with 8 dummy cycles and a 3-byte address
01629     qspi_status_t status = _qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_BUS_SINGLE, 0, QSPI_CFG_BUS_SINGLE, QSPIF_RSFDP_DUMMY_CYCLES);
01630     if (QSPI_STATUS_OK != status) {
01631         tr_error("_qspi_configure_format failed");
01632         return status;
01633     }
01634 
01635     // Don't check the read status until after we've configured the format back to 1-1-1, to avoid leaving the interface in an
01636     // incorrect state if the read fails.
01637     status = _qspi.read(QSPIF_INST_RSFDP, -1, (unsigned int) addr, (char *) rx_buffer, &rx_len);
01638 
01639     qspi_status_t format_status = _qspi.configure_format(QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_SINGLE, _address_size, QSPI_CFG_BUS_SINGLE, 0, QSPI_CFG_BUS_SINGLE, 0);
01640     // All commands other than Read and RSFDP use default 1-1-1 bus mode (Program/Erase are constrained by flash memory performance more than bus performance)
01641     if (QSPI_STATUS_OK != format_status) {
01642         tr_error("_qspi_configure_format failed");
01643         return format_status;
01644     }
01645 
01646     if (QSPI_STATUS_OK != status) {
01647         tr_error("Sending SFDP read instruction");
01648         return status;
01649     }
01650 
01651     return QSPI_STATUS_OK;
01652 }
01653 
01654 qspi_status_t QSPIFBlockDevice::_qspi_read_status_registers(uint8_t *reg_buffer)
01655 {
01656     // Read Status Register 1
01657     qspi_status_t status = _qspi_send_general_command(QSPIF_INST_RSR1, QSPI_NO_ADDRESS_COMMAND,
01658                                                       NULL, 0,
01659                                                       (char *) &reg_buffer[0], 1);
01660     if (QSPI_STATUS_OK == status) {
01661         tr_debug("Reading Status Register 1 Success: value = 0x%x", (int) reg_buffer[0]);
01662     } else {
01663         tr_error("Reading Status Register 1 failed");
01664         return status;
01665     }
01666 
01667     // Read Status Register 2 (and beyond, if applicable)
01668     unsigned int read_length = _num_status_registers - 1; // We already read status reg 1 above
01669     status = _qspi_send_general_command(_read_status_reg_2_inst, QSPI_NO_ADDRESS_COMMAND,
01670                                         NULL, 0,
01671                                         (char *) &reg_buffer[1], read_length);
01672     if (QSPI_STATUS_OK == status) {
01673         tr_debug("Reading Status Register 2 Success: value = 0x%x", (int) reg_buffer[1]);
01674         if (_num_status_registers > 2) {
01675             tr_debug("Reading Register 3 Success: value = 0x%x", (int) reg_buffer[2]);
01676         }
01677     } else {
01678         tr_error("Reading Status Register 2 failed");
01679         return status;
01680     }
01681 
01682     return QSPI_STATUS_OK;
01683 }
01684 
01685 qspi_status_t QSPIFBlockDevice::_qspi_write_status_registers(uint8_t *reg_buffer)
01686 {
01687     qspi_status_t status;
01688 
01689     if (_write_status_reg_2_inst == QSPI_NO_INST) {
01690         // Status registers are written on different data bytes of the same command
01691         if (_set_write_enable() != 0) {
01692             tr_error("Write Enable failed");
01693             return QSPI_STATUS_ERROR;
01694         }
01695         status = _qspi_send_general_command(QSPIF_INST_WSR1, QSPI_NO_ADDRESS_COMMAND,
01696                                             (char *) reg_buffer, _num_status_registers,
01697                                             NULL, 0);
01698         if (QSPI_STATUS_OK == status) {
01699             tr_debug("Writing Status Registers Success: reg 1 value = 0x%x, reg 2 value = 0x%x",
01700                      (int) reg_buffer[0], (int) reg_buffer[1]);
01701             if (_num_status_registers > 2) {
01702                 tr_debug("Writing Register 3 Success: value = 0x%x", (int) reg_buffer[2]);
01703             }
01704         } else {
01705             tr_error("Writing Status Registers failed");
01706             return status;
01707         }
01708     } else {
01709         // Status registers are written using different commands
01710         MBED_ASSERT(_num_status_registers == 2); // This flow doesn't support a nonstandard third status/config register
01711 
01712         // Write status register 1
01713         if (_set_write_enable() != 0) {
01714             tr_error("Write Enable failed");
01715             return QSPI_STATUS_ERROR;
01716         }
01717         status = _qspi_send_general_command(QSPIF_INST_WSR1, QSPI_NO_ADDRESS_COMMAND,
01718                                             (char *) &reg_buffer[0], 1,
01719                                             NULL, 0);
01720         if (QSPI_STATUS_OK == status) {
01721             tr_debug("Writing Status Register 1 Success: value = 0x%x",
01722                      (int) reg_buffer[0]);
01723         } else {
01724             tr_error("Writing Status Register 1 failed");
01725             return status;
01726         }
01727 
01728         // Write status register 2
01729         if (_set_write_enable() != 0) {
01730             tr_error("Write Enable failed");
01731             return QSPI_STATUS_ERROR;
01732         }
01733         status = _qspi_send_general_command(_write_status_reg_2_inst, QSPI_NO_ADDRESS_COMMAND,
01734                                             (char *) &reg_buffer[0], 1,
01735                                             NULL, 0);
01736         if (QSPI_STATUS_OK == status) {
01737             tr_debug("Writing Status Register 2 Success: value = 0x%x",
01738                      (int) reg_buffer[1]);
01739         } else {
01740             tr_error("Writing Status Register 2 failed");
01741             return status;
01742         }
01743     }
01744 
01745     return QSPI_STATUS_OK;
01746 }