Kenji Arai / mbed-dev4BLE

mbed library sources, mbed-dev only for TYBLE16

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drivers/SPI.cpp@180:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
180:96ed750bd169
Parent:
174:b96e65c34a4d 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2006-2013 ARM Limited
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16 #include "drivers/SPI.h"
<> 160:d5399cc887bb 17 #include "platform/mbed_critical.h"
<> 149:156823d33999 18
AnnaBridge 174:b96e65c34a4d 19 #if DEVICE_SPI_ASYNCH
AnnaBridge 174:b96e65c34a4d 20 #include "platform/mbed_sleep.h"
AnnaBridge 174:b96e65c34a4d 21 #endif
AnnaBridge 174:b96e65c34a4d 22
<> 149:156823d33999 23 #if DEVICE_SPI
<> 149:156823d33999 24
<> 149:156823d33999 25 namespace mbed {
<> 149:156823d33999 26
<> 149:156823d33999 27 #if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 28 CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
<> 149:156823d33999 29 #endif
<> 149:156823d33999 30
<> 149:156823d33999 31 SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
<> 149:156823d33999 32 _spi(),
<> 149:156823d33999 33 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 34 _irq(this),
<> 149:156823d33999 35 _usage(DMA_USAGE_NEVER),
Anna Bridge 180:96ed750bd169 36 _deep_sleep_locked(false),
<> 149:156823d33999 37 #endif
<> 149:156823d33999 38 _bits(8),
<> 149:156823d33999 39 _mode(0),
Kojto 170:19eb464bc2be 40 _hz(1000000),
Kojto 170:19eb464bc2be 41 _write_fill(SPI_FILL_CHAR) {
<> 149:156823d33999 42 // No lock needed in the constructor
<> 149:156823d33999 43
<> 149:156823d33999 44 spi_init(&_spi, mosi, miso, sclk, ssel);
Kojto 169:e3b6fe271b81 45 _acquire();
<> 149:156823d33999 46 }
<> 149:156823d33999 47
<> 149:156823d33999 48 void SPI::format(int bits, int mode) {
<> 149:156823d33999 49 lock();
<> 149:156823d33999 50 _bits = bits;
<> 149:156823d33999 51 _mode = mode;
Kojto 169:e3b6fe271b81 52 // If changing format while you are the owner than just
Kojto 169:e3b6fe271b81 53 // update format, but if owner is changed than even frequency should be
Kojto 169:e3b6fe271b81 54 // updated which is done by acquire.
Kojto 169:e3b6fe271b81 55 if (_owner == this) {
Kojto 169:e3b6fe271b81 56 spi_format(&_spi, _bits, _mode, 0);
Kojto 169:e3b6fe271b81 57 } else {
Kojto 169:e3b6fe271b81 58 _acquire();
Kojto 169:e3b6fe271b81 59 }
<> 149:156823d33999 60 unlock();
<> 149:156823d33999 61 }
<> 149:156823d33999 62
<> 149:156823d33999 63 void SPI::frequency(int hz) {
<> 149:156823d33999 64 lock();
<> 149:156823d33999 65 _hz = hz;
Kojto 169:e3b6fe271b81 66 // If changing format while you are the owner than just
Kojto 169:e3b6fe271b81 67 // update frequency, but if owner is changed than even frequency should be
Kojto 169:e3b6fe271b81 68 // updated which is done by acquire.
Kojto 169:e3b6fe271b81 69 if (_owner == this) {
Kojto 169:e3b6fe271b81 70 spi_frequency(&_spi, _hz);
Kojto 169:e3b6fe271b81 71 } else {
Kojto 169:e3b6fe271b81 72 _acquire();
Kojto 169:e3b6fe271b81 73 }
<> 149:156823d33999 74 unlock();
<> 149:156823d33999 75 }
<> 149:156823d33999 76
<> 149:156823d33999 77 SPI* SPI::_owner = NULL;
<> 149:156823d33999 78 SingletonPtr<PlatformMutex> SPI::_mutex;
<> 149:156823d33999 79
<> 149:156823d33999 80 // ignore the fact there are multiple physical spis, and always update if it wasnt us last
<> 149:156823d33999 81 void SPI::aquire() {
<> 149:156823d33999 82 lock();
<> 149:156823d33999 83 if (_owner != this) {
<> 149:156823d33999 84 spi_format(&_spi, _bits, _mode, 0);
<> 149:156823d33999 85 spi_frequency(&_spi, _hz);
<> 149:156823d33999 86 _owner = this;
<> 149:156823d33999 87 }
<> 149:156823d33999 88 unlock();
<> 149:156823d33999 89 }
<> 149:156823d33999 90
Kojto 169:e3b6fe271b81 91 // Note: Private function with no locking
Kojto 169:e3b6fe271b81 92 void SPI::_acquire() {
Kojto 169:e3b6fe271b81 93 if (_owner != this) {
Kojto 169:e3b6fe271b81 94 spi_format(&_spi, _bits, _mode, 0);
Kojto 169:e3b6fe271b81 95 spi_frequency(&_spi, _hz);
Kojto 169:e3b6fe271b81 96 _owner = this;
Kojto 169:e3b6fe271b81 97 }
Kojto 169:e3b6fe271b81 98 }
Kojto 169:e3b6fe271b81 99
<> 149:156823d33999 100 int SPI::write(int value) {
<> 149:156823d33999 101 lock();
Kojto 169:e3b6fe271b81 102 _acquire();
<> 149:156823d33999 103 int ret = spi_master_write(&_spi, value);
<> 149:156823d33999 104 unlock();
<> 149:156823d33999 105 return ret;
<> 149:156823d33999 106 }
<> 149:156823d33999 107
AnnaBridge 167:e84263d55307 108 int SPI::write(const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length) {
AnnaBridge 167:e84263d55307 109 lock();
Kojto 169:e3b6fe271b81 110 _acquire();
Kojto 170:19eb464bc2be 111 int ret = spi_master_block_write(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, _write_fill);
AnnaBridge 167:e84263d55307 112 unlock();
AnnaBridge 167:e84263d55307 113 return ret;
AnnaBridge 167:e84263d55307 114 }
AnnaBridge 167:e84263d55307 115
<> 149:156823d33999 116 void SPI::lock() {
<> 149:156823d33999 117 _mutex->lock();
<> 149:156823d33999 118 }
<> 149:156823d33999 119
<> 149:156823d33999 120 void SPI::unlock() {
<> 149:156823d33999 121 _mutex->unlock();
<> 149:156823d33999 122 }
<> 149:156823d33999 123
Kojto 170:19eb464bc2be 124 void SPI::set_default_write_value(char data) {
Kojto 170:19eb464bc2be 125 lock();
Kojto 170:19eb464bc2be 126 _write_fill = data;
Kojto 170:19eb464bc2be 127 unlock();
Kojto 170:19eb464bc2be 128 }
Kojto 170:19eb464bc2be 129
<> 149:156823d33999 130 #if DEVICE_SPI_ASYNCH
<> 149:156823d33999 131
<> 149:156823d33999 132 int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
<> 149:156823d33999 133 {
<> 149:156823d33999 134 if (spi_active(&_spi)) {
<> 149:156823d33999 135 return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
<> 149:156823d33999 136 }
<> 149:156823d33999 137 start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
<> 149:156823d33999 138 return 0;
<> 149:156823d33999 139 }
<> 149:156823d33999 140
<> 149:156823d33999 141 void SPI::abort_transfer()
<> 149:156823d33999 142 {
<> 149:156823d33999 143 spi_abort_asynch(&_spi);
Anna Bridge 180:96ed750bd169 144 unlock_deep_sleep();
<> 149:156823d33999 145 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 146 dequeue_transaction();
<> 149:156823d33999 147 #endif
<> 149:156823d33999 148 }
<> 149:156823d33999 149
<> 149:156823d33999 150
<> 149:156823d33999 151 void SPI::clear_transfer_buffer()
<> 149:156823d33999 152 {
<> 149:156823d33999 153 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 154 _transaction_buffer.reset();
<> 149:156823d33999 155 #endif
<> 149:156823d33999 156 }
<> 149:156823d33999 157
<> 149:156823d33999 158 void SPI::abort_all_transfers()
<> 149:156823d33999 159 {
<> 149:156823d33999 160 clear_transfer_buffer();
<> 149:156823d33999 161 abort_transfer();
<> 149:156823d33999 162 }
<> 149:156823d33999 163
<> 149:156823d33999 164 int SPI::set_dma_usage(DMAUsage usage)
<> 149:156823d33999 165 {
<> 149:156823d33999 166 if (spi_active(&_spi)) {
<> 149:156823d33999 167 return -1;
<> 149:156823d33999 168 }
<> 149:156823d33999 169 _usage = usage;
<> 149:156823d33999 170 return 0;
<> 149:156823d33999 171 }
<> 149:156823d33999 172
<> 149:156823d33999 173 int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
<> 149:156823d33999 174 {
<> 149:156823d33999 175 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 176 transaction_t t;
<> 149:156823d33999 177
<> 149:156823d33999 178 t.tx_buffer = const_cast<void *>(tx_buffer);
<> 149:156823d33999 179 t.tx_length = tx_length;
<> 149:156823d33999 180 t.rx_buffer = rx_buffer;
<> 149:156823d33999 181 t.rx_length = rx_length;
<> 149:156823d33999 182 t.event = event;
<> 149:156823d33999 183 t.callback = callback;
<> 149:156823d33999 184 t.width = bit_width;
<> 149:156823d33999 185 Transaction<SPI> transaction(this, t);
<> 149:156823d33999 186 if (_transaction_buffer.full()) {
<> 149:156823d33999 187 return -1; // the buffer is full
<> 149:156823d33999 188 } else {
<> 149:156823d33999 189 core_util_critical_section_enter();
<> 149:156823d33999 190 _transaction_buffer.push(transaction);
<> 149:156823d33999 191 if (!spi_active(&_spi)) {
<> 149:156823d33999 192 dequeue_transaction();
<> 149:156823d33999 193 }
<> 149:156823d33999 194 core_util_critical_section_exit();
<> 149:156823d33999 195 return 0;
<> 149:156823d33999 196 }
<> 149:156823d33999 197 #else
<> 149:156823d33999 198 return -1;
<> 149:156823d33999 199 #endif
<> 149:156823d33999 200 }
<> 149:156823d33999 201
<> 149:156823d33999 202 void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
<> 149:156823d33999 203 {
Anna Bridge 180:96ed750bd169 204 lock_deep_sleep();
Kojto 169:e3b6fe271b81 205 _acquire();
<> 149:156823d33999 206 _callback = callback;
<> 149:156823d33999 207 _irq.callback(&SPI::irq_handler_asynch);
<> 149:156823d33999 208 spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
<> 149:156823d33999 209 }
<> 149:156823d33999 210
Anna Bridge 180:96ed750bd169 211 void SPI::lock_deep_sleep()
Anna Bridge 180:96ed750bd169 212 {
Anna Bridge 180:96ed750bd169 213 if (_deep_sleep_locked == false) {
Anna Bridge 180:96ed750bd169 214 sleep_manager_lock_deep_sleep();
Anna Bridge 180:96ed750bd169 215 _deep_sleep_locked = true;
Anna Bridge 180:96ed750bd169 216 }
Anna Bridge 180:96ed750bd169 217 }
Anna Bridge 180:96ed750bd169 218
Anna Bridge 180:96ed750bd169 219 void SPI::unlock_deep_sleep()
Anna Bridge 180:96ed750bd169 220 {
Anna Bridge 180:96ed750bd169 221 if (_deep_sleep_locked == true) {
Anna Bridge 180:96ed750bd169 222 sleep_manager_unlock_deep_sleep();
Anna Bridge 180:96ed750bd169 223 _deep_sleep_locked = false;
Anna Bridge 180:96ed750bd169 224 }
Anna Bridge 180:96ed750bd169 225 }
Anna Bridge 180:96ed750bd169 226
<> 149:156823d33999 227 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 228
<> 149:156823d33999 229 void SPI::start_transaction(transaction_t *data)
<> 149:156823d33999 230 {
<> 149:156823d33999 231 start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
<> 149:156823d33999 232 }
<> 149:156823d33999 233
<> 149:156823d33999 234 void SPI::dequeue_transaction()
<> 149:156823d33999 235 {
<> 149:156823d33999 236 Transaction<SPI> t;
<> 149:156823d33999 237 if (_transaction_buffer.pop(t)) {
<> 149:156823d33999 238 SPI* obj = t.get_object();
<> 149:156823d33999 239 transaction_t* data = t.get_transaction();
<> 149:156823d33999 240 obj->start_transaction(data);
<> 149:156823d33999 241 }
<> 149:156823d33999 242 }
<> 149:156823d33999 243
<> 149:156823d33999 244 #endif
<> 149:156823d33999 245
<> 149:156823d33999 246 void SPI::irq_handler_asynch(void)
<> 149:156823d33999 247 {
<> 149:156823d33999 248 int event = spi_irq_handler_asynch(&_spi);
<> 149:156823d33999 249 if (_callback && (event & SPI_EVENT_ALL)) {
Anna Bridge 180:96ed750bd169 250 unlock_deep_sleep();
<> 149:156823d33999 251 _callback.call(event & SPI_EVENT_ALL);
<> 149:156823d33999 252 }
<> 149:156823d33999 253 #if TRANSACTION_QUEUE_SIZE_SPI
<> 149:156823d33999 254 if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
<> 149:156823d33999 255 // SPI peripheral is free (event happend), dequeue transaction
<> 149:156823d33999 256 dequeue_transaction();
<> 149:156823d33999 257 }
<> 149:156823d33999 258 #endif
<> 149:156823d33999 259 }
<> 149:156823d33999 260
<> 149:156823d33999 261 #endif
<> 149:156823d33999 262
<> 149:156823d33999 263 } // namespace mbed
<> 149:156823d33999 264
<> 149:156823d33999 265 #endif